Symmetric module
 Logical converter / 2248034Device has eleven majority elements, four information inputs, two adjustment inputs. |
 High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. |
|
High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751 System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. |
|
Logical converter / 2248034 Device has eleven majority elements, four information inputs, two adjustment inputs. |
 Symmetric module / 2248035Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered |
 Logical calculator / 2248036Device has 2n AND elements, n OR elements, n D-triggers. |
 Logic module / 2249844Logic module has And element, first, second majority elements, OR element, three data inputs and two adjustment inputs. |
 Logical processor / 2251142Device has majority elements, grouped in V+1 group in such a way, that i-numbered (I = 1, V) and V+1 numbered groups contain respectively n and V-1 majority element groups. |
 Singular signals number identifier / 2256211Identifier has twenty two cells, each of which has two inputs, two outputs, AND, XOR elements, while all cells are grouped as a matrix of four rows and seven columns in such a way, that i-numbered (i=1,4) string and j-numbered (j=1,4) column contain respectively 8-i and j cells. |
 Logic calculator / 2257608Device has n computing cells, each of which has AND element, OR element, D-trigger. |
 Logical processor / 2260205Device has closing and opening keys, register and calculating cells, each of which consists of OR element, AND element. |
 Unary signals adder / 2260836Device has n calculating cells, each of which consists of AND element and XOR element, n AND elements, n D-triggers. |
FIELD: computers.
SUBSTANCE: module has n D-triggers, n AND elements and n OR elements, while output of i-numbered And element is connected to first input of i-numbered OR element, connected by second input to data input of i-numbered D-trigger, setting input and clock input of which are connected respectively to first and second control inputs of module, connected by i-numbered information input to first input of i-numbered And element, second input of which is connected to non-inverse output of i-numbered D-trigger, output of each previous OR element is connected to second input of following OR element, and second input of first and output of n-numbered OR elements are connected respectively to zero potential bus and module output.
EFFECT: simplified adjustment.
2 dwg
The invention relates to computer technology and can be used for building automation, functional units of the control systems and other
Known symmetric modules (see, for example, in figure 1 the description of the invention to the patent of the Russian Federation 2171496, CL G 06 G 7/52, 2001), which can be used to play any of the four simple symmetric Boolean functions that depend on four arguments - input binary signals x1,x2,x3,x4∈ {0,1}.
For the reason that impede the achievement of specified following technical result when using the well-known symmetric modules is limited functionality due to the fact that not played any of the n simple symmetric Boolean functions that depend on n arguments - input binary signals x1,... ,xn∈{0,1}.
The closest device to the same destination to the claimed invention by the combination of features is adopted for the prototype, the symmetric module (figure 1 in the description of the invention to the patent of the Russian Federation 2192044, CL G 06 G 7/52, 2002), which contains the output and can be used to play any of the n simple symmetric Boolean functions that depend on n arguments - input binary signals x1,... ,xn∈{0,1}.
The reason, letting the th achievement of specified following technical result when using prototype is difficult to configure due to the fact that its implementation requires nV+V-1 control signals,
wherem=0,5(n+1) (m=0,5n) for odd (even) n.
The technical result of the invention is to simplify the setup to reproduce any of the n simple symmetric Boolean functions that depend on n arguments - input binary signals, by ensuring its implementation by means of two control signals.
This technical result in the implementation of the invention is achieved by the fact that in a symmetric module that contains the exit, the peculiarity lies in the fact that it introduced n D-triggers n elements And n elements “OR”, and the output of the i-roelement And connected to the first input of the i-th element “OR”connected as a second input to the data input of the i-th D-flip-flop, the input set and the clock input of which is connected respectively with the first and second control inputs of the symmetric module, connected to the i-th information input to the first input of the i-th element And the second input connected to reinvestiruet output of the i-th D-flip-flop, the output of each previous element OR is connected to the second input of the subsequent element “OR”, and second input and first output the n-th elements “OR” connected, respectively, with zero bus p. the potential and the output of the symmetric module.
Figure 1 and figure 2 presents respectively the proposed scheme symmetric module and timing diagrams of control signals.
Symmetric module contains output 1, D-2 triggers1,... ,2nelements “And” 31,... ,3nand elements “OR” 41,... ,4nand the output element 3iconnected to the first input element 4iconnected to the second input to the data input of D-flip-flop 2ithe input set and the clock input of which is connected respectively with the first and second control inputs of the symmetric module, connected to the i-th information input to the first input element 3ithe second input of which is connected to reinvestiruet output of D-flip-flop 2ithe output of element 4k
connected to the second input element 4k+1and the second input element 41and the output element 4nconnected respectively with the bus zero potential and the output 1 of the symmetric module.
The work of the proposed symmetric module is as follows. On his first,... , n-th information and the first, second control inputs are given correspondingly binary signals x1,... ,xn∈{0,1} and pulse signals y1,y2∈{0,1} (figure 2). Then the signal at the output of the element 4i will be determined by a recurrent expression
wherethere are a number of time tj(figure 2); W(i-1)0=1; W0j=0. The period T of the signal y2must satisfy the condition T>Δ t, where Δ t=Δ tTp+Δ tAnd+nΔ /torand Δ tTpthat Δ tandand Δ torthere is duration of the delay introduced respectively D-trigger 2ielements 3iand 4i. The following table summarizes the value of the expression (1) when n=4.
Thus, the proposed symmetric module output 1 reproduces the function
where τ1,... ,τnthere is a simple symmetric Boolean functions (see page 126 in the book Pospelov D.A. Logical methods of analysis and synthesis schemes. M: Energy, 1974.). According to (2) and figure 2 module configuration (1) on playback functions τjis the appropriate number m=j-1 pulse signal y2after pre-setting to its original state by the pulse signal y1.
The above data allow us to conclude that the proposed symmetric module reproduces any of the n simple symmetric Boolean functions that depend on n arguments of the input binary signal is fishing, and is more simple in comparison with the prototype setup, as it is implemented using only two control signals.
Symmetric module designed to play any of the n simple symmetric Boolean functions that depend on n arguments - input binary signal containing the output, characterized in that it introduced n D-triggers n elements And n elements “OR”, and the output of the i-thelement And connected to the first input of the i-th element “OR”connected as a second input to the data input of the i-th D-flip-flop, the input set and the clock input of which is connected respectively with the first and second control inputs of the symmetric module, connected to the i-th information input to the first input of the i-th element And the second input connected to reinvestiruet output of the i-th D-flip-flop, the output of each previous element OR is connected to the second input of the subsequent element “OR”, and second input and first output the n-th elements “OR” are connected respectively to the bus zero potential and the output of the symmetric module.