Logical processor
 Logic calculator / 2257608Device has n computing cells, each of which has AND element, OR element, D-trigger. |
 Singular signals number identifier / 2256211Identifier has twenty two cells, each of which has two inputs, two outputs, AND, XOR elements, while all cells are grouped as a matrix of four rows and seven columns in such a way, that i-numbered (i=1,4) string and j-numbered (j=1,4) column contain respectively 8-i and j cells. |
 Logical processor / 2251142Device has majority elements, grouped in V+1 group in such a way, that i-numbered (I = 1, V) and V+1 numbered groups contain respectively n and V-1 majority element groups. |
 Logic module / 2249844Logic module has And element, first, second majority elements, OR element, three data inputs and two adjustment inputs. |
 Logical calculator / 2248036Device has 2n AND elements, n OR elements, n D-triggers. |
 Symmetric module / 2248035Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered |
 Logical converter / 2248034Device has eleven majority elements, four information inputs, two adjustment inputs. |
 High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. |
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High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751 System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. |
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Logical converter / 2248034 Device has eleven majority elements, four information inputs, two adjustment inputs. |
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Symmetric module / 2248035 Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered |
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Logical calculator / 2248036 Device has 2n AND elements, n OR elements, n D-triggers. |
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Logic module / 2249844 Logic module has And element, first, second majority elements, OR element, three data inputs and two adjustment inputs. |
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Logical processor / 2251142 Device has majority elements, grouped in V+1 group in such a way, that i-numbered (I = 1, V) and V+1 numbered groups contain respectively n and V-1 majority element groups. |
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Singular signals number identifier / 2256211 Identifier has twenty two cells, each of which has two inputs, two outputs, AND, XOR elements, while all cells are grouped as a matrix of four rows and seven columns in such a way, that i-numbered (i=1,4) string and j-numbered (j=1,4) column contain respectively 8-i and j cells. |
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Logic calculator / 2257608 Device has n computing cells, each of which has AND element, OR element, D-trigger. |
 Logical processor / 2260205Device has closing and opening keys, register and calculating cells, each of which consists of OR element, AND element. |
 Unary signals adder / 2260836Device has n calculating cells, each of which consists of AND element and XOR element, n AND elements, n D-triggers. |
FIELD: computer science.
SUBSTANCE: device has closing and opening keys, register and calculating cells, each of which consists of OR element, AND element.
EFFECT: broader functional capabilities.
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The invention relates to computer technology and can be used for building automation, functional units of the control systems and other
Known logical processors (see, for example, in figure 1 the description of the invention to the patent of the Russian Federation 2124754, CL G 06 G 7/52, 1999), which can be used to implement any of the three simple symmetric Boolean functions that depend on three arguments - input binary signals x1, x2x3∈{0,1}.
For the reason that impede the achievement of specified following technical result when using known logical processors include limited functionality due to the fact that there is no parallel implementation n simple symmetric Boolean functions that depend on n {n≥2) arguments input binary signals x1,..., xn∈{0,1}.
The closest device to the same destination to the claimed invention by the combination of features is adopted for the prototype logical processor (figure 1 in the description of the invention to the patent of the Russian Federation 2171496, CL G 06 G 7/52, 2001), which has two ends and two break key and can be used to implement any of the four simple symmetric Boolean functions that depend on four arguments - input binary signals x1, x2, x34∈{0,1}.
For the reason that impede the achievement of specified following technical result when using the prototype include limited functionality due to the fact that there is no parallel implementation n simple symmetric Boolean functions that depend on n (n≥2) arguments input binary signals x1,..., xn∈{0,1}.
The technical result of the invention is the extension of functionality by providing a parallel implementation of n simple symmetric Boolean functions that depend on n (n≥2) arguments input binary signals.
This technical result in the implementation of the invention is achieved by the fact that a logical processor that has two ends and two break key feature is that it introduced n-2 guard and n-2 NC key register and a computational cell, each of which contains an element "OR"connected first, second inputs and output respectively to its first, second inputs and a first output, and element And connected first, second inputs and output respectively to its first, second inputs and a second output, and the input of the i-thNC key connected respectively with the output of the i-th end key and the volume is inanime i-th output of the register, i-th output of a logical processor connected first, second configuration and the i-th information inputs respectively to the control input of all keys input register entries and the input of the i-th trailing key, all computational cells are grouped into two groups so that the first and second groups contain, respectively, g and k of computational cells, the first and second inputs of the r-th
a computational cell of the first group are connected respectively to the outputs of the (2r-1)-th and (2r)-th guard keys, the first and second outputs of the m-th
a computational cell of the second group are respectively connected to the (2m)-th and {2m+1)-th inputs of the register, the second output of the r-th
the previous and first output (r+1)-th computing cells of the first group are connected respectively with the first and second inputs of the r-th computational cell of the second group and the first output of the first computational cell of the first group connected to the first input of the register, in addition, when n is even k=0,5n-1 and the second output g-th (g=0,5n) computational cell of the first group is connected to the n-th input of the register, and for odd n the first and second inputs of the k-th (k=0.5(n-1)) a computational cell of the second group are connected respectively with the second output of the g-th (g=0,5n-1)) of a computational cell of the first group and the output of the n-th trailing key.
Figure 1 and IG presents respectively the proposed scheme logical processor (for example, when n=5) and time diagrams of signals settings.
Logical processor contains trailing and disconnect keys 11,..., 1nand 21,..., 2n; computational cell 311,..., 3g1, 312,..., 3k2where g=k=0.5(n-1) or g=0,5n, k=0,5n-1 for odd or even n, respectively (n≥2); register 4. Each computational cell contains an element "OR" 5, is connected first, second inputs and output respectively to its first, second inputs and a first output, and element "And" 6, is connected first, second inputs and output respectively to its first, second inputs and second outputs. Output and input key 2iconnected respectively with the output key 1iand United the i-th output of the register 4, the i-th output of a logical processor connected first, second configuration and the i-th information inputs respectively to the control input of all keys input register entries 4 and the input key 1ithe first and second inputs of the cell
connected respectively to the outputs of keys 12r-1and 12rthe first and second outputs of the cell
connected respectively to the (2m)th and (2m+1)-th inputs of the register 4, the second output of the r-th
previous cell of the first group and the first output cell 3(r+1)1 r2and the first output cell 311connected to the first input register 4, in addition, when n is even the second output of the cell 3g1connected to the n-th input of the register 4, and for odd n the first and second inputs of the cell 3k2connected respectively with the second cell output 3g1and access key 1n.
The work of the proposed logical processor is as follows. On his first,..., n-th (n≥2) information and first, second tuning inputs are given correspondingly binary signals x1,..., xn∈{0,1} and y1, y2∈{0,1} (figure 2). The data is loaded in the register 4 is on the positive difference (from "0" to "1") signal at the input record, so the register can be hardware implemented using, for example, chip TO IR. If the control input keys 1i, 2ithere is a logical "1" or a logical "0", then the key 1irespectively closed or open, and the key 2irespectively open or closed. Then the signals on the first, an arbitrary odd and arbitrary odd (except the first) the outputs of the proposed processor will be determined accordingly recurrent expressions Z1j=Z1(j-1)∨Z2(j-1), Zpj=Z(p-1)(j-1)Zp(j-1)∨Z(p+1)(j-1)∨Z(p+2)(j-1)and Zqj=Z (q-2)(j-1)Z(q-1)(j-1)(Zq(j-1)∨Z(q+1)(j-1)), where the characters ∨ and · designated operations "OR" and "And";
there are a number of time tj(figure 2), here ν=0,5n (ν=0,5(n+1)) for even (odd) n; Zi0=xi. Duration Δt a high level signal at1and the period T of the signal y2must satisfy the conditions Δt≥2ΔtIand T≥ΔtP+2ΔtIwhere ΔtPand ΔtIthere is duration of the delay introduced respectively by the register and computational cell. The following table is obtained according to the specified recurrent expression ratio determining signals on the first,..., n-th outputs of the proposed processor when n=5.
Thus, at the outputs of the proposed processor when j=ν
Z1ν=τ1=x1∨x2∨...∨xn;
Z2ν=τ2=x1x2∨x1x3∨...∨xn-1xn;
................
Znν=τn=x1x2...xn,
where τ1,...,τnthere is a simple symmetric Boolean functions (see str in the book Pospelov D.A. Logical methods of analysis and synthesis schemes. M: Energy, 1974).
The above information can help to make the conclusion is, the proposed logical processor has a wider compared to the prototype functionality, as it provides a parallel implementation of n simple symmetric Boolean functions that depend on n (n≥2) arguments input binary signals.
Logical processor that is designed for parallel operation n simple symmetric Boolean functions that depend on n (n≥2) arguments input binary signals containing two ends and two break key, characterized in that it introduced n-2 guard and n-2 NC key register and a computational cell, each of which contains an element OR connected first, second inputs and output respectively to its first, second inputs and a first output, and element And connected first, second inputs and an output, respectively, to its the first, the second input and second output, the output and input of the i-thNC key connected respectively with the output of the i-th closing key and United the i-th output of the register, the i-th output of a logical processor connected first, second configuration and the i-th information inputs respectively to the control input of all keys input register entries and the input of the i-th trailing key, all computational cells are grouped in two groups the AK, that the first and second groups contain, respectively, g and k of computational cells, the first and second inputs of the r-th
a computational cell of the first group are connected respectively to the outputs of the (2r-1)-th and (2r)-th guard keys, the first and second outputs of the m-th
a computational cell of the second group are respectively connected to the (2m)th and (2m+1)-th input register, a second output r-th
the previous and first output (r+1)-th computing cells of the first group are connected respectively with the first and second inputs of the r-th computational cell of the second group and the first output of the first computational cell of the first group connected to the first input of the register, in addition, when n is even k=0,5n-1 and the second output of the g-th (g=0,5n) computational cell of the first group is connected to the n-th input of the register, and for odd n the first and second inputs of the k-th (k=0.5(n-1)) a computational cell of the second group are connected respectively with the second output of the g-th (g=0,5(n-1)) of a computational cell of the first group and the output of the n-th trailing key.