Logical processor
 Logic module / 2249844Logic module has And element, first, second majority elements, OR element, three data inputs and two adjustment inputs. |
 Logical calculator / 2248036Device has 2n AND elements, n OR elements, n D-triggers. |
 Symmetric module / 2248035Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered |
 Logical converter / 2248034Device has eleven majority elements, four information inputs, two adjustment inputs. |
 High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. |
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High-speed module for adding/comparing/selecting for use with witterby decoder / 2246751 System has first memory element for storing metrics of basic states, multiplexer, capable of selection between first and second operating routes on basis of even and odd time step, adding/comparing/selecting mechanism, which calculates metrics of end states for each state metric. Second memory element, connected to adding/comparing/selecting mechanism and multiplexer is used for temporary storage of end states metrics. Multiplexer selects first operating route during even time steps and provides basic states metrics, extracted from first memory element, to said mechanism to form end state metrics. During odd cycles multiplexer picks second operating route for access to second memory element and use of previously calculated end state metrics as metrics of intermediate source states. |
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Logical converter / 2248034 Device has eleven majority elements, four information inputs, two adjustment inputs. |
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Symmetric module / 2248035 Module has n D-triggers, n AND elements and n OR elements, while output of i-numbered |
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Logical calculator / 2248036 Device has 2n AND elements, n OR elements, n D-triggers. |
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Logic module / 2249844 Logic module has And element, first, second majority elements, OR element, three data inputs and two adjustment inputs. |
 Logical processor / 2251142Device has majority elements, grouped in V+1 group in such a way, that i-numbered (I = 1, V) and V+1 numbered groups contain respectively n and V-1 majority element groups. |
 Singular signals number identifier / 2256211Identifier has twenty two cells, each of which has two inputs, two outputs, AND, XOR elements, while all cells are grouped as a matrix of four rows and seven columns in such a way, that i-numbered (i=1,4) string and j-numbered (j=1,4) column contain respectively 8-i and j cells. |
 Logic calculator / 2257608Device has n computing cells, each of which has AND element, OR element, D-trigger. |
 Logical processor / 2260205Device has closing and opening keys, register and calculating cells, each of which consists of OR element, AND element. |
 Unary signals adder / 2260836Device has n calculating cells, each of which consists of AND element and XOR element, n AND elements, n D-triggers. |
FIELD: computer science.
SUBSTANCE: device has majority elements, grouped in V+1 group in such a way, that i-numbered (I = 1, V) and V+1 numbered groups contain respectively n and V-1 majority element groups.
EFFECT: broader functional capabilities.
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The invention relates to computer technology and can be used for building automation, functional units of the control systems and other
Known logical processors (see, for example, rise on str in the book Kazkas A.A. Basics of electronics. M: The High. HQ., 1988.), which implement simple symmetric Boolean function(majority function)that depends on three arguments - input binary signals x1, x2, x3∈ {0,1}.
For the reason that impede the achievement of specified following technical result when using known logical processors include limited functionality due to the fact that there is no implementation of any of the n simple symmetric Boolean functions that depend on n arguments (input binary signals).
The closest device to the same destination to the claimed invention by the combination of features is adopted for the prototype, the logical processor (see RIS on str in the book Digital and analog integrated circuits: Handbook/. Sviatoslavsky, Lignosellus, Vigolana and other M.: Radio and communication, 1989.), containing three majority element, each of which implements the majority function of three arguments (input binary signals).
To the cause, prevent the it to achieve specified below technical result when using prototype includes limited functionality due to the fact that there is no implementation of any of the n simple symmetric Boolean functions that depend on n arguments (input binary signals).
The technical result of the invention is the extension of functionality by ensuring the implementation of any of the n simple symmetric Boolean functions that depend on n arguments (input binary signals).
This technical result in the implementation of the invention is achieved by the logical processor containing three majority element, the peculiarity lies in the fact that it added similar to those mentioned majoritarian elements, and all of a majority of the items are grouped in V+1 groups, so that i-Iand (V+1)-I groups contain, respectively, n and V-1 a majority of elements in i-th group, the output of each previous majority element connected to the second input of the following majority element, and the output of the n-th majority of the first element and outputs n-x the majority of elements of the second,..., V-St groups respectively connected to the second input of the first and third inputs of the first,..., (V-1)-th majority of elements (V+1)-th group, in which the output of each previous majority element connected with the second input of the following m is Guitarsolo element, and the output (V-1)-th majority element is the output of a logical processor, with
(n≠1 is any natural number, m=0,5(n+1) or m=0,5n for odd or even n, respectively).
The drawing shows the proposed scheme logical processor.
Logical processor contains a majority of the members 111,...,1(V+1)(V-1)wheren≠1 is any natural number, m=0,5(n+1)(m=0,5n) for odd (even) n. All of a majority of the items are grouped in V+1 groups, so that i-I (i=
and (V+1)-I groups contain respectively the elements 1i1,...,1inand 1(V+1)1,...,1(V+1)(V-1)the output of
connected with the second input element 1i(j+1)the output of element 11nand the outputs of the elements 12n,...,1Vnconnected respectively to the second input element 1(V+1)1and third inputs of the elements 1(V+1)1,...,1(V+1)(V-1)the output of element 1(V+1)k(k=(i=
) is connected with the second input element 1(V+1)(k+1)and the output of the element 1(V+1)(V-1)is the output of a logical processor.
The work of the proposed logical processor is as follows. The second inputs of the elements 111,...,1V1fixed signal y=1, and at the third input elementov i1,...,1in(i=) are respectively input binary signals xi1,....,xin(xi1,...,xin∈ {x1,...,xn}, i1≠...≠in), and V sets xi1,...,xinshould be formed taking into account the fact that the subset {x11,...,x1(u-1)},...,{xW1,...,xW(u-1)} (W=C
| u-1 |
| n |
Here each continuous line circled all possible combinations of the five variables, X1,...,x5u-1 with the corresponding values of u. On the first input element 1(V+1)1,...1(V+1)(V-1)served respectively the control signals f1,...,fV-1∈ {0,l}, and
wherethere are a number of combinations of n n-p, p ∈ {1,...,n} is the number of required simple symmetric Boolean functions. On the first input element 1i1,...,1in(i=
) are respectively the control signals fi1,...,finthat ∈ {0,l}, and
The output signal of the majority of the element is equal to “1” (“0”) only when on two or on all inputs of this element signals are equal to “1” (“0”). Therefore, if the first input of the majority element is “1” (“0”, then this element will perform the operation “OR” (“AND”) over signals acting on its second and third inputs. Thus, the signal at the output of a logical processor is determined by the expression Z=ϕV-1(MV,...ϕ2(M3that ϕ1(M2, M1))...), where
characters ∨ and ∧ marked accordingly surgery “OR” and “And”. Taking into account (2) and (1) we can write:
if i=
and
Expression (3) containsnon-recurring intermob
and coincides with the form of p-th
simple symmetric Boolean function τpthat depends on n arguments x1,...,xn(see str in the book Pospelov D.A. Logical methods of analysis and synthesis schemes. M: Energy, 1974.). Thus, the proposed logical processor will play operation
The above information allows the t to conclude, the proposed logical processor has a wider compared to the prototype functionality, as it provides the implementation of any of the n simple symmetric Boolean functions that depend on n arguments (input binary signals).
Logical processor for implementing any of the n simple symmetric Boolean functions that depend on n arguments containing three majority element, each of which contains the first, second, and third inputs, characterized in that it additionally introduced similar to those mentioned majoritarian elements, and all of a majority of the items are grouped in V+1 groups, so that i-Iand (V+1)-I groups contain, respectively, n and V-1 a majority of elements in i-th group, the output of each previous majority element connected to the second input of the following majority element, and the output of the n-th majority of the first element and the output of the n-th majority of the elements of the second, ..., V-St groups respectively connected to the second input of the first and third inputs of the first, ..., (V-1)-th majority of elements (V+1)-th group, in which the output of each previous majority element is connected with the second input of the following majority element, and the output (V-1)-th majority element is the output of a logical processor, while
(n≠1 is any natural number, m=0,5(n+1) or m=0,5n for odd or even n, respectively).