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Logical calculator

IPC classes for russian patent Logical calculator (RU 2353967):

G06F7/57 - Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K0019000000)

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FIELD: information technologies.

SUBSTANCE: logical calculator is intended for implementation of n simple symmetric Boolean function depending on n arguments - input binary signals- and can be used in computer engineering digital systems as code conversion facility. The device contains n closing keys, n opening keys, n AND elements, n OR elements and n D-triggers.

EFFECT: device functionality enhancement due to implementation of parallel or sequential Boolean functions set depending on sequential or parallel set of specified arguments respectively.

2 dwg, 2 tbl

The invention relates to computer technology and can be used for building automation, functional units of the control systems and other

Known logic solvers (see, for example, in figure 1 the description of the invention to the patent of the Russian Federation 2276399, CL G06F 7/00, 2006), which implement a parallel set of n simple symmetric Boolean functions that depend on sequential set of n arguments - input binary signals.

For the reason that impede the achievement of specified following technical result when using known logic solvers are limited functionality due to the fact that there is no implementation of a sequential set of n simple symmetric Boolean functions that depend on a parallel set of n arguments - input binary signals.

The closest device to the same destination to the claimed invention by the combination of features is adopted for the prototype logic solver (figure 1 in the description of the invention to the patent of the Russian Federation 2282234, CL G06F 7/57, 2006), which contains n guard, n NC keys n elements And n elements, OR n of the D flipflops and implements a sequential set of n simple symmetric Boolean functions that depend on a parallel set of n arguments - input binary signals.

The reason prepyatstvyya the achievement of specified following technical result when using prototype includes limited functionality due to the fact that there is no parallel implementation of a set of n simple symmetric Boolean functions that depend on sequential set of n arguments - input binary signals.

The technical result of the invention is the extension of functionality by providing an implementation of a parallel set of n simple symmetric Boolean functions that depend on sequential set of n arguments - input binary signals or sequential set of these functions depending on a parallel set of specified arguments.

This technical result in the implementation of the invention is achieved in that in a logical computer containing n guard, n NC keys n elements And n elements OR and n D-flip-flops, the first and second inputs of the i-thelement And connected respectively with the second and first inputs of the i-th element OR the output of the i-th closing and the output of the i-th NC keys are combined, and the control input is connected to the first Manager of the input logic solver, connected second managing input to the clock input of the i-th D flip-flop feature is that the output of the k-thelement And the output of the i-th element OR otklucheny respectively to the first input of the (k+1)-th element And the input data of the i-th D flip-flop non-inverting output of which is connected to the input of the i-th NC key output connected to the first input of the i-th element OR the output of which is connected with the i-th parallel output logic solver that is connected to the i-th parallel input, serial input and serial output, respectively, to the input of the i-th trailing key, the first input of the first output n-th elements I.

Figure 1 and figure 2 presents respectively the proposed scheme logic solver and timing diagrams explaining the principle of its operation.

Logic solver contains n guard key 1₁,...,1_nn NC key 2₁,...,2_nn elements And 3₁,...,3_nn elements OR 4₁,...,4_nand n D-flip-flops 5₁,...,5_nand the output elementthe first and second inputsconnected respectively to the first input element 3_k+1second and first inputs of the element 4_iwhose output is connected to the data input of D-flip-flop 5_iconnected reinvestiruet output to the input key 2_iwhose output is connected to the output key 1_iand the first input element 4_iconnected the output to the i-th parallel output logic solver, the i-th parallel input, serial input, p is coherent output, the first and second control inputs of which are connected respectively to the input key 1_ithe first input element 3_i, the output element 3_nentrance control keys 1_i, 2_iand the clock input of D-flip-flop 5_i.

The work of the proposed logic solver is as follows. At its first, second control inputs are given correspondingly of pulse signals₁,₂∈{0,1} (2), and the duration T^*a high level signal at₁and the period T of the signal y₂must satisfy the conditions T^*>Δt^*and T>Δt, where

Δt^*=nΔt_And, Δt=Δt_Tp+nΔt_Anda ∆ T_Trand ∆ T_Andthere is duration of the delay introduced D-trigger and the element I. the Arguments of functions - input binary signals x₁,...,x_n∈{0,l} or sequentially served according to figure 2 on serial input logic solver (his first,..., n-th parallel inputs fixed logic 0)or in parallel are given correspondingly to the first,..., n-th parallel inputs of the logic solver on its serial input latched logic "1"). If₁=1 (y₁=0), then the keyclosed (open)and key 2_iopen (closed). Then the signals at the outputs of the elements 3 i, 4_iwill be determined by recurrent expressions

wherethere are a number of time t_j(figure 2); V_i0=x_i, W_0j=1 or V_i0=0, W_0j=x_j. The following table 1 and table 2 shows the values of the expressions (1) when n=4, if, respectively, V_i0=x_i, W_0j=1 and V_i0=0, W_0j=x_j.

Table 1
W₁₁=x₁ V₁₁=1	W₂₁=x₁x₂	W₃₁=x₁x₂x₃	W₄₁=x₁x₂x₃x₄
W₁₂=1 V₁₂=1	V₂₂=1
W₁₃=1 V₁₃=1	W₂₃=1 V₂₃=1	V₃₃=1
W₁₄=1 V₁₄=1	W₂₄=1 V₂₄=1	W₃₄=1 V₃₄=1	V₄₄=1

Table 2
W₁₁=0 V₁₁=x₁	W₁₂=x₁x₂
W₂₁=0 V₂₁=0	W₂₂=0 V₂₂=x₁x₂	W₂₃=x₁x₂x₃
W₃₁=0 V₃₁=0	W₃₂=0 V₃₂=0	W₃₃=0 V₃₃=x₁x₂x₃	W₃₄=x₁x₂x₃x₄
W₄₁=0 V₄₁=0	W₄₂=0 V₄₂=0	W₄₃=0 V₄₃=0	W₄₄=0 V₄₄=x₁x₂x₃x₄

Thus, at V_i0=x_iand W_0j=1 on the serial output of the proposed logic solver have

and at V_i0=0, W_0j=x_jand j=n in its first, second,..., nth parallel outputs respectively have

where τ₁,..., τ_nthere is a simple symmetric Boolean functions (see str in the book Pospelov D.A. Logical methods of analysis and synthesis schemes. M: Energy, 1974).

The above data allow us to conclude that the proposed logic solver has a wider compared to the prototype functionality, as it provides an implementation of a parallel set of n simple symmetric Boolean functions that depend on sequential set of n arguments - input binary signals or sequential set of these functions depending on a parallel set of specified arguments.

Logic solver, dedicated to the implementation of n simple symmetric Boolean functions that depend on n arguments - input binary signals containing n C is macauda, n NC keys n elements And n elements OR and n D-flip-flops, and the first and second inputs of the i-thelement And connected respectively with the first and the second inputs of the n-th element OR the output of the i-th closing and the output of the i-th NC keys are combined, and the control input is connected to the first Manager of the input logic solver, connected second managing input to the clock input of the i-th D-flip-flop, wherein the output of the k-th
element And the output of the i-th element, OR respectively connected to the first input of the (k+1)-th element And the input data of the i-th D-flip-flop, inverting the output of which is connected to the input of the i-th NC key output connected to the first input of the i-th element OR the output of which is connected to the i-th parallel output logic solver connected i-m parallel input, serial input and serial output, respectively, to the input of the i-th trailing key, the first input of the first output n-th element I.