Error handling for early decoding through branch correction

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to processors with pipeline architecture. The method of correcting an incorrectly early decoded instruction comprises stages on which: the early decoding error is detected and a procedure is called for correcting branching with a destination address for the incorrectly early decoded instruction in response to detection of the said error. The early decoded instruction is evaluated as an instruction, which corresponds to incorrectly predicted branching.

EFFECT: improved processor efficiency.

22 cl, 3 dwg, 1 tbl

 

The present invention in General relates to the field of processors and in particular to a method of correcting erroneous pre-decoded data associated with the instruction, by applying the correction procedure branches to the target address of the instruction.

Microprocessors perform computing tasks in a wide variety of applications. Improved CPU performance is almost always desirable to provide a faster and/or improved functionality through software changes. In many embedded applications, such as portable electronic devices, energy conservation is also an important task in the design and implementation of the processor.

Most modern processors can use a pipelined architecture, where sequential instructions to overlap in execution, in order to increase the overall performance of the processor. Maintaining a smooth run through the pipeline is critical to achieve high performance. Most modern processors also use a hierarchical memory with a fast placed on the chip of the processor modules cache memory that stores local copies of data and instructions, which were recently accessed. One of those is ology optimization of the conveyor, known in the technical field is pre-decoding instructions. That is, instructions are treated when they are read from memory, partially decoded, and some information about the instructions is known as the preliminary information of the decoding is stored in the cache memory with associative related instructions. When instructions are later invoked from the cache, the information is preliminary decoding is also invoked and used to help fully decode the instructions.

Sometimes the information is preliminary decoding contains errors. These errors can be detected during the decoding stages in the pipeline. When an error is detected, an exception occurs and the pipeline must be cleaned and all instructions, including incorrectly pre-decoded instruction must be selected again. This process introduces a significant deterioration in performance and energy management.

The invention

The present invention in one embodiment relates to a method of correction of the incorrectly pre-decoded instruction. An error is detected prior to decoding. Is called the correction procedure of branching to the target address of the incorrectly pre-decoded instruction in response to about narushenie errors.

The present invention in another embodiment relates to a processor. The processor includes a pre-decoder, placed in the path of the call instruction, the pre-decoder generates information pre-decoding, associative associated with individual instruction. The processor also includes an error detector pre-decoding and the offset detecting incorrect information prior to decoding, associative associated with the instruction, and initiating the execution of instructions as incorrectly predicted branch target address of the branching address instruction.

Brief description of drawings

Figure 1 is a functional block diagram of the processor.

Figure 2 is a functional block diagram of the memory pre-decoder, instruction cache misses and part of the processor pipeline.

Figure 3 is a functional block diagram of the logic correction branching.

Detailed description of the invention

Pipelined processor architectures exploit parallelism, overlapping the execution of multiple sequential instructions, each of which has multiple stages. Typical stages include a call instruction decode, execute, and writeback. Each step in the pipeline, one is or more stages of the pipeline, contains the logic and memory element, such as a trigger-latch or register. Stages of the pipeline are connected together to form a pipeline. Instructions are entered into the pipeline and consistently performed in stages. Additional instructions are inserted into the pipeline before the end of the previous instructions, therefore the set of instructions can be processed in the pipeline at any given time. This ability to exploit parallelism among instructions in a sequential instruction stream significantly improves processor performance. In ideal conditions, and the processor that completes each stage of the pipeline for one cycle, followed by a brief initial process of filling the pipeline, the instruction execution can be completed in each cycle. Many real constraints prevent the keeping of this ideal conditions; however, the pipeline is full and it works smoothly flowing is the overall goal when designing the processor.

Usually modern processors also use the memory hierarchy, which places a small amount of fast, expensive memory closer to the processor and which is supported by a large number of slower, cheaper memory. A typical memory hierarchy of the processor may content the TB registers in the processor at the top level, supported by one or more located on the processor die modules of the cache memory (e.g., SRAM); it is possible that the module cache memory outside of the crystal, referred to as the cache level 2 or L2 (for example, SRAM); main memory (usually DRAM); a storage device to a disk (magnetic media) and tape or CD (magnetic or optical media) in a slow level. In embedded applications, such as portable electronic devices may be limited, if necessary, the backing store on disk, and therefore, the main memory (usually limited in size) may be the slowest level of memory hierarchy.

Figure 1 depicts a functional block diagram of a typical processor 10 using and pipeline architecture, and the structure of the hierarchical memory. The processor 10 executes instructions in the pipeline 12 execute instructions according to the logic 14 controls. The conveyor includes various registers or the trigger-latch 16 arranged in speed of the conveyor, and one or more arithmetical-logical unit (ALU) 18. Set of 20 General purpose registers (GPR) provides registers containing the top of the memory hierarchy. The pipeline fetches instructions from the cache 22 of the instructions with memory addressing and permissions managed by the buffer quickly convert addresses from the instructions (ITLB) 24, and kotoroe the initial decoding of the instruction pre-decoder 21. Data are available from the cache 26 data memory addressing and permissions managed in the main buffer fast address translation (TLB) 28. In various embodiments, the implementation of the ITLB can contain a copy of the part of the TLB. Alternatively, ITLB and TLB can be combined. Similarly, in various embodiments, the implementation of the processor 10, the I-cache 22 and D-cache 26 may be combined or unified. Accesses that are not represented in the I-cache 22 and/or D-cache 26 (omissions), cause the access to the main (outside of chip) memory 32 under the control interface 30 of the memory. The processor 10 may include an interface 34 input/output (I/O)that controls access to a variety of peripheral devices 36. Experts in the field of technology will recognize that many possible variations of the processor 10. For example, processor 10 may include a secondary cache (L2) for either one of the two or both I - and D-caches. In addition, one or more of the functional blocks depicted in the processor 10 may be omitted in a separate embodiment.

One known technique of increasing processor performance and reduce energy consumption known as pre-decoding. Pre-decoder 21 includes logic to be placed on the path between the main memory 32 and the cache 22 of the instructions. Some of the instructions that caused samati, can be pre-decoded information about the preliminary decoding formed and recorded in the I-cache 22 together with the instruction. Information pre-decoding can help one or more stages of the pipeline in the decoding of instructions, when it is called from the cache for execution. For example, the pre-decoder may determine the length of the variable length instructions and to record information about pre-decoding in the cache, which helps stages of the decoding pipeline to find the correct number of bits for variable length instructions. Various information may be pre-decoded and stored in the I-cache 22.

Pre-decoder 21 improves performance by removing logic from one or more stages of the decoding pipeline, allowing earlier use logic and possibly allowing for shorter cycle time machine. Pre-decoder 21 also reduces energy consumption when performing operations pre-decoding once. Since the coefficients match the I-cache 22 are usually in the high 90%, significant energy savings can be realized by eliminating the need to perform a logical operation each time the instruction is executed from the I-cache 22.

Sometimes before retelny decoder 21 makes mistakes. For example, if data such as parameters or immediate value is stored in memory along with instructions, the operation of pre-decoding, which determines the length of the instructions, just counting the bytes from the beginning of the cache line may erroneously identify the bytes of one or more of these parameters or values as the statement following the next lines. Other types of errors, including random errors in bits, either in the pre-decoder 21, or in the I-cache 22. These errors will be detected at one or more stages of the decoding pipeline and will be in a typical cause of the exception, requiring that the pipeline was cleaned and re-launched, thus bringing additional costs in terms of productivity and energy consumption.

There are ways to correct the errors prior to decoding, which prevent the occurrence of an exceptional situation and associative associated cleaning of the conveyor 12. Figure 2 is a functional block diagram depicting a part of the CPU 10 and the conveyor 12. Figure 2 also depicts the address register instruction cache misses (ICAR) 48, which generates an index of the I-cache 22. The address loaded in ICAR 48, formed and/or selected by the circuit 46 of calculating the address of the next sample. When the select statement is I from the memory 32 (or L2 cache), they are pre-pre-decoded by the decoder 21 and information 23 preliminary decoding is stored in the cache 22 of the instructions along with the instructions.

In the pipeline 12 instructions and associate related information 23 preliminary decoding are selected from the I-cache 22, at least partially decoded by the logic 40 decoding, and the results are stored in the trigger-latch 42 degrees DCD1 pipeline. In many processors 10 level

DCD1 conveyor includes a device for prediction. In cases where the prediction device predicts branching branching to be obtained, the stage of the pipeline can calculate the target address of the branch and provide his logic 46 calculate the address of the next fetch address on path 44 of the prediction. This is one example of the address path from stage pipeline to logic 46 of calculating the address of the next sample (branching, as predicted missed, just let continue fetching subsequent instructions).

Selected and partially decoded instruction then moves, in an exemplary embodiment, to the degree DCD2 pipeline, which includes logic 50 for detection and correction of incorrect pre-decoding. If an error is detected in the tentative information is tion decoding, step DCD2 conveyor may signal an exceptional situation and to clear the conveyor 12, as discussed above.

Alternatively, the preliminary error decoding can be corrected by re-fetching instructions from the memory 32. One way to do this is to invalidate the instruction cache 22 and to provide the address of the instruction route 54 scheme 46 addressing the next fetch. This address is then loaded into ICAR 48. Because the statement has been invalidated in the cache 22, the access to the cache is missing, causing the address to the main memory 32. Instruction selected from the main memory 32, and then must be properly pre-pre-decoded by the decoder 21 and placed back in the cache 22 of the instructions. Instruction can then be re-selected from the cache 22 together with the correct information 23 preliminary decoding.

Scheme 46 calculate the address of the next fetch is usually on the critical route for the most part, data flow processor and, thus, limits the time machine cycle. Adding route 54 for the address of the instruction memory associated with incorrect pre-decoding, add logic to calculate 46 addresses the following sample, increasing the time machine cycle and reducing performance. This splackavellie is particularly evident, taking into account the fact that pre-decoded information 23 is entirely wrong. Optimizing performance for rare cases, the price of a regular case usually reduces the overall performance of the processor.

According to one variant of implementation of the present invention eliminates the wrong route 54 preliminary decoding device 46 of calculating the address of the next sample (as indicated by the dashed line in figure 2). Rather than intended to provide a route to the device 46 of calculating the address of the next fetch logic 50 of the detection and correction of incorrect pre-decoding causes the conveyor 12 to assess the incorrectly pre-decoded instruction as an instruction branching. Logic 50 of the preliminary correction decoding can change the semantics of the incorrectly pre-decoded instruction on the semantics of branching or alternatively can set a flag, which is transferred through the pipeline, the flag indicates the stages of the execution pipeline, which statement must be interpreted as branching.

In particular, the incorrectly pre-decoded instruction is evaluated as branching, which was predicted as missed and appreciated as having been made with the target address of the branch, I had laudisa address incorrectly pre-decoded instruction. At some point down the conveyor 12 (depends on implementation details) statement is evaluated by the execution stage 56 of the conveyor, which evaluates the condition "branch taken", and generates the target address of the branch. The target address of the branch is provided to the device 46 calculate the next sample on route 58 correction of branching. The logic of assessment branching conditions, the logic of the formation of the target address of the branch and route 58 correction branching and associative associated control logic device 46 calculate the address of the next fetch already exist in each pipeline processor 10, which predicts the behavior of branching.

Figure 3 is a functional diagram of one possible implementation of the logic correction branching. In the trigger latch 56 EXE-stage pipeline, there are bits received 60 predicted branching (BPT) and bit 62 evaluation of the branching conditions (COND). Bit 60 BPT equal to one if the branch was predicted to be accepted by the device of prediction earlier in the pipeline 12, and equal to zero if the branch was predicted missed. Bit 62 COND equal to one if the branching is estimated as adopted, and equal to zero if the branching is estimated as missed. These two bits can be folded modulo two, as indicated by the valve 66 to form the selection multiplexer or origin which the second control signal, available device 46 of calculating the address of the next sample, indicating that the route 58 correction branching should be selected as the next fetch address. Table 1 below depicts the truth table for XOR 66.

Table 1
The truth table permissions prediction
BPTCONDOutputComment
000correctly predicted as missed; no correction
011incorrectly predicted as missed - you need to deliver the target address of the branch the addressing scheme of the next sample on the route correction sample
101incorrectly predicted as taken - need to deliver consistent and address the addressing scheme of the next sample on the route correction sample
1 10correctly predicted as taken; no correction

Bit 62 evaluation conditions may additionally serve as input data for a selection of multiplexer 68, which selects between the serial address and the calculated target address 64 branching to form the address placed on the route 58 correction of branching.

According to one variant of implementation of the present invention to operate incorrectly pre-decoded instruction, bit 60 BPT can be installed or forcibly adjusted to zero, and bits 62 COND can be installed or forcibly adjusted in the unit to call the situation "branch is incorrectly predicted as missed". In this case, the calculated target address 64 branching will be sent to the circuit 46 addressing the following sample through the route 58 correction of branching.

According to one variant of implementation of the present invention incorrectly pre-decoded instruction is evaluated as PC-coherent instruction branching to the field replacement of branching equal to zero. When this instruction is evaluated in the EXE stage 56 of the conveyor, the calculated target address of the branch will contain the address of the incorrectly pre-decoded instructions (with zero offset is). In another embodiment, the present invention incorrectly pre-decoded instruction is the instruction register branch and, optionally, register the target address of the branch is loaded with the address of the incorrectly pre-decoded instruction. When the register with the target address of the branch is loaded by means of arithmetic operations, registers operands can be loaded so as to form the address of the incorrectly pre-decoded instruction. Numerous other methods of assessment incorrectly pre-decoded instruction, such as instruction incorrectly predicted missed branching with the target address of the instruction that will be easily visible to the specialists in the field of engineering and is included in the scope of the present invention.

Referring again to figure 2, the instruction compulsory incorrectly predicted missed branching is performed in the EXE stage 56, and the target address of the branch that contains the address of the incorrectly pre-decoded instructions, is located on route 58 correction of branching. This address is chosen by the device 46 of calculating the address of the next sample is loaded in ICAR 48, and the selection instruction is executed in the I-cache 22.

Since logic 50 of the detection and correction of incorrect predvaritelnogo the decoding disables the cache line, containing the incorrectly pre-decoded instruction, access to the I-cache 22 will be absent, leading to the selection instructions from the memory 32 (or L2 cache). The statement will then be correctly pre-pre-decoded by the decoder 21 and placed together with information 23 proper pre-decoding in the I-cache 22. Instruction and information 23 preliminary decoding can then be re-selected from the I-cache 22, correctly decoded and properly executed in the pipeline 12. The bias error, for example, due to the fact that the data is scattered with instructions, will not happen again in the pre-decoder 21 as a memory access is performed on the exact address of the instruction, not the beginning of the cache line.

Note that the above description of memory accesses is conceptual. In any given implementation of the access to the memory 32 may occur in parallel with the access to the I-cache 22; miss I-cache 22 can be predicted and, therefore, access to the I-cache 22 is canceled; the results of the memory 32 can go directly to the conveyor 12 in parallel with the entry in the I-cache 22; and the like. In General, the present invention encompasses the optimization of the performance of the whole memory and/or cache, which may deviate from the above description.

Although the present invented the e has been described herein with respect to certain characteristics, aspects and variants of its implementation, it will be obvious that numerous changes, modifications and other embodiments of possible in the broad framework of the present invention and, accordingly, all changes, modifications and alternatives of implementation should be considered as within the scope of the invention. These variants of the invention should therefore be construed in all aspects as illustrative and not restrictive, and all changes made within the meaning and equivalence of the appended claims, are assumed to be covered by it.

1. Method of correction of the incorrectly pre-decoded instruction comprising stages, which are:
discover a mistake preliminary decoding and cause the correction of the branch target address is incorrectly pre-decoded instruction in response to detection of the error mentioned, these pre-decoded instruction is assessed as an instruction corresponding to the incorrectly predicted the branch.

2. The method according to claim 1, additionally containing a phase in which invalidate referred incorrectly pre-decoded instruction cache before calling the above procedure for the correction of branching.

3. The method according to claim 2, additionally containing the third stage, which selects the instruction from the memory in response to the correction procedure of branching.

4. The method according to claim 3, further comprising stages, on which the pre-decode the instructions and save the instructions and information prior decoding associated with the said instructions in said cache.

5. The method according to claim 1, wherein when the procedure is called correction branching specify the condition is true (TRUE) branching and set false (FALSE) prediction.

6. The method according to claim 1, wherein when the procedure of correction branch target address incorrectly pre-decoded instruction retain the above address register destination address and cause the correction instruction register branch.

7. The method according to claim 6, in which while maintaining the above-mentioned address in the register target address mentioned in the register target address to download the results of the arithmetic operations in relation to the contents of two registers as operands, store the calculated values in these registers operands, and the above-mentioned values are calculated to obtain the above address, on the basis of the above-mentioned arithmetic operations.

8. The method according to claim 1, wherein when the procedure of correction branch target address incorrectly predvaritelnaya instructions cause the correction associated with the program counter (PC) branching with zero offset fork.

9. The processor that contains:
pre-decoder, inserted on the path sampling instructions, and this pre-decoder generates information pre-decoding associated with the instruction; and
detector and corrector of errors pre-decoding, detecting incorrect information pre-decoding associated with the said instruction, and prescribing the above instructions to run as an incorrectly predicted branch address mentioned instructions as the target address of the branch.

10. The processor according to claim 9, further containing a cache memory that stores the instructions and the information was preliminary decoding, while the above-mentioned detector and error corrector pre-decode advanced invalidate the instruction in said cache memory upon detection of error mentioned pre-decoding.

11. The processor according to claim 9, further containing device of prediction and route correction branching delivering the corrected target address of the branch to fetch instructions in response to a conditional branch, estimated adopted, which was predicted missed.

12. The processor according to claim 11, in which the said detector and corrector of the flexible pre-decoding uses the route correction for branching instructions referred incorrectly pre-decoded instructions to be executed as instructions, appropriate incorrectly predicted missed the branch.

13. Method of correction of the incorrectly pre-decoded instruction comprising stages, which are:
find the error pre-decoding
in response to detection of the error mentioned pre-decoding prescribe incorrectly pre-decoded instructions to be executed as an incorrectly predicted branch address mentioned instructions as the target address of the branch, and
correct the error prior decoded by the fetch the instructions from the memory and pre-decode the instructions.

14. The method according to item 13, in which when fetching the instructions from memory invalidate the instruction cache memory and try to choose the instruction of the said cache memory after said instruction is made invalid.

15. The method according to item 13, in which when fetching the instructions from memory estimate referred to the statement as a branch from the said instruction address as the target address of the branch.

16. The method according to clause 15, which when assessing the above instructions as branching appreciate the above statement as correctly predicted missed in tweenie.

17. Method of correction of the incorrectly pre-decoded instruction comprising stages, which are:
discover a mistake preliminary decoding and
cause correction procedure, the branch target address is incorrectly pre-decoded instruction in response to the detection of the above errors,
when the procedure is called correction branching specify the condition is true (TRUE) branching and set false (FALSE) prediction.

18. Method of correction of the incorrectly pre-decoded instruction comprising stages, which are:
discover a mistake preliminary decoding and
cause correction procedure, the branch target address is incorrectly pre-decoded instruction in response to the detection of the above errors,
when the procedure is called, the correct branch target address incorrectly pre-decoded instructions save target address register destination address and initiate the correction instruction register branch.

19. The method according to p, which when stored in the register target address is loaded into the target register addresses the results of the arithmetic operations in relation to the contents of two registers as operands, store the computed values in these registers operands and determine the target and the RES, based on this arithmetic operations.

20. Method of correction of the incorrectly pre-decoded instruction comprising stages, which are:
discover a mistake preliminary decoding and
cause correction procedure, the branch target address is incorrectly pre-decoded instruction in response to the detection of the above errors,
when the procedure is called, the correct branch target address incorrectly pre-decoded instructions cause the software counter (PC) relative correction branching with zero offset fork.

21. The processor that contains:
pre-decoder, inserted on the path sampling instructions, and this pre-decoder generates information pre-decoding associated with the instruction with the address;
detector and corrector of errors pre-decoding to detect incorrect information pre-decoding associated with the said instructions, and instructions of this manual be performed incorrectly predicted branch address mentioned instructions as the target address of the branch, the power prediction for filing corrected target address of the branch to fetch instructions in response to Uslon the e branch, estimated adopted, which was predicted missed.

22. The processor according to item 21, in which the detector and corrector of errors pre-decoding uses the route correction for branching instructions referred incorrectly pre-decoded instructions to be executed as instructions corresponding to the incorrectly predicted missed the branching.



 

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