Configurable computing device

FIELD: computing devices with configurable number length for long numbers.

SUBSTANCE: device consists of two computing device units, each of them divided into at least four subunits, which consist of a quantity of unit cells. Named units are spatially located so that the distance between unit cell of first unit and equal unit cell in the second unit is minimal. Computing device configuration can be changed using configurational switches, which are installed between device subunits.

EFFECT: increased performance of computing device, reduced time of data processing.

12 cl, 6 dwg

 

The present invention relates to computing devices and, in particular, to a configurable length computing devices for long integers.

DE 3631992 T2 describes a cryptographic processor for efficient performance of the method with the public key Rivest, Shamir, Adleman, which is also known as the RSA method. Necessary for this method of modular exponentiation is computed with the method of the multiplication with a proactive method of reducing proactively. To do this, use trichopterology adder. Known trichopterology the adder has a length of 660 bits. The unit cell consists of several cryptographic registers, shift register, half-adder, full adder and item expedited transfer. Four such elementary cells form chetyrehyacheechny block, and attached to it the element of accelerated migration. Five such chetyrehyacheechny blocks form 20 cell block. Device encryption consists of 33 such 20 cell blocks and a control unit that includes a clock generator for clocking unit cells. The elements of the accelerated transfer chetyrehyacheechny blocks included together to recognize, whether the transfer at a greater distance, namely at 20 bits. If activated signal promote of 20 RA is inline-block, this means that the transfer in question 20-bit block depends on the transfer on the output of the preceding unit. If, on the contrary, the signal promoting 20-bit block is not activated, it means that the available transfer at the output of this block, i.e. at the senior most important category of this unit, is formed inside this block, and does not depend on the preceding block.

Thereby, it is possible to improve the performance of the operating cycle of the computing device, i.e. the speed of the feeding new input operands, compared to the worst case in which the track transfer continues from the LSB of all computing devices to the most significant bit of all computing devices. If activated, the signal distribution for a 20-bit block, then the duty cycle of the entire computing device is slowed down to such an extent that whereas the worst case, i.e. the computing device is stopped until such time as the transfer is excluded from the Junior to the senior level only computing device.

Therefore, the cycle time, i.e. the time after which the next input operand is served in the computing device is set so that it has enough to handle transfer directly from the neighboring blocks. The advantage of this is that regardless of the number of cells of a computing device, you must take into account only the time of the transfer unit. If, on the contrary, it is established that the transfer of the current block affects not only the previous block and the previous block previous block, the cycle time is slowed down so that there is enough time for a full track transfer.

4 shows an elementary cell of rank i is known computing device. The unit cell consists of several registers for multiple input operands, of which figure 4 shows only two register cells 110 and 112. The unit cell also includes an adder 114 and the register cell for the result, which in figure 4 is indicated by the reference position 116. From a relatively large number of components in the unit cell presented in figure 4, it follows that one such unit cell in its practical implementation has a relatively small height h, but a relatively large width d. Based on the fact that 660 of such unit cells must be stacked on top of each other, it is a tall narrow tower. Technologically still desirable are possible square chips, so a tall narrow tower is divided into several small bundles, which size is placed next to each other. Each second stack turned top down. Data required by the stack from the previous stack is transferred on the upper side and the lower side of the stack to the adjacent piles.

In order to reduce processing time, certain cryptographic algorithms can be processed using two parallel computing devices. Specific algorithms have a requirement: if they, for example, are iterative, the content in the register of the one computing device is loaded into the register operand of another computing device.

A similar situation is presented in figure 3. Figure 3 shows the first computing device 91 long numbers and the second computing device 92 long numbers. Each computing device includes a number of unit cells 90, and each unit cell has a structure as shown in figure 4. The number of unit cells in each computing device long numbers is the same and equals to n. Depending on the application, the computing device have different lengths. Described in DE 36 312 992 C2 computing device has a length of 660 bits. If should be executed in parallel two encryption operations, it is necessary to use two 660-bit computing device is istwa long integers.

For cryptography using elliptic curves already achieved sufficient reliability, if the secret key is used, having a length of, for example 160 bits. Therefore, such a computing device must have a width of at least 160 bits. For RSA cryptosystems there are implementations with a satisfactory level of reliability, in which the module is 1024 bits. More reliable RSA system are 2048 bits. Therefore, for parallel application must be enabled in parallel, for example, two 1024-bit or two 2048-bit computing device.

In order to download the content in the register of the, for example, computing device 1 long numbers (91 figure 3) in the input register operand of the computing device 2 long numbers (92 figure 3), you can use the first bus interface, the second interface 94 tires, as well as, for example, 32-bit bus 95. Therefore, the interface 93 bus will contain a block sample of 32-bit blocks of the computing device 1 long numbers. Then, each 32-bit block is transferred one after another to the interface 94 bus via the bus 95, and the interface 94 bus stipulates that each 32-bit block is loaded into the corresponding elementary cell computing devices long numbers. For a 660-bit computing device requires dvadtsat the cycles, each cycle consists of the following steps: addressing 32 unit cells in the source computing device long numbers, the sample 32 unit cells in the source computing device long numbers, the transfer 32 bits via the bus, addressing 32 unit cells in the target computing device long numbers and loading it into memory, 32 bits in the addressed 32 elementary cells of the computing device long integers.

The access computing device to register another computing device using a prior exchange of explicit operands via the bus system, which linked both computing devices. According to the standard, the width of this bus is 32 bits. Depending on the proposed system bus may be a width of 8 bits. Therefore, the sharing of computing devices long numbers and, especially, for series-parallel computing device takes a long time. In addition, there are often problems of reliability, because the data transfer is observed in the current profile.

The task of the invention is to create an efficient and reliable computing device. This problem is solved by creating a computing device in accordance with claim 1 of the claims.

The basis of the proposed image is etenia is the idea, that registered exchange between computing devices long numbers can be accelerated, if the first unit of a computing device located adjacent to the second unit of the computing device; if the distance between one unit cell of the first unit of the computing device and the equivalent unit cell of the second unit of the computing device is smaller than the average distance between the same elementary cell of the first unit of the computing device and at least two non-equivalent elementary cells of the second unit of a computing device. Blocks of computing devices connected via a communications device using a certain number of lines, number of lines equals the number of unit cells in one unit of a computing device, one line connects the at least one register cell in the unit cell of the first unit of the computing device with at least one register cell unit cell, in accordance with the importance of the second unit of the computing device, and in addition, is provided by the control device to download the content of the register cells of one unit of the computing device through the communication line in the register cell of another block the transmitter is on the device.

The advantage of the invention is that the registered exchange between the two parallel computing devices runs faster because it only requires one cycle.

Another advantage of the present invention is that both the parallel computing devices are located nearby, so that the unit cell in both computing devices with the same significance are located nearby, lines of communication are short and therefore more difficult to unauthorized listening, because such unauthorized listening can be carried out easier the longer the line, exposed to such listening.

Another advantage of the present invention is that the profile of the current, in particular, the computing device long numbers when the data transfer is homogeneous, since they simultaneously transferred many independent from each other bits.

Another advantage of the invention is to ensure that the computing device can be subjected to a reconfiguration due to the fact that two parallel spaced computing device can be reconfigured into a single computing device with double length, if the track of the transfer of the output signal is of arenosa senior level of the first computing device is connected to the input of the transfer LSB of the second unit of a computing device. In other words, this means that very long computing device can be reconfigured through action on the track transfer between two or more blocks of the computing device 2, 4 parallel computing devices of a smaller length. This feature is of particular advantage for multi-purpose cryptographic processor, because for certain cryptographic tasks require different lengths of computing devices. In cryptography using elliptic curves length codes reach the order of magnitude in the range from 150 to 180 bits, preferably 160 bits, to ensure sufficient reliability. In contrast, in the conventional RSA system reliability is achieved only if apply length code 1024 bits or recently even 2048 bits, which inevitably leads to the fact that for efficient processing cryptosystem requires computing device long numbers with a length of more than 1024 or greater than 2048 bits.

On the other hand, in particular in the case of cryptographic processors, which are placed on smartcart in the form of chips, the requirement to the surface of a chip set from the outside, and the appropriate size strictly adhered to. The challenge is to put in a chip of a given size such necessary components for cryptographic what about the processor, as, for example, computing device, storage device, etc. Requirements to the chip surface, lead to the fact that it is preferable to provide a separate computing device for every cryptographic algorithm, and opportunities for all cryptographic algorithms are the same computing device. On the other hand, different code length and different length computing devices are essential hallmark of cryptographic algorithms.

The ability to reconfigure the length of a computing device by introducing track transfer between two blocks of the computing device and by providing a configuration device for connecting circuit of the computing device, if it requires long computing device, or to interrupt track of the transfer, if you need multiple parallel short computing devices, provides the advantage that can be used one computing device for multiple applications, and, additionally, if you have a shorter code length, part of the computing device, not just disabled, but can work as a second concurrent computing device, which can realize rapid registers is th communication with the first computing device.

In order to place the computing device in accordance with this invention on the chip, i.e. in an integrated circuit with a given geometry, each unit of the computing device is divided into subunits. When the subunits are invested in each other so that the two subunits of the first unit of the computing device is one subunit of the second unit of the computing device, and in addition, the subunits of the first and second blocks of a computing device placed in such a way that the elementary cell of equal importance are the smallest distance. This leads to a nested one into another double meander structure. Thus, the meanders of both parallel blocks of a computing device are placed alternately. The first protrusion meander one computing device, the first protrusion meander the other unit of the computing device, the latter is geometrically mirrored to implement short distances between the elementary cells of the same importance, if both blocks of a computing device are parallel to each other. The location of blocks of a computing device in the form of incoming into each other meander patterns makes it possible for that sort of blocks the transmitter is the first device through the activation track migration are joined in a single computing device with double length.

Preferred examples of the invention were explained in detail on the accompanying drawings:

figure 1 - block diagram of a computing device according to this invention;

figure 2 - block diagram of the preferred configuration of a computing device according to this invention;

figure 3 - block diagram for the implementation of the register exchange between the first computing device long numbers and the second computing device long numbers using conventional bus system;

4 is a schematic representation of the unit cell for a bit i in the computing device a long number;

5 is a block diagram of another preferred arrangement of a computing device according to this invention;

6 is a detail view to illustrate the arrangement of the two blocks of the computing device relative to each other.

Figure 1 shows a block diagram of a computing device according to this invention. The computing device includes a first block 10 computing device and the second block 12. Each block itself consists of a certain number of unit cells 10A and, accordingly, 12A, and of the unit cell for the younger discharge 10V and 12V and unit cell for senior level 10s and 12s. Unit cell 10V for Junior level calc the tion of the device 10, also referred to as LSB1. Unit cell for senior level computing device 10, also referred to as MSB1. A similar designation is selected for the second unit of the computing device 12, the term "LSB" (least significant bit) is used for the Junior category, and the term "MSB" (most significant bit) to the senior level. Each elementary cell shown in figure 1, 10A, 10B, 10C, 12A, 12B, 12C, may be performed as shown in figure 4. You should specify that each unit cell includes more or less of register cells for operands to be processed by the adder unit cell, or more or less of register cells for one or more results. To ensure rapid exchange of data between registers both computing devices, each computing device must have the elementary cells that have at least one register cell for storing in the memory discharge treated computing device of the operand.

Shown in figure 1, the computing device includes a coupling device, which has a certain number of lines 14a, 14b, 14C, and each line connects two elementary cells of the same value in both blocks of a computing device. For example, the communication line 14a cell battery (included) connects the container cell for bit i of the first unit of the computing device, which figure 1 is designated as 10A, with unit cell for bit i of the second unit of the computing device 12, which is designated as 12A. Similarly, the communication line connects LSB-unit cell 10B of the first block 10 with LSB-unit cell 12B of the second unit. The same applies to the communication line 14C, which connects both MSB-unit cell both units of a computing device.

According to this invention, the computing device includes a device 16 to control the blocks 10, 12 of the computing device so that the contents of the register cells of one unit of the computing device to load the contents of another unit via communication lines 14a, 14b, 14C directly for each unit cell.

Both units 10, 12 of the computing device shown in figure 1 a preferred variant implementation, can function as parallel blocks, to a certain extent independently of each other. Another option is that both units 10 and 12 are connected so that they function as a single computing device with a width that is equal to the number of unit cells in the first block 10 computing devices plus the number of unit cells in the second block 12 of the computing device. This is achieved by the fact that the provided l is of 18 transfer which connects the output transfer MSB-elementary cell of the first unit of a computing device with a carry-in input LSB-elementary cell of the second unit of a computing device. This functionality is further achieved by configuring the device 20 that controls the switch 22, while if the switch 22 is opened, both units of a computing device functioning as two parallel computing device. If switch 22 is closed, then both block computing device operate as a single computing device. The bits of the operand stored in the memory unit cell of the first block 10 of the computing device are in this case, the low-order bits of the complete operand, while the bits of the operand stored in the memory unit cells of the second block 12 of the computing device, are high-order bits of the complete operand.

In accordance with the design and the number of elementary cells in the block computing device and a given geometry for an integrated circuit, which is implemented is shown in figure 1, the computing device may be enough spatial configuration, shown in figure 1. In that case, if the specified geometry for CPU observe the characteristic, what is required computing device with a relatively small width, or the required rectangular chip.

As a rule, the requirement in this respect is that it is desirable to use a square chips.

For this purpose, let us turn to that shown in figure 2, the preferred double meander structure. Each unit of the computing device is divided into at least two subunits. As shown in figure 2 the example shows that each of the first and second blocks of the computing device consists of 16 unit cells, and that each unit of the computing device is divided into two subunits with eight elementary cells. Should indicate that the typical dimensions for a multi-purpose cryptographic computing devices require more than 1024 unit cells on each subunit.

The first block of the computing device 10 is divided into the first subunit 101 and the second subunit 102. Similarly, the second block of the computing device is divided into a first sub 121 and the second sub 122. The first subunit 101 and the second subunit 102 of the first unit of the computing device are connected by a path of migration 103. In the same way the first subunit 121 of the second unit of computing devices connected by a path of migration 123 with a second subunit 122 of the second unit of a computing device (12 in figure 1). Prina is being separate subunits shown in figure 1 to the blocks of the computing device is indicated in figure 2 in Roman numerals.

To ensure short lines of communication in the meander structure, both units of the computing device are in the form of incoming into each other meander-line structure, as shown in figure 2. For example, the LSB is the elementary cell of the first unit of a computing device connected to LSB-elementary cell of the second unit of the computing device through the communication line 14C. The same applies for the unit cell for category i of the first unit of the computing device and the unit cell for category i of the second unit of computing devices that are interconnected through communication lines 14a. And, finally, the MSB is the elementary cell of the first unit of the computing device and the MSB is the elementary cell of the second unit of computing devices connected via a communication line 14C. In the selected exemplary embodiment, the value entered in the corresponding unit cell. The value of the elementary cells of the first block is 0 (LSB-unit cell) to 15 (MSB-unit cell). The value of the second block is from 16 (LSB-unit cell) to 32 (MSB-unit cell), and these characteristics are valid for the case when the first and second blocks of computing devices interconnected via the line 18 and transfer switch 22, which is held configures the device is 20 in the closed position.

If both units computing devices working in parallel, the values of the elementary cells of the first unit of the computing device are not changed. The values of the second unit of the computing device are as shown in figure 2, from 0 to 15.

The device 16 controls as shown in figure 2, has a control connection to each subunit of the computing device in order to make it possible to register the exchange between the elementary cells of the first and second subunit through the connecting lines 14a, 14b, 14C.

Shown in figure 2 nested into each other meander structure both units of a computing device and, in particular, individual subunits ensures that the connecting line between the respective elementary cells of the same significance are as short as possible.

It should be stated that in practice a double meander structure consists of a larger number of subunits, as shown in figure 2. In practice, in particular, the individual subunits have a much greater height than width. In this case, in order to achieve an approximately square shape of the chip, it is necessary to divide the block computing device for more than two subunits, and be placed in accordance with the shown in figure 2, the interdigital structure.

Figure 5 shows d the u preferred configuration of the computing device, which occurs through reflection shown in figure 2, the computing device according to the first embodiment of the present invention relative to the horizontal axis. Shown in figure 5 computing device includes two blocks of the computing device, and the first block consists of sub-blocks 1001, 1002, 1003 and 1004, and the second set of sub-blocks 1005, 1006, 1007 and 1008. As shown in figure 5, the MSB of the computing device with the lowest sequence number from 1 to 7 is always connected to the LSB of a computing device with a serial number greater by one. Individual subunits are connected by means shown in figure 5 connecting lines, which represent the path of the transfer, which must be laid from one subunit to another. On the subunits 1001 to 1008 direction from the LSB to the MSB of the corresponding subunit of the arrow.

Figure 5 also shows the switch 22, which has the same function as the switch 22 in figure 2. If the switch is closed, the computing device shown in figure 5, operates as a single computing device long numbers with the number of bits 8 x m, where m is the number of bits subunit 1001 to 1007.

If, on the contrary, the switch is open, the computing device operates as two parallel and respectively over orodij computing device. The first unit of the computing device has the subunits 1-4, while the composition of the second unit of the computing device includes subunits 5-8. From figure 5 we can then see that the digits of the same order in both shorter computing devices are located so close to each other that the distance between the elementary cell of the first unit of the computing device and the equivalent unit cell of the second unit of the computing device is smaller than the average distance between the elementary cell of the first unit of the computing device and at least two unequal cells of the second unit of a computing device.

It should be noted that the average distance can be calculated so that all the elementary cells of one unit of a computing device, uneven relative to the unit cell of another unit of a computing device connected to the unit cell of the second unit of the computing device, an interval of each individual connection is summed, and then you can calculate the average value, for example, by dividing the length by the number of summed compounds. However, to calculate the average interval does not need to summarize each possible connection between the two blocks of a computing device and then calculate the average mn of the increase. Instead, it is enough to measure some compounds (e.g., 2) asymmetric unit cells and then on this basis to calculate the average value. In any case, the configuration is such that the track transfer between equivalent elementary cells are short, to be able to quickly register the exchange of one unit of a computing device to another computing unit of the device, and it is through the connection between the elementary cells, through which each elementary cell of one unit of a computing device connected to the respective other unit cell of another unit of the computing devices of the same order.

You must specify that the individual subunits do not have to be strictly parallel to each other, i.e. not necessarily the case that the distance between two elementary cells of the same order of magnitude is always less than the spatial interval between the elementary cell of the first unit of the computing device and the unit cell per unit of a larger order of the second unit of a computing device. If, for example, subunit 5 is shifted in the vertical direction on the length of the half, full or multiple unit cells, however, the effect according to this invention is still achieved, although the measure length between the equivalent of elementary cells in the sub-blocks 1001 and 1005 is the same as the distance from the unit cell of one subunit to the elementary cell of another subunit of the next older or younger discharge.

This is explained below with reference to Fig.6. Figure 6 shows an enlarged fragment of figure 1. On the left of figure 6 shows the first block 10 computing device and, in particular, the unit cell of order i+2, i+1, i, i-1, i-2. Right on 6 shows a second block of the computing device with the elementary cells (i+3, i+2, i+1, i, i-1, i-2. It is assumed that the height of each unit cell is equal in both blocks. The height of each unit cell is indicated at 6 h. On this basis, both the unit is not placed exactly at the same height, as shown in Fig.6, and offset from each other by a distance equal to half the height (h/2). It should be noted that there are other possible offset values, in which one can still achieve the shortest connection between the elementary cells of the same order, provided that the offset v between the two blocks of the computing device is 0.

Line 14a between the two elementary cells of the same order in both blocks of the computing device indicated at 6 by the solid line. According to the invention, both units of a computing device are placed so that the length of the transmission line 14a is shorter than the average distance between the unit cell i of the first unit of the computing device and at least two elementary cells of a different order, for example, electricity is entername cells of order i+1 and i-1 or i+1, i+2 of the second unit of a computing device. The distance between the unit cell 10A and the unit cell of the next older category in block 12 of the computing device, that is, the unit cell i+1 is indicated in Fig.6 as 60. From Fig.6 shows that this distance is equal to the length of the transmission line 14a. From Fig.6 also shows that the distance between the unit cell 10A of the first unit of the computing device and, for example, the unit cell with the order i-1, which is marked on the 6 as 62, is greater than the distance 60. If you calculate a simple average of the two distances 60, 62, it will appear that it is the arithmetic mean is greater than the length of the transmission line 14a.

You should indicate that to the present invention it does not matter whether both units computing device the shape of a rectangular columns, which are placed parallel to each other. Instead, the blocks of the computing device can be in the form of a rectangular column, which is placed at an angle to each other. Blocks of computing devices can also be circular segments, and a separate unit cell can be in the form of a circular sector, i.e. they need not be strictly rectangular. Moreover, the individual dimensions of unit cells need not be identical, although it is preferable in the sense of more p is ostogo circuit design and a simpler layout.

Each computing device according to the invention has the advantage, which is that of an elementary cell of the same order are arranged to each other that you can use a short connecting line to provide fast, fully parallel exchange of data between the registers of unit cells of both blocks of the computing device, if both blocks of a computing device operating as a separate computing device.

It should also be noted, as shown in figure 5 configuration of the computing device may operate in such a way that parallel will work four separate computing device. This is achieved by additional switches 50A, 50B mounted between the sub-blocks 1002 and 1003 and respectively between subunits 1006 and 1007. In this case, there are four independent from each other shorter computing device, namely, the first computing device, which consists of subunits 1 and 2; the second computing device, consisting of subunits 5 and 6; the third computing device, consisting of subunits 3 and 4, and the fourth computing device, consisting of subunits 1007 and 1008.

From figure 5 it is seen that four of the computing device is placed in relation to each other so that who is ogen rapid exchange of data between registers two separate computing devices.

If appropriate connectors embedded switches from 52a to 52d, as shown in figure 5, the configuration of the computing device can be used as eight separate computing devices, each computing device has a number of elementary cells equal to the number of unit cells in the sub 1001-1007.

From figure 5 it is seen that the invention computing device meander structure is optimally scalable. It can function as a computing device long numbers, and if you open the switch 22, it can act as two short computing device. If you open the switch 22 switches 50A and 50B are also open, the computing device can function as four short computing device, always possible the rapid exchange of data between two neighboring computing devices via communication lines.

Description of the drawings

10the first unit of the computing device
10Aunit cell i
10bLSB1-elementary cell
10CMSB1-elementary cell
12the second BL is to computing devices
12Aunit cell i
12bLSB1-elementary cell
12sMSB1-elementary cell
14aline
14bline
14Cline
16the control unit
18line transfer
20configures the device
22switching devices transfer
50A-50bswitch configurations
52a-52dswitch configurations
60, 62the distance between non-equivalent elementary cells
90elementary cell
91the first computing device long numbers
92the second computing device long numbers
93bus interface
94bus interface
101the first subblock of the first unit of the computing device
102the second subunit of the first unit of the computing device
110register cell for the first operand
112register cell for the second operand
114the adder
116register cell for the result
121the first subblock of the second unit of the computing device
122the second subunit of the second unit of the computing device
1001-1008the subunits

1. The configurable device for exchanging data between computing devices that handle long integers containing the first block (10) of the computing device, which consists of a first set of elementary cells (10A, 10b, 10 C), which include elementary cell (10b) for the LSB of the first operand and the elementary cell (10C) for high-order bit of the first operand, each elementary cell of the first unit of the computing device has at least one register cell for storing digits of the first operand or discharge of the calculated unit cell, and the first computing unit the device consists of at least four subunits (1001, 1002, 1003, 1004) and each of at least four subunits (1001, 1002, 1003, 1004) consists of e is ementary cells, the second block (12) of the computing device, which consists of a second number of elementary cells (12A, 12b, 12C), which include elementary cell (12b) for the LSB of the second operand, and a unit cell (12C) for high-order bit of the second operand, each elementary cell of the second block (12) of the computing device has a register cell to be stored in memory of the discharge of the second operand or discharge of the calculated unit cell and the second unit of the computing device consists of at least four subunits (1005, 1006, 1007, 1008 and each of at least four subunits (1005, 1006, 1007, 1008) consists of unit cells, while the first and second blocks (10, 12) spatial computing device is placed in relation to each other so that the distance between the unit cell (10A) of the first block (10) of the computing device and the equivalent unit cell (12A) of the second unit of the computing device is smaller than the average distance between the unit cell (10A) of the first block (10) of the computing device and uneven elementary cells (12b, 12C the second block (12) of the computing device, the first subunit (1005) of the second unit of the computing device is located between the first subunit (1001) and the second sub the beginning (1002) of the first unit of the computing device, and the direction from the unit cell for the LSB to the unit cell for high-order bit of the first subunit (1005) of the second unit of the computing device is identical with the direction of the unit cell for the LSB to the unit cell for high-order bit of the first subunit (1001) of the first unit of the computing device when the direction from the unit cell for the LSB to the unit cell for high-order bit of the first subunit (1005) of the second unit of a computing device opposite to the direction from the unit cell for the LSB to the unit cell for the senior level of the second subunit (1002) of the first unit of the computing device while the second sub (1006) of the second unit of the computing device is located near the second subunit (1002) of the first unit of the computing device, the fourth subunit (1008) of the second unit of the computing device is located between the third subunit (1003) and the fourth subunit (1004) of the first unit of the computing device and the third subunit (1007) of the second unit of the computing device is located next to the third subunit (1003) of the first unit of the computing device, a means of communication with the number of communication lines (14a, 14b, 14C), which is equal to the number of elementary cells in the block (10, 12) computing the about device, this line connects the at least one register cell unit cell of some significance of the first unit (10) of the computing device to registered cell unit cell of the same significance of the second unit (12) for computing devices and communication lines are located between the two subunits (1001, 1005), which have the same direction of the unit cell for the LSB to the unit cell for senior level subunits (1001, 1005), and means (16) to load the contents of register cell block (10) of the computing device after a certain number of lines (14a, 14b, 14C) in the register cell of another block (12) of the computing device.

2. The device according to claim 1, characterized in that it further comprises a switchable line transfer (18) for connecting the output of the transfer unit cell (10C) for high-order bit of the first block (10) of the computing device with the input of the transfer unit cell (12b) for the LSB of the second unit of the computing device and the configuration tool (20) for switching a switchable line transfer (18)to configure the first and second blocks (10, 12) of the computing device as a single computing device to the first operand and the second operand could be treated as a common operand, and partyblack computing device is provided for younger categories General operand, and the second unit of a computing device is provided to the senior ranks of the common operand.

3. The device according to claim 1, characterized in that the elementary cell for the LSB of the first subunit (1001) of the first block (10) of the computing device is located near an elementary cell for the LSB of the first subunit (1005) of the second unit (12) of the computing device, the elementary cell for high-order bit of the first subunit (1001) of the first block (10) of the computing device is located near an elementary cell for high-order bit of the first subunit (1005) of the second unit (12) of the computing device, the elementary cell for the LSB of the second subunit (1002) of the first unit (10) computing the device is located near an elementary cell for the Junior category of the second subunit (1006) of the second unit (12) of the computing device and unit cell for the senior level of the second subunit (1002) of the first block (10) of the computing device is located near an elementary cell for the senior level of the second subunit (1006) of the second unit (12) of the computing device.

4. The device according to claim 1, characterized in that the number of elementary cells in each subblock of the first and second blocks of a computing device in the same way.

5. The device according to claim 2, characterized in that each su is a block has a geometric horizontal size and geometric vertical dimension and each subunit is located, essentially parallel to the other subunits, forming a window in which the alternately arranged first sub unit of a computing device and a subunit of the second unit of a computing device.

6. The device according to claim 1, characterized in that each elementary cell contains at least two register cells of the input operands and register the result cell, each unit cell is designed to load the contents of register cells result in the register cell of the input operand of the same unit cell.

7. The device according to claim 1, characterized in that each elementary cell contains at least two register cells of the input operands and register the result cell, and the means (16) to load the contents of register cells is to download the content of the register cells of the first unit of a computing device in the register cell of the input operand of the second unit of the computing device through a communication line (14a)associated with the elementary cell of the same significance, and means (16) to load the contents of register cells is to download the content of the register cells of the second unit of the computing device in the register cell of the input operand of the first block vychislitel the first device through the communication line (14a), correlated with the elementary cells of the same value.

8. The device according to claim 1, characterized in that it is made in the form of computing device, long integers.

9. The device according to claim 8, characterized in that the first unit of the computing device consists of more than 160 elementary cell and the second unit of the computing device also consists of more than 160 elementary cells.

10. The device according to claim 1, characterized in that between the subunits (1004) of the first unit of a computing device and a subunit (1005) of the second unit of the computing device has a configuration switch (22), which in the open position configures the first and second blocks of the computing device as independent from other blocks of the computing device.

11. The device according to claim 10, characterized in that between the corresponding two subunits (1002, 1003; 1006, 1007) of one unit of a computing device installed additional switches (50A, 50b), and the above-mentioned switches (50A, 50b) in the open position is formed from the first and second blocks of the computing device four independent one from another computing device, each of which consists of two subunits(1001, 1002; 1003, 1004; 1005, 1006; 1007, 1008).

12. The device according to claim 10 or 11, characterized in that it contains additional switches (52a, 52b, 52, 52d) for separation of all subunits from each other so that when the open state of auxiliary switches (52a, 52b, 52, 52d,a computational device into eight independent from each other computing devices.



 

Same patents:

FIELD: engineering of data processing systems, which realize operations of type "one command stream and multiple data streams".

SUBSTANCE: system is disclosed with command (ADD8TO16), which decompresses non-adjacent parts of data word with utilization of signed or zero expansion and combines them by means of arithmetic operation "one command stream, multiple data streams", such as adding, performed in response to one and the same command. Command is especially useful for utilization in systems having a data channel, containing a shifting circuit before the arithmetic circuit.

EFFECT: possible use for existing processing resources in data processing system in a more efficient way.

3 cl, 5 dwg

The invention relates to data processing systems

FIELD: engineering of data processing systems, which realize operations of type "one command stream and multiple data streams".

SUBSTANCE: system is disclosed with command (ADD8TO16), which decompresses non-adjacent parts of data word with utilization of signed or zero expansion and combines them by means of arithmetic operation "one command stream, multiple data streams", such as adding, performed in response to one and the same command. Command is especially useful for utilization in systems having a data channel, containing a shifting circuit before the arithmetic circuit.

EFFECT: possible use for existing processing resources in data processing system in a more efficient way.

3 cl, 5 dwg

FIELD: computing devices with configurable number length for long numbers.

SUBSTANCE: device consists of two computing device units, each of them divided into at least four subunits, which consist of a quantity of unit cells. Named units are spatially located so that the distance between unit cell of first unit and equal unit cell in the second unit is minimal. Computing device configuration can be changed using configurational switches, which are installed between device subunits.

EFFECT: increased performance of computing device, reduced time of data processing.

12 cl, 6 dwg

FIELD: physics, computer engineering.

SUBSTANCE: group of inventions relates to computer engineering and can be used in arithmetic processors. A processor receives at least one floating-point operand and performs a floating-point operation using at least one floating-point operand to provide a floating-point result. The method includes determining if a preferred quantum is stored in the floating-point result, said quantum indicating a value which is presented as the least significant digit of the significant of the floating-point result. An indication of the occurrence of a quantum exclusion is provided at the output in response to the determination that the preferred quantum is not stored.

EFFECT: high accuracy.

18 cl, 3 dwg

FIELD: physics, computer engineering.

SUBSTANCE: group of inventions relates to computer engineering and can be used to convert data. The method includes steps of obtaining, by a processor, a machine instruction for execution, wherein the machine instruction is defined for execution by the processor according to computer architecture and includes at least one operation code field which provides an operation code, the operation code identifying a conversion function from a zoned from decimal floating-point; a first register field defining a first operand cell; a second register field and a displacement field, wherein contents of a second register defined by the second register field are combined with contents of the displacement field to form an address of a second operand; and a sign directive used to indicate whether the second operand has a sign field; and executing the machine instruction, which includes converting the second operand in a zoned format to a decimal floating-point format; and placing the conversion result in the first operand cell.

EFFECT: high efficiency.

20 cl, 18 dwg, 6 tbl

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