Processing of message digest generation commands

FIELD: information technologies.

SUBSTANCE: command of message digest generation is selected from memory, in response to selection of message digest generation command from memory on the basis of previously specified code of function, operation of message digest generation, which is subject to execution, is determined, at that previously specified code of function defines operation of message digest calculation or operation of function request, if determined operation of message digest generation subject to execution is operation of message digest calculation, in respect to operand, operation of message digest calculation is executed, which contains algorithm of hash coding, if determined operation of message digest generation subject to execution is operation of function request, bits of condition word are stored in block of parameters that correspond to one or several codes of function installed in processor.

EFFECT: expansion of computer field by addition of new commands or instructions.

14 cl, 18 dwg

 

The present invention relates to the architecture of the computing system and, in particular, to processing new commands that extend the z-architecture IBM and can be emulated by other architectures.

Until the present invention, since the 60-ies of the last century, when computers were created, known under the name of the S/360, and up to the present time the work of many talented engineers, IBM has established a special architecture, which due to its natural facilities to computer systems called "mainframe" ("mainframe" is a powerful, universal computer), and the principles which determine the architecture of the machine, describing implemented in the mainframe commands, which were invented at IBM and which, on account of their recognized over the past years significant contribution to the improvement of computing machinery mainframes, were included in the principles of operation of systems of IBM. The first edition of "principles of operation z-architecture" was published in December 2000 in the form of a published standard reference, SA22-7832-00.

The authors found that the development of this field of technology can facilitate new additional commands or instructions that may be included in the computers the z-architecture, and can emalirov the sterile other developers in a more simple machines that is discussed below.

In the present invention proposes a method of generating digests (such digests are also called message profiles, as well as hashes or hash values) memory computing environment, namely, that through commands set the memory unit for which you want to generate a digest, and generate digest data stored in the memory unit.

Particularly preferred embodiments of the invention will become apparent to a person skilled from the following detailed description of the invention accompanied by drawings on which is shown:

figure 1 - command "compute intermediate message digest" (KIMD) in the command format RRE,

figure 2 - command "compute last message digest" (KLMD) in the command format RRE,

figure 3 is a table which shows the function codes for the command KIMD, shown in figure 1,

figure 4 is a table which shows the function codes for the command KLMD shown in figure 2,

figure 5 - assigning teams KIMD and KLMD shown in figures 1 and 2, the values in the General purpose register (GR),

figure 6 - the symbol using block generation algorithm digest SHA-1 (algorithm secure hash),

7 format of parameter block for KIMD-query

on Fig format of parameter block for KIMD-SHA-1

nafig - operation KIMD-SHA-1

figure 10 - the format of parameter block for KLMD-query

figure 11 - the format of parameter block for KLMD-SHA-1

on Fig - operation KLMD-SHA-1 with full block

on Fig - operation KLMD-SHA-1 with empty block

on Fig - operation KLMD-SHA-1 with a partially filled block in case 1,

on Fig - operation KLMD-SHA-1 with a partially filled block in the case of 2

on Fig - table, which shows the priority of the commands KIMD and KLMD,

on Fig - cryptographic coprocessor, and

on Fig - generic preferred variant implementation of the computer's memory that stores command corresponding to a preferred variant of the invention, and data, as well as the mechanism fetch, decode and execute such commands or computing system, which uses the commands of the architecture, or in emulation of such commands.

Included in this command description generate message digests are used to compute a condensed representation of a message or data file. First it looks at the command "compute intermediate message digest" and "compute last message digest", and then described the preferred computer system for executing such commands. In the alternative possibility of a second preferred computing system, which is the carrying out of such commands emulates another computing system.

Command "compute intermediate message digest" (KIMD)

Figure 1 shows the command "compute intermediate message digest" (KIMD) RRE instruction format.

Command "compute last message digest" (KLMD)

Figure 2 presents the command "compute last message digest" (KLMD) RRE instruction format.

Executes the function specified by the function code in register 0 General purpose.

Bits 16-23 team and field R1 are ignored.

The bits 57-63 register 0 General purpose contains function code. Figure 3 and 4 shows the function codes assigned to the command "compute intermediate message digest" and "compute last message digest", respectively. All other function codes are free (not assigned). The discharge 56 General register must be zero, otherwise it is determined by the exceptional situation when the violation of the specified terms. All the other bits of register 0 General purpose ignored. Register 1 General purpose contains the logical address of the leftmost byte of the parameter block that is stored in memory. In 24-bit addressing, the contents of bits 40-63 of the register 1 General purpose is to address, and the contents of bits 0-39 ignored. Mode 31-bit addressing, the contents of bits 33-63 of the register 1 General purpose is to address and contain imoe bits 0-32 ignored. Mode 64-bit addressing, the contents of bits 0-63 of the register 1 General purpose is the address.

Figure 3 shows the function codes command "compute intermediate message digest".

Figure 4 shows the function codes command "compute last message digest".

All other function codes are free (not assigned).

The query function is a means of indicating the availability of other functions. For the query function, the contents of registers R2 and R2+1 General purpose is ignored.

For all other functions the second operand is treated in accordance with how it is specified by the function code using the initial values of the chain in the parameter block, and the result replaces the value chain. For the command "compute last message digest by performing this operation also uses the length of the message in bits in the parameter block. The operation is carried out until reaching the location of the end of the second operand or the processing of the number of bytes specified by the Central processing unit (CPU), whichever occurs sooner. The result indicate in code terms.

Field R2 designates an even-odd pair of General purpose registers and must match the case with an even number, otherwise it is determined by the exceptional situation when the violation of the specified terms.

The location of the leftmost byte of the second operand specifies the contents of register R2 General purpose. The number of bytes in the location of the second operand is set in the register R2+1 General purpose.

When performing the address in register R2 General purpose increases with the number of processed bytes from the second operand, and the length in register R2+1 General purpose reduced by the same number of bytes. The form and update the address and its length depends on the addressing mode.

In 24-bit addressing, the contents of bits 40-63 of the register R2 General purpose is the address of the second operand and the contents of bits 0-39 ignored; bits 40-63 updated addresses replace the corresponding bits in register R2 General purpose transfers discharge 40 updated address are ignored, and the contents of bits 32-39 of the register R2 General purpose is set to zero. Mode 31-bit addressing, the contents of bits 33-63 of the register R_ General purpose is the address of the second operand and the contents of bits 0-32 ignored; bits 33-63 updated addresses replace the corresponding bits in register R2 General purpose transfers discharge 33 updated address are ignored, and the contents of order 32 of the register R2 General purpose is set to zero. Mode 64-bit addressing is obsessed bits 0-63 of the register R2 General purpose is the address of the second operand; the bits 0-63 updated address replaces the contents of register R_ General purpose, and transfers the bit 0 is ignored.

In two modes : 24-bit and 31-bit addressing, the contents of bits 32-63 of the register R2+1 General purpose is a 32-bit binary integer unsigned number that specifies the number of bytes in the second operand, and the updated value replaces the contents of bits 32-63 of the register R2+1 General purpose. Mode 64-bit addressing, the contents of bits 0-63 of the register R2+1 General purpose forms a 64-bit binary integer unsigned number that specifies the number of bytes in the second operand, and the updated value replaces the contents of register R2+1 General purpose.

In modes 24-bit and 31-bit addressing, the contents of bits 0-31 of register R2 and R2+1 General purpose always remains the same.

Figure 5 shows the contents of the above-described General-purpose registers. Mode addressing using register access (AR) registers access 1 and R2 specify the address space containing the parameter block and the second operand, respectively.

The result is similar to the result of processing, starting from the left end of the second operand, and continue to the right block by block. The operation ends when you have processed all the original bytes in the second operand (which is enoeda normal end) or when processed the specified CPU number of blocks, which is less than the length of the second operand (which is referred to as partial completion). The specified CPU number of blocks depends on the model and may be different each time you run the command. As a rule, the specified CPU number of blocks is not equal to zero. In some emergency situations such number may be zero, and can be set in code terms 3 without moving forward (loop). However, the CPU provides protection from the endless repetition in this case the loops.

If the field value chain overlaps any portion of the second operand, the result obtained in the field of value chain is unpredictable.

For the command "compute intermediate message digest" normal termination occurs when processed the number of bytes in the second operand, which is specified in the register R2+1 General purpose. For the command "compute last message digest" after you have processed all the bytes in the second operand is set in the register R2+1 General purpose operation is in progress additions, then there is a normal termination.

If the operation has been due to the normal completion code is set terms 0 and the value in register R2+1 is zero. If the operation has been due to partial completion code is set condition 3, and the obtained value is in Regis is re R2+1 is not zero.

When the length of the second operand is initially zero, the second operand is not performed, the registers R2 and R2+1 General purpose does not change, and code set conditions 0. For the command "compute intermediate message digest" access to block parameters does not occur. However, for the command "compute last message digest" perform the operation of additions empty block (L=0), and the result is stored in the parameter block.

From the point of view of the other CPU and channel programs references to the parameter block and stored in the memory operands can be links, multiple access, access to such cells in the memory need not be carried out simultaneously with the access to the parameter block, and the sequence of these accesses or links are not defined.

On exceptional situations in access (exceptions access) can be reported in relation to the larger part of the second operand, than the part to be processed in one operation command; however, exceptions to access are not recognized in relation to locations outside the length of the second operand, and locations at a distance of more than 4 KB from the current workpiece location.

The symbols used in the description of functions

In the further description of the functions "vechicle is their intermediate message digest" and "compute last message digest" uses characters shown in Fig.6. In more detail, the algorithm secure hash described in the publication "Secure Hash Standard", Federal standards for information processing, issue 180-1, national Institute of standards and technology (NIST), Washington, DC, April 17, 1995

KIMD-request (code KIMD-function 0)

The location of the operands and addresses used by this command correspond shown in figure 5.

7 shows the format of the parameter block KIMD request.

In the parameter block is stored 128-bit status word. The bits 0-127 of this field correspond to the codes functions respectively 0-127 command "compute intermediate message digest". If the bit is one, the corresponding function is set; otherwise, the feature is not installed.

Upon completion of the execution of the function KIMD request code set conditions 0; code conditions 3 to this function is not applicable.

KIMD-SHA-1 (code KIMD-function 1)

The location of the operands and addresses used by this command correspond shown in figure 5.

On Fig shows the format of the parameter block used for the function KIMD-SHA-1.

For a 64-byte message block in operand 2 generate a 20-byte intermediate digest (profile) of a message (or a hash), using a block algorithm SHA-1 generation digests with 20-byte value chain in the parameter block. Sgenerirovanny the message digest, also called output value chains (OCV from English. "Output Chaining Value"), save in field value chain block parameters. Operation KIMD-SHA-1 is shown in Fig.9.

KLMD-request (code KLMD-function 0)

The location of the operands and addresses used by this command correspond shown in figure 5.

Figure 10 shows the format of the parameter block used for the function KLMD request.

In the parameter block is stored 128-bit status word. The bits 0-127 of this field correspond to the codes of the functions 0-127, respectively, the command "compute last message digest". When the presence of a single discharge is set, the corresponding function; otherwise, the feature is not installed.

Upon completion of the execution of the function KLMD request code applies conditions 0; code condition 3 is not applicable to this function.

KLMD-SHA-1 (code KLMD-function 1)

The location of the operands and addresses used by this command correspond shown in figure 5.

Figure 11 shows the format of the parameter block used for the function KLMD-SHA-1.

In operand 2 to generate the message digest (M), using SHA-1 to generate a digest (hash) value chain and information about the message length in bits, stored in the parameter block.

If the length of the message in operand 2 is greater than or equal to 64 bytes, for each 64-byte BL is ka messages generate an intermediate message digest, using a block algorithm SHA-1 generation digests with 20-byte value chain in the parameter block, and the generated intermediate message digest, which is also called the output value chains (OCV), remain in the field of value chain block parameters. This operation, which is shown in Fig repeatedly carried out until such time as the remaining message will not be less than 64 bytes. If the length of the message, or the remaining messages is zero bytes, perform the operation shown in Fig.

If the length of the message, or the remaining message is from one byte up to 55 bytes, inclusive, perform the operation shown in Fig; if length ranges from 56 to 63 bytes, inclusive, perform the operation shown in Fig. The message digest, which is also called the output value chains (OCV), remain in the field of value chain block parameters.

Additional symbols used in functions KLMD

When the function description compute last message digest to use the following additional notation:

L is the length in bytes of operand 2 in memory

R<n> n-the number of bytes placeholder; the leftmost byte is a hexadecimal value 80, all of the remaining bytes is hexadecimal value 00

Z<56> 56 zero byte placeholder

Mb1 8-byte value that is surrounding the length in bits of all messages

q<64> consisting of 56 zero-byte-block-placeholder, followed by 8-byte value of Mb1.

Special conditions for KIMD and KLMD

When any of the following conditions is determined by the exceptional situation when the violation of the specified terms and not taken any steps:

1. The discharge 56 register 0 General purpose is not equal to zero.

2. The bits 57-63 register 0 General purpose point code is unassigned or unknown functions.

3. Field R2 denotes a register with an odd number or register 0 General purpose.

4. Functions compute intermediate message digest length of the second operand is not a multiple of the block size of the data specified function (to determine the size of the data blocks for functions "compute intermediate message digest", see figure 3). This is an exceptional situation when the violation of the specified conditions is not part of the query function or functions compute last message digest".

Get code conditions:

0 normal termination

1 --

2 --

3 is a partial end

Software exceptions:

access (fetch, operand 2 and the length of the message in bits; sampling and preservation, value chain);

when performing the operation (if not installed auxiliary program a privacy message);

if n is the violation of the specified conditions.

Notes on programming:

1. The discharge 56 register 0 General purpose reserved for future expansion and must be set to zero.

2. If key is specified condition 3, the address and length of the second operand registers R2 and R2+1 General purpose, respectively, and the value chain in the parameter block will usually update so that the program can easily return to the team and to continue the operation.

In emergency situations the CPU protects from the endless repetition of the operations in the loop cases. Thus, whatever was specified code condition 3, the program may return to the team without loops.

3. If the length of the second operand is not initially zero and code set conditions 0, the update of the registers is the same as in code condition 3; the value chain in this case is that the processing of additional operands can be carried out in the same manner as if they were part of the same chain.

4. Command "compute intermediate message digest" and "compute last message digest" is designed for their use of the application programming interface (PPI) system service protection. Such PPIS provide program funds calculate digests for messages of virtually unlimited size, including message size is too large for so you can save immediately. To do this, the program can send a message to the STI parts. The following explanation of the programming is written in a language such PPIS.

5. Before processing the first part of the message, the program should set the initial values for the field value chain. For SHA-1 the initial values of the chain are listed below:

H0=x'6745 2301'

H1=x EFCD AB89'

H2=h WE DCFE'

H3=x'1032 5476'

H4=x C3D2 E1F0'

6. When handling any parts of the message, except the last, the program should process the message part, multiples of 512 bits (64 bytes), and use the command "compute intermediate message digest".

7. While processing the last part of the message, the program should calculate the length of the original message in bits, to put this 64-bit field of the message length in bits of the parameter block and use the command "compute last message digest".

8. For the command "compute last message digest" does not require that the second operand is not a multiple of block size. First and foremost is to process full blocks, and the processing of all blocks can be specified code conditions 3. Next, after processing all full blocks perform the operation of additions, including the remaining portion of the second operand. This may require one or more cycles is terachi block SHA-1 generation digests.

9. Command "compute last message digest" provides additions messages in accordance with the requirements of SHA-1 for message whose length is a multiple of eight bits. If the SHA-1 algorithm to be applied to the sequence of bits is not a multiple of eight bits, the program must make additions to the desired size and use the command "compute intermediate message digest".

Cryptographic coprocessor

In a preferred embodiment, the invention provides for the use of cryptographic coprocessor (coprocessor cryptographic support)that can be used in combination with the above commands, and to perform encrypted messages and as an adjuvant for a variety of tasks clutch messages that can be used to grip and cryptographic application in conjunction with relevant commands.

On Fig shown cryptographic coprocessor, which is directly connected to the data path common to all internal actuators on the universal microprocessor, which has several operating conveyors. Internal bus 1 microprocessor, which is common for all other actuators are connected to obligationsin unit 2 control which tracks on the bus command processor, which it should execute.

The cryptographic control unit serves as a cryptographic coprocessor, which is directly connected with the data path common to all internal execution units of the CPU on the universal microprocessor, providing affordable hardware (E0...En) or combinations thereof in a preferred embodiment, operating conveyors). When in register 3 teams cryptographic commands unit 2 control causes of the available hardware, the corresponding algorithm. Data through the input operand register 4, operating on the principle of service in order of arrival (FIFO-register), go through the same internal bus of the microprocessor. Upon completion of the operation in the register 6 status is a flag, and the results can be read from the output FIFO register 5.

In the illustrated preferred embodiment, the invention is intended to build to turn on as many hardware machines as required by the specific implementation depending on the objectives for the system. Data transfer path in the direction of the input and output registers 7 are common to all machines.

In the preferred variationbetween invention cryptographic functions are implemented in the hardware of the Executive device for the CPU, due to less waiting time (delay) when the invocation and execution of cryptographic operations and increased efficiency.

By reducing the waiting time significantly expand the possibilities of universal processors in systems where often performed many cryptographic operations, especially if we are talking only about small amounts of data. This makes possible the implementation, could significantly speed up the processes associated with the implementation of a secure online transaction. The most common ways to ensure the security of online transactions involve the use of a set of three algorithms. The first algorithm is used once per session and can be implemented in either hardware or software, and other algorithms are called when each transaction during the session, while the present invention eliminates the time associated with the delay when calling external hardware, and the algorithm is executed by means of software.

On Fig shows the conceptual implementation of the preferred alternative implementation of the invention on the example of the mainframe with the above-described microprocessor, which, as proved experimentally in IBM, can be effectively used in the mass implementation of the proposed architecture for whom is utero with functionality long offset, used by programmers, these days typically the programmers working on the language "C". Such formats of commands that are stored in the storage device may implement a "native" for them, the IBM z architecture or, as an option, computing machines based on other architectures. They can emulate existing and future IBM class mainframe and other IBM machines (for example, servers, series R and servers x series). They can be run using the operating system a variety of Linux-based computers, hardware, IBM, Intel, AMD, Sun Microsystems and other companies. In addition to performing such hardware z-architecture, Linux can also be used in machines that use emulation on the basis of Hercules, UMX, FXI or Platform Solutions, in which the execution mode in General is an emulation mode. In emulation mode perform decoding of a particular emulated team and form a standard routine for the implementation of individual commands in the form of routine or driver on the language or create a driver for a specific hardware otherwise available to specialists in the art, familiar with the description of the preferred option implementation. Different ways of implementation on the target computer emulation command format, the architecture to the categories developed for execution on another computer, as well as commercially available software tools used in these purposes described in several patents, revealing software and hardware emulation, including, without limitation, patents US 5551013, US 6009261, US 5574873, US 6308255, US 6463532 and US 5790825.

In this preferred embodiment of the invention formats for superscalar team prior to the format with a long offset, form the address of the storage operand by adding a base register and a 12-bit offset unsigned or base register, index register and a 12-bit offset unsigned and new formats of commands with a long offset form the address of the storage operand by adding a base register and a 20-bit signed offset or base register, index register and a 20-bit signed offset.

As shown in Fig, such commands are executed by the hardware processor, or by emulation of such a command set software installed on a computer with others your own, or "native"instruction set.

On Fig position 501 designated memory (storage device) of the computer that stores commands and data. This computer originally stored is described in the present invention the team with a long offset. Position 502 indicated the mechanism of fetching from memory the minute computer which can also provide the location of the selected commands in the local buffer storage device. Then the teams in the original form received in the decoder 503 command that specifies the type of the selected command. Position 504 identified the mechanism of the commands. It may include loading data into a register from memory 501, the data from a register into memory or perform any arithmetic or logical operations. The type of such operations are predefined decoder commands. In this case, are described in the present invention the team with a long offset. If a team with a long offset run in a native computer system, the process is terminated as described above. If the command set with the structure that contains the commands with a long offset, emulates another computer, the described process will be implemented in the host computer 505 software. In this case, the above-mentioned mechanisms, as a rule, will be implemented in the form of one or more standard system routines within the emulation software. In both cases there is a call, the decoding (decoding) and the command.

In particular, commands, this architecture can be used with a computer architecture that uses existing formats whom the nd 12-bit offset unsigned used to generate the address of the storage operand, as well as the architecture, which uses additional formats of commands that provide additional discharges offset, preferably 20 digits representing increased displacement with the token used to generate the address of the storage operand. Team this architecture is a computer software that is stored in a storage device of the computer and is used for code generation, coming from the processor, which uses computer software, and contains the command code used by the compiler / emulator/interpreter stored in the storage device 501 of the computer, with the first part of the command code contains the opcode that specifies the operation you want to perform, and the second part assigns the operands to participate in its implementation. When using commands with a long offset, it becomes possible to directly access additional addresses.

As shown in Fig, such commands are executed by the hardware processor, or by emulating the specified command set - software running on a computer with a different native instruction set.

In accordance with the computer architecture used in a preferred embodiment, from which retene, the offset field consists of two parts, with the least significant part consists of 12 bits and is denoted by DL, DL1 - for operand 1 or DL2 - for operand 2, and the most significant part consists of 8 bits and is denoted by DH, DH1 - for operand 1 or DH2 - for operand 2.

In addition, in the preferred computer architecture, the format for the command is that the code operations correspond to the digits 0 through 7 and from 40 to 47, the target register, called R1, correspond to the bits 8 through 11, the index register, called x2 correspond to the bits 12 through 15, the base register, called B2 correspond to the bits 16 through 19, the first part consisting of the two parts of the displacement, which is called DL2, correspond to the bits 20 through 31, and the second part, which is called DH2, correspond to bits 32 through 39.

This computer architecture has such a command format that code operations correspond to the digits 0 through 7 and from 40 to 47, the target register, called R1, correspond to the bits 8 through 11, the source register, called R3 correspond to the bits 12 through 15, the base register, called B2 correspond to the bits 16 through 19, the first part consisting of the two parts of the displacement, which is called DL2, correspond to the bits 20 through 31, and the second part, which is called DH2, correspond to bits 32 through 39.

In addition, the proposed architecture computers is a team with a long offset have this format, that code operations correspond to the digits 0 through 7 and from 40 to 47, the target register, called R1, correspond to the bits 8 through 11, the mask value, called the MOH, correspond to the bits 12 through 15, the base register, called B2 correspond to the bits 16 through 19, the first part consisting of the two parts of the displacement, which is called DL2, correspond to the bits 20 through 31, and the second part, which is called DH2, correspond to bits 32 through 39.

As shown above, the preferred computer architecture with a long offset has such a command format that code operations correspond to the digits 0 through 7 and from 40 to 47, the immediate value called 12 correspond to the bits 8 through 15, the base register, called B2 correspond to the bits 16 through 19, the first part consisting of the two parts of the displacement, which is called DL1, correspond to the bits 20 through 31, and the second part, which is called DH1, correspond to bits 32 through 39.

Proposed invention is a computer architecture with a long offset is effective when working with new created teams that applied only command format with the new 20-bit offset unsigned.

In a special embodiment of the proposed invention in computer architecture uses existing commands, formats which have only a 12-bit offset b is C sign and in new formats are defined as having an existing 12-bit offset unsigned if the 8 high-order bits in the offset field of the DH are zero bits, or as having a 20-bit signed offset, if the 8 high-order bits in the offset field of the DH are not zero digits.

Another form of the invention is a device for generating a digest of the content memory computing environment that contains tools for the job via memory unit for which you want to generate a digest, and the means for generating digest data stored in the memory unit.

1. The way to execute commands generate a message digest that contains the query function in the computing system containing multiple General purpose registers and a universal processor associated with the memory of a computer system containing one or more actuators that executes commands selected from a memory of a computer system, characterized in that it comprises the following stages:

choose from the memory command generating the message digest,

in response to fetching from memory commands generate a message digest based on a predefined function code determines the subject to perform the operation of generating the message digest, and a predefined function code defines the calculation of the message digest and the and operation query functions

if some want to perform the operation of generating the message digest is the calculation of the message digest in respect of the operand perform an operation to calculate the digest of the message containing the hash algorithm

if some want to perform the operation of generating the digest of the message is a query operation function block parameters retain bits of the status word corresponding to one or more function codes set in the processor.

2. The method according to claim 1, wherein the operation of calculating the message digest includes the following stages:

x1) receive a 20-byte value chain

x2) receive 64-byte block operand;

X3) using a 20-byte value chain, perform direct hashing 64-byte block operand to obtain a new 20-byte value chain

x4) repeat stage x2-X3 in respect of successive blocks operand, and

X5) received a new 20-byte value chain stores.

3. The method according to claim 2, characterized in that, when hashed using the SHA-1 algorithm.

4. The method according to claim 2, characterized in that as the value chain retain the 20-byte hexadecimal value '6745 2301', 'EFCD AB89', 'VA DCFE', '1032 5476', 'C3D2 E1F0'.

5. The method according to claim 1, Otley is audica fact, the team generate a message digest consists of commands compute intermediate message digest or commands compute last message digest.

6. The method according to claim 5, wherein if the command generating the message digest is the command compute last message digest, if the operand is less than 64 bytes receive bytes less than 64, and fill it with bytes with a value of '00' to create a 64-byte operand.

7. The method according to claim 1, wherein the command generating message digest includes a code field operations, field R2 defining a pair of General purpose registers, including the first General purpose register containing the address of the operand, and the second General purpose register, which defines the length of the operand, and the preset function code is obtained from the first specified General purpose register that is included in the number of General purpose registers of the processor, and the second specified General purpose register that is included in the multiple General purpose registers, contains the memory address of the parameter block that contains the value chain the method includes the following additional stages:

get the address of a parameter block in memory

from the in-memory parameter block location in the Annex, defined by the received memory address, initially receive a 20-byte value chain, and from the first of the specified General purpose register initially receive a predefined function code,

from the first General purpose register initially receive the address of the operand,

from the second General purpose register initially get the length of the operand, and

originally receive 64-byte block of the operand at the location defined by the received address of the operand.

8. The method according to claim 7, characterized in that the first specified General purpose register is register 0 General purpose, and the second specified General purpose register is a register 1 General purpose.

9. The method according to claim 7, characterized in that the content of the first General purpose register increase according to the number of bytes operands are processed in stages performed, and the contents of the second General purpose register is reduced according to the number of bytes operands are processed in stages performed.

10. The method according to claim 1, wherein when performing the calculation of the message digest only a portion of the operand as a code condition code set conditions "partial complete", indicating that the operation of calculating the message digest is not completed, and the ri operation calculate the message digest for the entire operand as a code condition code set conditions "normal termination", indicates that the operation of calculating the message digest is completed.

11. The method according to claim 1, wherein the command generating message digest format is inherent in the architecture of the processor commands.

12. The method according to claim 1, wherein the command generating message digest format is not inherent in the architecture of the processor commands, and the command generating the message digest is then interpreted to determine a given program that is designed to emulate the commands generate a message digest and contains many of the commands and perform the specified target program.

13. System for generating a digest of the contents of a memory of a computing environment that includes a processor, containing one or more execution units that share a common data path, and the cryptographic coprocessor attached to the specified data path and ensure the operations of the method according to any one of claims 1 to 12.

14. A data carrier for use in a computing environment containing a machine-readable software code that enables generating a digest of the contents of memory specified computing environment by performing the method according to any one of claims 1 to 12.



 

Same patents:

FIELD: physics; computer technology.

SUBSTANCE: present invention pertains to digital signal processors with configurable multiplier-accumulation units and arithmetic-logical units. The device has a first multiplier-accumulation unit for receiving and multiplying the first and second operands, storage of the obtained result in the first intermediate register, adding it to the third operand, a second multiplier-accumulation unit, for receiving and multiplying the fourth and fifth operands, storage of the obtained result in the second intermediate register, adding the sixth operand or with the stored second intermediate result, or with the sum of the stored first and second intermediate results. Multiplier-accumulation units react on the processor instructions for dynamic reconfiguration between the first configuration, in which the first and second multiplier-accumulation units operate independently, and the second configuration, in which the first and second multiplier-accumulation units are connected and operate together.

EFFECT: faster operation of the device and flexible simultaneous carrying out of different types of operations.

21 cl, 9 dwg

FIELD: physics.

SUBSTANCE: invention pertains to the means of providing for computer architecture. Description is given of the method, system and the computer program for computing the data authentication code. The data are stored in the memory of the computing medium. The memory unit required for computing the authentication code is given through commands. During the computing operation the processor defines one of the encoding methods, which is subject to implementation during computation of the authentication code.

EFFECT: wider functional capabilities of the computing system with provision for new extra commands or instructions with possibility of emulating other architectures.

10 cl, 15 dwg

FIELD: engineering of microprocessors and computer systems.

SUBSTANCE: in accordance to shuffling instruction, first operand is received, which contains a set of L data elements, and second operand, which contains a set of L shuffling masks, where each shuffling mask includes a "reset to zero" field and selection field, for each shuffling mask, if the "reset to zero" field of shuffling mask is not set, then data indicated by shuffling mask selection field are moved, from data element of first operand, into associated data element of result, and if "reset to zero" field of shuffling mask is set, then zero is placed in associated data element of result.

EFFECT: improved characteristics of processor and increased productivity thereof.

8 cl, 43 dwg

FIELD: network communications, in particular, control means built into applications for conduction of network exchange.

SUBSTANCE: expandable communication control means is used for maintaining communication between computing device and remote communication device. In a computer program adapted for using expandable communication control means, information about contacting side is found, and on basis of found contact information it is determined which types of transactions may be used for communication with contacting side at remote communication device. As soon as communication setup function is determined using contacting side information, communication setup request, associated with such a function, is dispatched to communication address. After receipt, expandable communication control means begins conduction of communication with remote communication device.

EFFECT: creation of more flexible and adaptable software communication control means (program components) for processing communications (connections, exchange) between devices.

3 cl, 11 dwg

FIELD: computing devices with configurable number length for long numbers.

SUBSTANCE: device consists of two computing device units, each of them divided into at least four subunits, which consist of a quantity of unit cells. Named units are spatially located so that the distance between unit cell of first unit and equal unit cell in the second unit is minimal. Computing device configuration can be changed using configurational switches, which are installed between device subunits.

EFFECT: increased performance of computing device, reduced time of data processing.

12 cl, 6 dwg

FIELD: engineering of data processing systems, which realize operations of type "one command stream and multiple data streams".

SUBSTANCE: system is disclosed with command (ADD8TO16), which decompresses non-adjacent parts of data word with utilization of signed or zero expansion and combines them by means of arithmetic operation "one command stream, multiple data streams", such as adding, performed in response to one and the same command. Command is especially useful for utilization in systems having a data channel, containing a shifting circuit before the arithmetic circuit.

EFFECT: possible use for existing processing resources in data processing system in a more efficient way.

3 cl, 5 dwg

The invention relates to data processing systems having a rated Bank and supporting vector operations

The invention relates to data processing devices

The invention relates to electronics

The invention relates to the addressing of the registers in the processing unit and can be used for digital signal processing

FIELD: engineering of data processing systems, which realize operations of type "one command stream and multiple data streams".

SUBSTANCE: system is disclosed with command (ADD8TO16), which decompresses non-adjacent parts of data word with utilization of signed or zero expansion and combines them by means of arithmetic operation "one command stream, multiple data streams", such as adding, performed in response to one and the same command. Command is especially useful for utilization in systems having a data channel, containing a shifting circuit before the arithmetic circuit.

EFFECT: possible use for existing processing resources in data processing system in a more efficient way.

3 cl, 5 dwg

FIELD: computing devices with configurable number length for long numbers.

SUBSTANCE: device consists of two computing device units, each of them divided into at least four subunits, which consist of a quantity of unit cells. Named units are spatially located so that the distance between unit cell of first unit and equal unit cell in the second unit is minimal. Computing device configuration can be changed using configurational switches, which are installed between device subunits.

EFFECT: increased performance of computing device, reduced time of data processing.

12 cl, 6 dwg

FIELD: network communications, in particular, control means built into applications for conduction of network exchange.

SUBSTANCE: expandable communication control means is used for maintaining communication between computing device and remote communication device. In a computer program adapted for using expandable communication control means, information about contacting side is found, and on basis of found contact information it is determined which types of transactions may be used for communication with contacting side at remote communication device. As soon as communication setup function is determined using contacting side information, communication setup request, associated with such a function, is dispatched to communication address. After receipt, expandable communication control means begins conduction of communication with remote communication device.

EFFECT: creation of more flexible and adaptable software communication control means (program components) for processing communications (connections, exchange) between devices.

3 cl, 11 dwg

FIELD: engineering of microprocessors and computer systems.

SUBSTANCE: in accordance to shuffling instruction, first operand is received, which contains a set of L data elements, and second operand, which contains a set of L shuffling masks, where each shuffling mask includes a "reset to zero" field and selection field, for each shuffling mask, if the "reset to zero" field of shuffling mask is not set, then data indicated by shuffling mask selection field are moved, from data element of first operand, into associated data element of result, and if "reset to zero" field of shuffling mask is set, then zero is placed in associated data element of result.

EFFECT: improved characteristics of processor and increased productivity thereof.

8 cl, 43 dwg

FIELD: physics.

SUBSTANCE: invention pertains to the means of providing for computer architecture. Description is given of the method, system and the computer program for computing the data authentication code. The data are stored in the memory of the computing medium. The memory unit required for computing the authentication code is given through commands. During the computing operation the processor defines one of the encoding methods, which is subject to implementation during computation of the authentication code.

EFFECT: wider functional capabilities of the computing system with provision for new extra commands or instructions with possibility of emulating other architectures.

10 cl, 15 dwg

FIELD: physics; computer technology.

SUBSTANCE: present invention pertains to digital signal processors with configurable multiplier-accumulation units and arithmetic-logical units. The device has a first multiplier-accumulation unit for receiving and multiplying the first and second operands, storage of the obtained result in the first intermediate register, adding it to the third operand, a second multiplier-accumulation unit, for receiving and multiplying the fourth and fifth operands, storage of the obtained result in the second intermediate register, adding the sixth operand or with the stored second intermediate result, or with the sum of the stored first and second intermediate results. Multiplier-accumulation units react on the processor instructions for dynamic reconfiguration between the first configuration, in which the first and second multiplier-accumulation units operate independently, and the second configuration, in which the first and second multiplier-accumulation units are connected and operate together.

EFFECT: faster operation of the device and flexible simultaneous carrying out of different types of operations.

21 cl, 9 dwg

FIELD: information technologies.

SUBSTANCE: command of message digest generation is selected from memory, in response to selection of message digest generation command from memory on the basis of previously specified code of function, operation of message digest generation, which is subject to execution, is determined, at that previously specified code of function defines operation of message digest calculation or operation of function request, if determined operation of message digest generation subject to execution is operation of message digest calculation, in respect to operand, operation of message digest calculation is executed, which contains algorithm of hash coding, if determined operation of message digest generation subject to execution is operation of function request, bits of condition word are stored in block of parameters that correspond to one or several codes of function installed in processor.

EFFECT: expansion of computer field by addition of new commands or instructions.

14 cl, 18 dwg

FIELD: information technology.

SUBSTANCE: present invention relates to computer engineering and can be used in signal processing systems. The device contains an instruction buffer, memory control unit, second level cache memory, integral arithmetic-logic unit (ALU), floating point arithmetic unit and a system controller.

EFFECT: more functional capabilities of the device due to processing signals and images when working with floating point arithmetic.

4 cl, 4 dwg

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to processors with pipeline architecture. The method of correcting an incorrectly early decoded instruction comprises stages on which: the early decoding error is detected and a procedure is called for correcting branching with a destination address for the incorrectly early decoded instruction in response to detection of the said error. The early decoded instruction is evaluated as an instruction, which corresponds to incorrectly predicted branching.

EFFECT: improved processor efficiency.

22 cl, 3 dwg, 1 tbl

FIELD: information technology.

SUBSTANCE: method involves defining a granule which is equal to the smallest length instruction in the instruction set and defining the number of granules making up the longest length instruction in the instruction denoted MAX. The method also involves determining the end of an embedded data segment, when a program is compiled or assembled into the instruction string and inserting a padding of length MAX-1 into the instruction string to the end of the embedded data. Upon pre-decoding of the padded instruction string, a pre-decoder maintains synchronisation with the instructions in the padded instruction string even if embedded data are randomly encoded to resemble an existing instruction in the variable length instruction set.

EFFECT: ensuring reconstruction during repeated synchronisation owing to reduced errors of synchronising the mechanism for pre-decoding the instruction string.

20 cl, 11 dwg

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