Processing of message authentication control commands providing for data security

FIELD: physics.

SUBSTANCE: invention pertains to the means of providing for computer architecture. Description is given of the method, system and the computer program for computing the data authentication code. The data are stored in the memory of the computing medium. The memory unit required for computing the authentication code is given through commands. During the computing operation the processor defines one of the encoding methods, which is subject to implementation during computation of the authentication code.

EFFECT: wider functional capabilities of the computing system with provision for new extra commands or instructions with possibility of emulating other architectures.

10 cl, 15 dwg

 

The invention relates to the architecture of the computing system and, in particular, to new commands that extend the z-architecture IBM and can be emulated by other architectures.

Until the present invention, since the 60-ies of the last century, when computers were created, known under the name of the S/360, and up to the present time the work of many talented engineers, IBM has established a special architecture, which due to its natural facilities to computer systems called "mainframe" ("mainframe" is a powerful, universal computer), and the principles which determine the architecture of the machine, describing implemented in the mainframe commands, which were invented at IBM and which, on account of their recognized over the past years significant contribution to the improvement of computing machinery mainframes, were included in the principles of operation of systems of IBM. The first edition of "principles of operation z-architecture" was published in December 2000 in the form of a published standard reference, SA22-7832-00.

The authors found that the development of this field of technology can facilitate new additional commands or instructions that may be included in the computers the z-architecture, and can be emulated by other developing what uchikomi in more simple machines that is discussed below.

In the present invention proposes a method of calculating the message authentication codes for data stored in a memory of a computing environment by a processor containing a memory in which there is the parameter block for processing commands from the processor. Proposed in the invention the method includes the job through command processor unit memory computing environment that contains the data for which you want to calculate the message authentication code, and calculating by means of this command the specified message authentication codes, and the specified command is mapped to a field in a processor register, determining the code value calculation functions message authentication codes based on which the processor when executing the specified command defines one of the encryption methods that will be applied to calculate the authentication code, and if the specified field for more values of the function code, the processor performs a query operation that calls the save parameters block status word having many categories, each of which corresponds to a specific function, and if a specific discharge status word has the first binary value, this bit corresponds to the value of the function code corresponding to the set in the process the e function, and if a certain category of the status word has the second binary value, this bit corresponds to the value of the function code corresponding to the not installed in the CPU of the function.

Proposed in the invention method allows via calculation of the authentication code to execute the save operation to save the parameters block status word, in contrast to known systems command processor, for providing this opportunity commands load or move.

Particularly preferred embodiments of the invention will become apparent to a person skilled from the following detailed description of the invention accompanied by drawings on which is shown:

figure 1 - calculation of message authentication codes" (CMAS) in the command format RRE,

figure 2 - table, which shows the function codes for commands CMAS shown in figure 1,

figure 3 - assigning team CMAS shown in figure 1, the values in the General purpose register (GR),

figure 4 - the symbol that represents a bitwise exclusive OR operation (XOR),

figure 5 is a symbol for encryption and decryption on the data encryption algorithm (DEA),

figure 6 - the format of parameter block for CMAS-query

7 format of parameter block for KMAC-DEA,

on Fig - operation KMAC-DEA,

figure 9 fo the Mat parameter block for KMAC-TDEA-128,

figure 10 is an operation KMAC-TDEA-128,

figure 11 - the format of parameter block for KMAC-TDEA-192,

on Fig - operation KMAC-TDEA-192,

on Fig - table showing the priority command CMAS,

on Fig - cryptographic coprocessor, and

on Fig - generic preferred variant implementation of the computer's memory that stores command corresponding to a preferred variant of the invention, and data, as well as the mechanism fetch, decode and execute such commands or computing system, which uses the commands of the architecture, or in emulation of such commands.

Below is considered first command "compute message authentication codes" (CMAS), then the preferred computing system, and alternatively, computing system that can perform such commands emulates another computing system.

Command "compute message authentication codes" (CMAS)

Figure 1 shows the command "compute message authentication codes" (CMAS) RRE instruction format.

Executes the function specified by the function code in register 0 General purpose. Bits 16-23 team and field R1 are ignored.

The bits 57-63 register 0 General purpose contains function code. Figure 2 shows the assigned function codes. All other function codes are free (not assigned) Discharge 56 General register must be zero, otherwise, lies in the exceptional situation when the violation of the specified terms. All the other bits of register 0 General purpose ignored.

Register 1 General purpose contains the logical address of the leftmost byte of the parameter block that is stored in memory. In 24-bit addressing, the contents of bits 40-63 of the register 1 General purpose is to address, and the contents of bits 0-39 ignored. Mode 31-bit addressing, the contents of bits 33-63 of the register 1 General purpose is to address, and the contents of bits 0-32 ignored.

Mode 64-bit addressing, the contents of bits 0-63 of the register 1 General purpose is the address.

Figure 2 shows the function codes command "compute message authentication codes".

All other function codes are free (not assigned). The query function is a means of indicating the availability of other functions. For the query function, the contents of registers R2 and R2+1 General purpose is ignored.

For all other functions the second operand is treated in accordance with how it is specified by the function code using the initial values of the chain in the parameter block, and the result replaces the value chain. When performing this operation also uses a cryptographic key in the parameter block. The operation is carried out until Costigan the I location of the end of the second operand or the processing of the number of bytes, given the Central processing unit (CPU), whichever occurs sooner. The result indicate in code terms.

Field R2 designates an even-odd pair of General purpose registers and must match the case with an even number, otherwise it is determined by the exceptional situation in violation of the specified conditions.

The location of the leftmost byte of the second operand specifies the contents of register R2 General purpose. The number of bytes in the location of the second operand is set in the register R2+1 General purpose.

When performing the address in register R2 General purpose increases with the number of processed bytes from the second operand, and the length in register R2+1 General purpose reduced by the same number of bytes. The form and update the address and its length depends on the addressing mode.

In 24-bit addressing, the contents of bits 40-63 of the register R2 General purpose is the address of the second operand, and is ignored; bits 40-63 updated addresses replace the corresponding bits in register R_ General purpose transfers discharge 40 updated address are ignored, and the contents of bits 32-39 register R_ General purpose is set to zero. Mode 31-bit addressing, the contents of bits 33-63 of the register R_ General purpose address is in the showing of the operand, and the contents of bits 0-32 ignored; bits 33-63 updated addresses replace the corresponding bits in register R_ General purpose transfers discharge 33 updated address are ignored, and the contents of the discharge 32 register R_ General purpose is set to zero. Mode 64-bit addressing, the contents of bits 0-63 of the register R_ General purpose is the address of the second operand; places 0-63 updated address replaces the contents of register R_ General purpose, and transfers the bit 0 is ignored.

In two modes : 24-bit and 31-bit addressing, the contents of bits 32-63 of the register R2+1 General purpose is a 32-bit binary integer unsigned number that specifies the number of bytes in the second operand, and the updated value replaces the contents of bits 32-63 of the register R2+1 General purpose. Mode 64-bit addressing, the contents of bits 0-63 of the register R2+1 General purpose forms a 64-bit binary integer unsigned number that specifies the number of bytes in the second operand, and the updated value replaces the contents of register R2+1 General purpose.

In modes 24-bit and 31-bit addressing, the contents of bits 0-31 of register R2 and R2+1 General purpose always remains the same.

Figure 3 shows the contents of the above-described General-purpose registers.

the mode addressing using register access (AR) registers access 1 and R2 specify the address space, containing, respectively, the parameter block and the second operand.

The result is similar to the result of processing, starting from the left end of the second operand, and continue to the right block by block. The operation ends when you have processed all the original bytes in the second operand (which is referred to as the normal end) or when processed the specified CPU number of blocks, which is less than the length of the second operand (which is referred to as partial completion). The specified CPU number of blocks depends on the model and may be different each time you run the command. As a rule, the specified CPU number of blocks is not equal to zero. In some emergency situations such number may be zero and can be installed code condition 3 without moving forward (loop). However, the CPU provides protection from the endless repetition in this case the loops.

If the field value chain overlaps any portion of the second operand, the result obtained in the field of value chain is unpredictable.

Normal termination occurs when processed the number of bytes in the second operand, which is specified in the register R2+1 General purpose.

If the operation has been due to the normal completion code is set terms 0 and the value in register R2+1 is zero. If the operation has been due partly what about the finish, code set conditions 3, and the resulting value in the register R2+1 is not zero.

If the length of the second operand is initially zero, the access to the second operand, and the parameter block is not performed, the registers R2 and R2+1 General purpose does not change and code set conditions 0.

From the point of view of the other CPU and channel programs references to the parameter block and stored in the memory operands can be links, multiple access, access to such cells in the memory does not have to be carried out simultaneously with the access to the parameter block, and the sequence of these accesses or links are not defined.

On exceptional situations in access (exceptions access) can be reported in relation to the larger part of the second operand, than the part to be processed in one operation command; however, exceptions to access are not recognized in relation to locations outside the length of the second operand, and locations at a distance of more than 4 KB from the current workpiece location.

The symbols used in the description of functions

In the further description of the functions the calculation of the message authentication codes are used the symbols shown in figure 4 and 5. For functions that involve data encryption algorithm DEA (from the English. "Data Encryption Algorithm"), the category of even the spine of the key DEA in each byte of the key DEA ignored and the operation continues in the normal mode, regardless of the parity of the key DEA.

In more detail, the data encryption algorithm described in the standard Data Encryption Algorithm, ANSI X3.92.1981, American National Standard for Information Systems (American national standard for information systems).

CMAS request (function code 0)

The location of the operands and addresses used by this command correspond shown in figure 3. Figure 6 shows the format of the parameter block used for the function of CMAS request.

In the parameter block is stored 128-bit status word. The bits 0-127 of this field correspond to the codes functions respectively 0-127 team CMAS. If the bit is one, the corresponding function is set; otherwise, the feature is not installed.

Upon completion functions CMAS request code applies conditions 0; code conditions 3 to this function is not applicable.

KMAC-DEA (function code 1)

The location of the operands and addresses used by this command correspond shown in figure 3.

7 shows the format of the parameter block used for the function KMAC-DEA.

Message authentication code for an 8-byte message block (M1, M2...Mn) in operand 2 is calculated using the algorithm of DEA using a 64-bit cryptographic key and a 64-bit value chain in the parameter block.

Code authentication the message, also called output value chains (OCV from English. "Output Chaining Value"), save in field value chain block parameters. Operation KMAC-DEA shown in Fig.

KMAC-TDEA-128 (function code 2)

The location of the operands and addresses used by this command correspond shown in figure 3.

Figure 9 shows the format of the parameter block used for the function KMAC-TDEA-128.

Message authentication code for an 8-byte message block (M1, M2...Mn) in operand 2 is calculated using the TDEA algorithm using two 64-bit cryptographic key and a 64-bit value chain in the parameter block.

Message authentication code, which is also called the output value chains (OCV), remain in the field of value chain block parameters. Operation KMAC-TDEA-128 shown in figure 10.

KMAC-TDEA-192 (function code 3)

The location of the operands and addresses used by this command correspond shown in figure 3.

Figure 11 shows the format of the parameter block used for the function KM-TDEA-192.

Message authentication code for an 8-byte message block (M1, M2...Mn) in operand 2 is calculated using the TDEA algorithm with three 64-bit cryptographic key and a 64-bit value chain in the parameter block.

Message authentication code, which is also called the output value chains is key (OCV), retain in field value chain block parameters. Operation KMAC-TDEA-192 shown in Fig.

Special conditions for CMAS

When any of the following conditions is determined by the exceptional situation when the violation of the specified terms and not taken any steps:

1. The discharge 56 register 0 General purpose is not equal to zero.

2. For bits 57-63 register 0 General purpose is not defined or is not selected function code.

3. Field R denotes the case with an odd number or register 0 General purpose.

4. The length of the second operand is not a multiple of the block size of the data specified function (to determine the size of the data blocks for functions "calculation of message authentication codes, see Fig.7-54 on page 7-92).

Get code conditions:

0 normal termination

1 --

2 --

3 is a partial end

Software exceptions:

• access (fetch, operand 2 and the length of the message in bits; sampling and preservation, value chain);

• when the operation is performed (unless the auxiliary program a privacy message);

• for violation of specified conditions.

Notes on programming:

1. The discharge 56 register 0 General purpose reserved for future expansion and must be set to zero.

2. If the code is installed conditions 3 address and the length of the second operand registers R2 and R2+1 General purpose accordingly, the value chain in the parameter block will usually update so that the program can easily return to the team and to continue the operation. In emergency situations the CPU protects from the endless repetition of the operations in the loop cases. Thus, whatever was installed code condition 3, the program may return to the team without loops.

3. If the length of the second operand is not initially zero and the code is installed conditions 0, the update of the registers is the same as in code condition 3; the value chain in this case is that the processing of additional operands can be carried out in the same manner as if they were part of the same chain.

4. Before processing the first part of the message, the program must specify the initial values for the field value chain. According to the ANSI standard X9.0 or H original value chain must comply with zero discharge.

Cryptographic coprocessor

In a preferred embodiment, the invention provides for the use of cryptographic coprocessor (coprocessor cryptographic support)that can be used in combination with the above commands, and to perform encrypted messages and as an adjuvant for a variety is ADAC clutch messages which can be used to grip and cryptographic application in conjunction with relevant commands.

On Fig shown cryptographic coprocessor, which is directly connected to the data path common to all internal actuators on the universal microprocessor, which has several operating conveyors. Internal bus 1 microprocessor, which is common for all other actuators, connected with a cryptographic unit 2 control, which monitors the bus command processor, which it should execute.

The cryptographic control unit serves as a cryptographic coprocessor, which is directly connected with the data path common to all internal execution units of the CPU on the universal microprocessor, providing affordable hardware (E0...En) or combinations thereof in a preferred embodiment, operating conveyors. When in register 3 teams cryptographic commands unit 2 control causes of the available hardware, the corresponding algorithm. Data through the input operand register 4, operating on the principle of service in order of arrival (FIFO-register), go through the same internal bus of the microprocessor. In the end the NII operations in the register 6 status is a flag that and the results can be read from the output FIFO register 5.

In the illustrated preferred embodiment, the invention is intended to build to turn on as many hardware machines as required by the specific implementation depending on the objectives for the system. Data transfer path in the direction of the input and output registers 7 are common to all machines.

In a preferred variant of the invention, the cryptographic functions are implemented in the hardware of the Executive device for the CPU, which results in less waiting time (delay) when the invocation and execution of cryptographic operations and increased efficiency.

By reducing the waiting time significantly expand the possibilities of universal processors in systems where often performed many cryptographic operations, especially if we are talking only about small amounts of data. This makes possible the implementation, could significantly speed up the processes associated with the implementation of a secure online transaction. The most common ways to ensure the security of online transactions involve the use of a set of three algorithms. The first algorithm is used once per session and can be implemented in hardware or p is ogramme, and the rest of the algorithms are called when each transaction during the session, while the present invention eliminates the time associated with the delay when calling external hardware, and the algorithm is executed by means of software.

On Fig shows the conceptual implementation of the preferred alternative implementation of the invention on the example of the mainframe with the above-described microprocessor, which, as proved experimentally in IBM, can be effectively used in the mass implementation of the proposed architecture for computers with the functionality of long offset, which is used by programmers, these days typically the programmers working on the language "C". Such formats of commands that are stored in a memory device can implement a native IBM z architecture or alternatively, computing machines based on other architectures. They can emulate existing and future IBM class mainframe and other IBM machines (for example, servers, series R and servers x series). They can be run using the operating system a variety of Linux-based computers, hardware, IBM, Intel, AMD, Sun Microsystems and other companies. In addition to performing such hardware z-architecture Linux can also be used in machines that use em is the transmission on the basis of Hercules, UMX, FXI or Platform Solutions, in which the execution mode in General is an emulation mode. In emulation mode perform decoding of a particular emulated team and form a standard routine for the implementation of individual commands in the form of routine or driver on the language or create a driver for a specific hardware otherwise available to specialists in the art, familiar with the description of the preferred option implementation. Different ways of implementation on the target computer emulation command format, and the architecture is developed for execution on another computer and commercially available software tools used in these purposes described in several patents, revealing software and hardware emulation, including, without limitation, patents US 5551013, US 6009261, US 5574873, US 6308255, US 6463532 and US 5790825.

In this preferred embodiment of the invention formats for superscalar team prior to the format with a long offset, form the address of the storage operand by adding a base register and a 12-bit offset unsigned or base register, index register and a 12-bit offset unsigned and new formats of commands with a long offset form the address of the storage operand is by adding a base register and a 20-bit signed offset or base register, index register and a 20-bit signed offset.

As shown in Fig, such commands are executed by the hardware processor, or by emulation of such a command set software installed on a computer with a different native instruction set.

On Fig position 501 designated memory (storage device) of the computer that stores commands and data. This computer originally stored is described in the present invention the team with a long offset. Position 502 indicated the mechanism of selecting commands from the computer memory, which can also provide the location of the selected commands in the local buffer storage device. Then the teams in the original form received in the decoder 503 command that specifies the type of the selected command. Position 504 identified the mechanism of the commands. It may include loading data into a register from memory 501, the data from a register into memory or perform any arithmetic or logical operations. The type of such operations are predefined decoder commands. In this case, are described in the present invention the team with a long offset. If a team with a long offset run in a native computer system, the process is terminated as described above. If the set command structure is Roy, contains commands with a long offset, emulates another computer, the described process will be implemented in the host computer 505 software. In this case, the above-mentioned mechanisms, as a rule, will be implemented in the form of one or more standard system routines within the emulation software. In both cases originate a call, the decoding (decoding) and the command.

In particular, commands, this architecture can be used with a computer architecture that uses existing formats of commands with a 12-bit offset unsigned used to generate the address of the storage operand, as well as the architecture, which uses additional formats of commands that provide additional discharges offset, preferably 20 digits representing increased displacement with the token used to generate the address of the storage operand. Team this architecture is a computer software that is stored in a storage device of the computer and is used for code generation, coming from the processor, which uses computer software, and contains the command code used by the compiler / emulator/interpreter stored in the storage device 501 computer, if e is ω the first part of the command code contains the operation code, specifies the operation you want to perform, and the second part assigns the operands to participate in its implementation. When using commands with a long offset, it becomes possible to directly access additional addresses.

As shown in Fig, such commands are executed by the hardware processor, or by emulating the specified command set - software running on a computer with a different native instruction set.

In accordance with the computer architecture used in a preferred embodiment of the invention, the offset field consists of two parts, with the least significant part consists of 12 bits and is denoted by DL, DL1 - for operand 1 or DL2 - for operand 2, and the most significant part consists of 8 bits and is denoted by DH, DH1 - for operand 1 or DH2 - for operand 2.

In addition, in the preferred computer architecture, the format for the command is that the code operations correspond to the digits 0 through 7 and from 40 to 47, the target register, called R1, correspond to the bits 8 through 11, the index register, called x2 correspond to the bits 12 through 15, the base register, called B2 correspond to the bits 16 through 19, the first part consisting of the two parts of the displacement, which is called DL2, correspond to the bits 20 through 31, and the second part, which is called DH2, correspond to bits 32 through 39.

In addition, the proposed computer architecture team with a long offset have such a format that the code operations correspond to the digits 0 through 7 and from 40 to 47, the target register, called R1, correspond to the bits 8 through 11, the mask value, called M3, which correspond to the bits 12 through 15, the base register, called B2 correspond to the bits 16 through 19, the first part consisting of the two parts of the displacement, which is called DL2, correspond to the bits 20 through 31, and the second part, which is called DH2, correspond to 32 bits 39.

As shown above, the preferred computer architecture with a long offset has such a command format that code operations correspond to the digits 0 through 7 and from 40 to 47, the immediate value, called I2 correspond to the bits 8 through 15, the base register, called B2 correspond to the bits 16 through 19, the first part consisting of the two parts of the displacement, the which is called DL1, correspond to the bits 20 through 31, and the second part, which is called DH1, correspond to bits 32 through 39.

Proposed invention is a computer architecture with a long offset is effective when working with new created teams that applied only command format with the new 20-bit offset unsigned.

In a special embodiment of the proposed invention in computer architecture uses existing commands, formats which have only a 12-bit offset unsigned and in new formats are defined as having an existing 12-bit offset unsigned, if the 8 high-order bits in the offset field of the DH are zero bits, or as having a 20-bit signed offset, if the 8 high-order bits in the offset field of the DH are not zero digits.

Another form of the invention is a device for computing message authentication codes for the data stored in the memory of the computing environment with tools for the job via memory unit for which you want to calculate the authentication code, and calculation tools by means of this command, the authentication code to the memory unit.

1. The method of calculating the message authentication codes for the data stored in the memory of the computing environment, using the processor, containing a memory in which is the parameter block for executing commands of the processor, including

job through command processor unit memory computing environment that contains the data for which you want to calculate the message authentication code, and

calculation by means of this command the specified message authentication codes, and the specified command is mapped to a field in a processor register, determining the code value calculation functions message authentication codes based on which the processor when executing the specified command defines one of the encryption methods that will be applied to calculate the authentication code, and if the specified field for more values of the function code, the processor performs a query operation that calls the save parameter block specified unit pasyati status words with multiple categories, each of which corresponds to a specific function, and if a specific discharge status word has the first binary value, this the category corresponds to the value of the function code corresponding to the installed processor functions, and if a specific discharge status word has the second binary value, this bit corresponds to the value of the function code corresponding to the not installed in the rocessor functions.

2. The method according to claim 1, in which the specified command when it is executed by the CPU stores the calculated authentication code in the first operand.

3. The method according to claim 1, in which encryption methods corresponding to the values of the function code, include a cryptographic operation on a 64-bit key algorithm DEA cryptographic operation with two 64-bit key algorithm Triple DEA cryptographic operation with three 64-bit keys according to the algorithm Triple TDEA.

4. The method according to claim 1, wherein to calculate the authentication code to create a cryptographic key associated with the memory unit.

5. The method according to claim 1, in which the command is executed by the processing unit that emulates the architecture team and the architecture team is different from the architecture of the processing unit.

6. The method according to claim 1, in which a lot of memory units and the calculation of the message authentication codes to perform this set of memory units.

7. The method according to claim 6, in which the message authentication code is calculated by forming chaining blocks of the message contained in the units memory.

8. The method according to claim 1, in which the specified command is implemented in hardware and/or software.

9. The method according to claim 1, wherein the setting unit memory includes providing information about the location is ogenyi data structures, associated with the specified unit of memory.

10. The media data stored therein a computer program that contains commands that are intended for all stages of the method according to any one of claims 1 to 9, when executing a computer program in a computer system.



 

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The invention relates to the field of computer systems and may be used to execute processor commands floating point and Packed data

FIELD: engineering of data processing systems, which realize operations of type "one command stream and multiple data streams".

SUBSTANCE: system is disclosed with command (ADD8TO16), which decompresses non-adjacent parts of data word with utilization of signed or zero expansion and combines them by means of arithmetic operation "one command stream, multiple data streams", such as adding, performed in response to one and the same command. Command is especially useful for utilization in systems having a data channel, containing a shifting circuit before the arithmetic circuit.

EFFECT: possible use for existing processing resources in data processing system in a more efficient way.

3 cl, 5 dwg

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