Hybrid microprocessor

FIELD: information technology.

SUBSTANCE: present invention relates to computer engineering and can be used in signal processing systems. The device contains an instruction buffer, memory control unit, second level cache memory, integral arithmetic-logic unit (ALU), floating point arithmetic unit and a system controller.

EFFECT: more functional capabilities of the device due to processing signals and images when working with floating point arithmetic.

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The invention relates to computer technology and may find application in systems, signal processing and other information, where high performance when working with floating point arithmetic.

The prototype device may be any processor with a RISC architecture, but the closest is the microprocessor RM7065A company PMC-Sierra, buffer containing instructions, a memory management unit, the cache memory of the second level, integer arithmetical-logical unit (ALU), the block floating point arithmetic and the bus controller (see, for example. Short Form Data Sheet PMC-2011599 RM7065A 64-Bit MIPS RISC Microprocessor with Integrated L2 Cache, http://www.pmc-sierra.com).

The described prototype can execute up to two instructions per cycle, but does not effectively solve the problems of signal processing and image when working with floating point arithmetic.

The objective of the invention is the creation of the universal high-performance microprocessor microprocessor hybrid, allowing the processing of signals and images when working with floating point arithmetic.

This task is performed by the microprocessor hybrid containing buffer instructions, a memory management unit, the cache memory of the second level, integer arithmetical-logical unit (ALU), the block floating point arithmetic and the controller, and the buffer instructions is executed with the ability to predict transitions for loss compensation when performing the transition team and the opportunity to deploy to execute up to four instructions in the mode of signal processing hardware control the possibility of simultaneous execution of instructions in the dynamic reorder, has one input and five outputs and associated with a memory management unit, the integer ALU and real arithmetic unit, a memory management unit includes a cache memory instructions of the first level and the cache data of the first level, ten inputs and seven outputs and associated with all blocks of a microprocessor, a cache memory of the second level is made in the form of internal memory for reducing losses in exchange with external memory has eight inputs and six outputs, and is divided into 16 separate memory banks with extra tires, connecting it to the control unit memory block floating point arithmetic and the system controller, designed to work with memory banks individually and download data both double block floating point arithmetic, integer ALU is configured to execute two integer instructions per cycle, and calculating the addresses to 128-bit load/store, has six inputs and two outputs and is associated with a buffer of instructions, a memory management unit and block floating point arithmetic real arithmetic unit configured to perform two dual operations of multiplication, addition and subtraction of real numbers single precision per cycle and operations cleverly is possible and the addition of double-precision numbers, has seven inputs and four outputs and is associated with a buffer of instructions with a memory management unit, the integer ALU and cache memory of the second level, the controller is implemented in an embedded system controller has two inputs and three outputs and associated with a memory management unit and cache memory of the second level.

This task is also the fact that the connection block floating point arithmetic with the cache memory of the second level is performed on four additional 128-bit data bus, and the connection cache memory of the second level with the system controller for two additional 64-bit data bus.

This task is also the fact that the buffer contains instructions buffer transition control block buffers, the execution buffer block fetch/decode commands, the block prediction of transition, the unit of analysis dependencies, counter, counter move, the block select thread and two multiplexer, and the buffer transfer completed with one input and one output and is connected with a memory management unit and through the multiplexer with the execution buffer control block buffers are made with four outputs and two inputs and is associated with a block of branch prediction, the block fetch/decode commands, the unit of analysis dependencies, register counter programs that control the multiplexer buffer execution the execution buffer is made with one input and one output and is connected with the block fetch/decode commands, block fetch/decode the commands executed with two inputs and two outputs and is associated with the execution buffer block dependency analysis, the block select thread of execution, the control unit buffers and block prediction of the transition block to predict the transition is made with three inputs and three outputs and is connected with the control unit buffers, block fetch/decode commands, counter, counter transition and multiplexer associated with a memory management unit, a unit of the dependency analysis is performed with a single input and two outputs and is connected with the control unit buffers, block fetch/decode commands and unit selection thread of execution, the program counter is made with one input and one output and is connected with the control unit buffers, block prediction of transition and the multiplexer associated with a memory management unit, the counter move is made with one input and one output and is connected with the block prediction of transition and the multiplexer associated with a memory management unit, the block select thread is made with two inputs and four outputs and is connected with the block fetch/decode commands, the unit of analysis dependencies with a memory management unit, the integer ALU and block floating point arithmetic.

This task is also the fact that the cache memory of the second level which contains four input multiplexer, the control unit cache memory of the second level, the unit registers of the RAP and vector mode, four groups of memories 4×16 KB and six output buffers, each of the four input multiplexers made with six inputs and one output and is connected with the system controller, a memory management unit and block floating point arithmetic, with the control unit, the cache memory of the second level and the corresponding group of memories 4×16 KB, the control unit cache memory of the second level is made with five inputs and three outputs and is connected to the input multiplexers, memories 4×16 KB, output buffers and registers unit RAP and vector mode, the unit registers of the RAP and vector mode is performed with a single input and two outputs and is connected with a memory management unit, with control unit, the cache memory of the second level and output buffers, each of the four groups of memories 4×16 KB performed with two inputs and one output and is connected to the input multiplexers, the control unit cache memory of the second level and output buffers, six output buffers, each of which is made with five inputs and one output and is connected with the system controller, a memory management unit, unit real arithmetic, with a memory management unit and groups of memories 4×16 KB.

This task is also the fact that the unit is existenoe arithmetic, contains two asymmetric schemes of the input interface, the decoder processor instructions, two twin-block multiplication of single-precision, block multiplication of double-precision, two twin-unit addition of single-precision, two twin block subtract single-precision, block addition of double-precision, two unbalanced circuits output interface, two register file, two unbalanced circuits input interface, one of which is made with five inputs and nine outputs, and the other with three inputs and five outputs, and associated with a memory management unit, the integer ALU and cache memory of the second level decoder instructions microprocessor, two double blocks multiplication of single-precision, block multiplication of double-precision, two double blocks the addition of single-precision, two double blocks subtract single-precision, block addition of double-precision and two register files, the decoder microprocessor instructions executed with three inputs and twelve outputs and is associated with a buffer of instructions, the two input circuits of interface, two double blocks multiplication of single-precision, block multiplication of double-precision, two double blocks the addition of single-precision, two double blocks subtract single-precision, unit double addition is echnosti and two circuits of the output interface, two twin-block multiplication of single-precision, each of which has three inputs and one output and is connected with the input circuits of interface, the decoder microprocessor instructions, schemes output interface dual block addition of single-precision, double block subtract single-precision, block multiplication of double-precision made with three inputs and one output and is connected with the input circuits of interface, the decoder microprocessor instructions, schemes output interface block addition doubles, two twin-unit addition of single-precision, each of which has four inputs and one output and is connected with the input circuits of interface, the decoder microprocessor instructions, schemes output interface, dual blocks the multiplication of single-precision, two twin block subtract single-precision, each of which has four inputs and one output and is connected with the input circuits of interface, the decoder microprocessor instructions, schemes output interface, dual blocks the multiplication of single-precision, block addition of double-precision made with four inputs and one output and is connected with the input circuits of interface, the decoder processor instructions, schemes output interface block multiplication of double-precision and, two unbalanced circuits output interface, one of which is made with six inputs and four outputs, and the other with four inputs and two outputs and are connected respectively with a memory management unit, the integer ALU and cache memory of the second level decoder microprocessor instructions, two double blocks multiplication of single-precision, block multiplication of double-precision, two double blocks the addition of single-precision, two double blocks subtract single-precision, block addition of double-precision and two register files, two register files, each of which is made with two inputs and one output and is associated with the schema of the input interface and output interface circuits.

Figure 1 presents the block diagram of the microprocessor hybrid.

Figure 2 - block diagram of the buffer of instructions.

Figure 3 - block diagram of the cache memory of the second level.

Figure 4 - block diagram block floating point arithmetic.

The microprocessor hybrid (figure 1) consists of a buffer of instructions 1, output 2 which lines of inquiry and addresses associated with the input 3 of a memory management unit 4, input 5 - input instruction associated with the output 6 of a memory management unit 4. The outputs 7, 8 and 9, and a memory management unit 4 requests and addresses, data, instructions, and save operations - related inputs 10, 11 and 12, the cache memory of the second in the anti-shudder performance 13. The output 14 of a memory management unit 4 - data save - connected to the input 15 of the cache memory of the second level 13, and outputs 16, 17 - boot data cache instructions and data of the first level and an 18 - output mode internal memory - cache memory of the second level 13 are connected to the inputs 19, 20 and 21 of a memory management unit 4. The output buffer 22 instructions 1 - integer instruction is connected to the input 23 of the integer ALU 24, exit 25 - integer instruction or instruction load/store is connected to the input 26 of the integer ALU 24, entry 27 of a memory management unit 4 and the input 28 of the real arithmetic unit 29, the output buffer 30 instructions 1 - extended instruction load/store is connected to the input 31 of the integer ALU 24, the input 32 of a memory management unit 4 and the input 33 of real arithmetic unit 29, the output of buffer 34 instructions 1 instruction floating point arithmetic instruction or extended floating point arithmetic - related the entrance 35 of the integer ALU 24 and the inlet 36 of real arithmetic unit 29. The output 37 of the control unit memory 4 is connected to the input 38 of the integer ALU 24, and the output 39 of the integer ALU 24 is connected to the input 40 of a memory management unit 4 - line interaction integer ALU and a memory management unit. The output 41 of the integer ALU 24 is connected to the input 42 of real arithmetic unit 29, and the output 43 of the block of material is Oh arithmetic 29 is connected to the input 44 of the integer ALU 24 - lines of communication the integer ALU and block floating point arithmetic. The output 45 of a memory management unit 4 - the output is connected to the input 46 of the system controller 47, the output 48 of the system controller 47 - line monitoring of coherence is associated with the input 49 of a memory management unit 4, the output 50 of the system controller 47 is input is connected to the input 51 of the control memory 4 and the inlet 52 of the cache memory of the second level 13. The output 53 of the control unit memory 4 is connected to the input 54 of real arithmetic unit 29, and the output 55 of real arithmetic unit 29 is connected to the input 56 of a memory management unit 4 - line exchange of data of a memory management unit and block floating point arithmetic. The outputs 57 and 58 of the cache memory of the second level 13 are connected to the inputs 59 and 60 of the real arithmetic unit 29, and outputs 61 and 62 of real arithmetic unit 29 are connected to the inputs 63 and 64 of the cache memory of the second level 13 - additional 128-bit data bus. The output 65 of the cache memory of the second level 13 is connected to the input 66 of the system controller 47, and the output 67 of the system controller 47 is connected to the input 68 of the cache memory of the second level 13 - channel direct memory access.

As a memory management unit 4 can use any block of memory management microprocessor with RISC architecture, containing a cache memory for data and instructions of the first level, for example, the control unit memory is MIPS similar microprocessor type prototype or any other or SPARC V8 similar to the processor. As integer ALU 24 can be any integer ALU of the microprocessor RISC architecture enables to execute two integer commands per cycle, the processing address and forwarding. As the system controller can use any of the existing system controller, allowing you to connect additional data channels and compatible with the local bus with the control unit memory.

Buffer instructions 1 consists of a control unit buffers 69, entry 70 which is connected with the output 71 of the block to predict the transition 72 exit 73 - input 74 of the block to predict the transition 72, exit 75 - with the control input of the multiplexer 76 and 77, exit 81 - input 82 of the counter 83, entry 84 - exit 85 block dependency analysis 86; buffer transition 87, entry 88 which is connected to the input 2 buffer instructions 1, exit 89 - input multiplexer 90 77; multiplexer 77, the control input 76 which is connected with the output 75 of the block control buffers 69, entry 90 to the output 89 of the buffer transition 87, entry 91 - input 2 buffer instruction 11, the output 92 from the inlet 93 of the buffer run 94; buffer run 94, entry 93 which is connected with the output of multiplexer 92 77, exit 95 - input 96 of the block fetch/decode 80; block to predict the transition 72, the output 71 of which is connected to the input 70 of the control unit is Fermi 69, the input 74 from the output 73 of the control unit buffers 69, exit 97 - with the control input of multiplexer 98 99, exit 102 from the inlet 103 of the counter transition 104, entry 105 with the output 106 of the counter 83, input 100 - output unit 101 fetch/decode 80; block fetch/decode 80, entry 96 which is connected with the output 95 of the buffer run 94, entry 79 - exit 78 of the control unit buffers 69, exit 101 to the input 100 of the block to predict the transition 72, exit 107 - inputs 108 block dependency analysis 86 and 109 of the block select thread 110; a multiplexer 99, the control input 98 which is connected with the output 97 of the block to predict the transition 72, the output 111 from the output 5 of the buffer instructions 1, the input 112 from the output 106 of the counter 83, entry 113 - the output of counter 114 transition 104; counter 83, entry 82 which is connected with the output 81 of the control unit buffers 69, exit 106 - input multiplexer 112 99; unit of analysis dependencies 86, exit 85 which is connected to the input 84 of the control unit buffers 69, entry 108 - with the output 107 of the block fetch/decode 80, exit 115 - input 116 of the block select thread 110; block selection thread 110, the output 116 which is connected with the output 115 of the unit of analysis dependencies 86, entry 109 - the output 107 of the block fetch/decode 80, exit 117 from the output buffer 22 of the instructions 1, the output 118 from the output 25 of the buffer instructions 1, the output 119 from the output buffer 30 instructions is 1, the output 120 from the output buffer 34 instructions 1.

As the control unit buffers 69 may be used by the control unit buffers are FIFO (first input first output stage). The buffer passage 87 and the execution buffer 94 - registers for storage of 4 32-bit instructions. The block prediction of transition 72 - standard unit branch prediction RISC processor with the prediction of transition, managing the billing request on the address bus and generates the signals for setting the predicted request and confirm or cancel the predicted transition. Block fetch/decode 80 - the standard unit for decoding instructions of the RISC microprocessor architecture (for example, the block decoding MIPS similar microprocessor type prototype or any other), decoding the received command. Counter transition 104 is a register that stores a value of the target address of the predicted transition of the transition. The counter 83 is the register that stores the current value of the counter. The unit of analysis dependencies 86 - the standard unit of dependency analysis is selected for execution of instructions of the microprocessor RISC architecture, performing 2 teams per cycle (for example, the block decoding microprocessor type prototype or any other). The block select thread 110 - standard unit with RISC microprocessor architecture with 4 threads to be executed is (for example, block the issuing of instructions of the microprocessor type prototype)that distributes selected and decoded instruction execution flow.

The cache memory of the second level 13 consists of four input multiplexers 121, 122, 123, and 124; four groups of memories 125, 126, 127 and 128 capacity of 4×16 KB each; six output buffers 129, 130, 131, 132, 133 and 134; unit registers 135 that stores operation parameters of the block cache second-level modes of vector and direct memory access (RAP); the control unit cache memory of the second level 136.

The entrance 52 of the block 13 - input is connected to the inputs 137, 138, 139 and 140 of the input multiplexers 121, 122, 123 and 124, respectively; the input 68 of the block 13 - input is connected to the inputs 141, 142, 142 and 144 of the input multiplexers 121, 122, 123 and 124, respectively; entrance 15 block 13 - input is connected to the inputs 145, 146, 147 and 148 of the input multiplexers 121, 122, 123 and 124, respectively; the input 63 of the block 13 - input is connected to the inputs 149, 150, 151 and 152 of the input multiplexers 121, 122, 123 and 124, respectively; the input 64 of the block 13 - input is connected to the inputs 153, 154, 155 and 156 of the input multiplexers 121, 122, 123 and 124, respectively.

The input 10 of block 13 of the address lines is connected to the input 157 of the control unit, the cache memory of the second level 136; 11 block 13 - the address lines is connected to the input 158 of the control unit, the cache memory of the second level 136; input 12, block 13 - line addresses associated with the I the house 159 control unit cache memory of the second level 136.

The output 160 of the input multiplexer 121 is connected by a data line to the input 161 of the group of memory 125. The output 162 of the input multiplexer 122 is connected by a data line to the input 163 of the group of memories 126. The output 164 of the input multiplexer 123 is connected by a data line to the input 165 of the group of memory 127. The output 166 of the input multiplexer 124 is connected by a data line to the input of 167 group memory 128.

The output 168 of the control unit, the cache memory of the second level 136 is connected with the control inputs 169, 170, 171 and 172 of the input multiplexers 121, 122, 123 and 124, respectively. Output 173 is connected with the input address and control signals 174, 175, 176 and 177 of groups of memories 125, 126, 127 and 128, respectively. The output 178 of the group of memory 125 is connected by a data line to the input 179, 180, 181, 182, 183 and 184 of the output buffers 129, 130, 131, 132, 133 and 134, respectively. The output 185 of the group of memories 126 is connected by a data line to the input 186, 187, 188, 189, 190 and 191 of the output buffers 129, 130, 131, 132, 133 and 134, respectively. The output 192 of the group of memory 127 is connected by a data line to the input 193, 194, 195, 196, 197 and 198 of the output buffers 129, 130, 131, 132, 133 and 134, respectively. The output 199 of the group of memories 128 is connected by a data line to the inputs 200, 201, 202, 203, 204 and 205 of the output buffers 129, 130, 131, 132, 133 and 134, respectively. The output 206 of the control unit, the cache memory of the second level 136 is connected with the control inputs 207, 208, 209, 210, 211 and 212 of the output buffers 129, 130, 131, 132, 133 and 134, respectively.

The output of the output buffer 213 129 - line data - SV is associated with the output 65 of the block 13; the output 214 of the output buffer 130 is a data line is connected with the output 18 of the block 13; the output 215 of the output buffer 131 - data line is connected with the output 16 of the block 13; the output 216 of the output buffer 132 - line data associated with the output 17 of the block 13; the output 217 of the output buffer 133 - line data associated with the output 57 of the block 13; the output 218 of the output buffer 134 - line data associated with the output 58 of the block 13.

The output 219 of the register unit 135 is connected by a data line to the input 220 of the control unit, the cache memory of the second level 136. The output 221 of the register unit 135 is connected by a data line to the input 222 of the control unit, the cache memory of the second level 136.

The blocks 121, 122, 123 and 124 are standard 128-bit multiplexers 4-in-1. Blocks 125, 126, 127 and 128 are standard 128-bit memory blocks. Blocks 129, 130, 131, 132, 133 and 134 are standard 128-bit multiplexers 4-in-1 combined with output buffers. Block 135 is a set of registers. Block 136 is a standard memory controller that generates the address signals, the signals enable input multiplexers and output buffers.

The real arithmetic unit 29 consists of blocks, described below. The data from the external device are received at the inputs 223, 224 and 225 of the input interface circuit 226 with inputs 42, 54 and 59 of the block 29, respectively. Data outputs 227 and 228 unit 226 receives the input operands 22 and 230 dual block multiplication of single-precision 231. Data outputs 232 and 233 are received respectively on the input operands 234 and 235 of block multiplication of double-precision 236. Data outputs 237 and 238 unit 226 receives respectively on the input operands 239 and 240 dual block addition of single-precision and respectively to the inputs of the operands 242 and 243 dual block subtract single-precision 244. Data outputs 245 and 246 unit 226 receives the input operands 247 and 248 of the unit of addition of double-precision 249 respectively. Output 250 block 226, the data arrives at the input 251 of the register file 252, the output of 253 which data arrive at the input 254 block 226. Input 255 unit 226 receives a set of control signals output 256 decoder processor instructions 257. The inputs 258, 259 and 260 unit 257 receives the instruction processor with inputs 28, 33 and 36 of the block 29. Sets of control signals fed to the input of block 261 231 output block 262 257 and to the input of 263 block 237 with exit 264 block 257. Output 265 unit 257 control signals fed to the input of 266 circuit input interface 267, and output block 268 257 - input 269 dual block multiplication of single-precision 270. Input 271 unit 270 to exit 53 unit 54 receives data from external devices. With outputs 272 and 273 operands arrive at the inputs 274 and 275 unit 270, respectively. Operands with outputs 276 and 277 block 267, respectively, are received at the inputs 278 and 279 dual block addition on the single is the second accuracy 280, as well as the inputs 281 and 282 dual block subtract single-precision. Output block 284 267 data fed to the input of 285 register file 286, exit 287 which data arrive at the input of block 288 267. Output 289 block 231 double multiplication of single-precision is input to 290 unit 241, entry 291 block 244 and input 292 of the output interface circuit 293. Output 294 block 236 the result of the multiplication of double-precision is input 295 block 249 and to the input of block 296 293. Output 297 unit 270 double multiplication of single-precision is input 298 block 280, entry 299 block 283 and to the input 300 of the schema of the input interface 301. Control signals for unit 241 receives at its input 302 from the output 303 of block 257. The control signals for the unit 244 receives at its input 304 from the output 305 of the block 257. The control signals for the block 249 receives at its input 306 output 307 block 257. Output block 308 257 control signals fed to the input block 309 283, and output block 310 257 - input 311 of the block 280. Output 312 of block 241 double addition of single-precision fed to the input of block 313 293. Output 314 block 244 double subtraction of single-precision is fed to the input 315 of block 293. Output block 316 249 the result of the addition of double precision is fed to the input block 317 293. Output 318 block 280 double addition of single-precision is fed to the input 319 BC the AC 301. Output block 320 283 double subtraction of single-precision is fed to the input 321 of the block 301. The control signals fed to the input of block 322 293 to exit 323 block 257. Output block 324 257 the control signals fed to the input of block 325 301. Data outputs 326, 325 and 328 block 293 are fed to the inputs of the external blocks, respectively, by the outputs 55, 43, and 61 of the block 29. Output 329 of block 293, the data arrives at the input 330 of the block 252. Output 331 unit 301, the data arrives at the input of the external units through the output 62 of the block 29. Output data 332 is fed to the input block 333 286.

Blocks 226, 267, 293 and 301 consists of a standard 64-bit multiplexers. Blocks 231 and 270 consist of two standard 32-bit multiplication of real numbers single precision. Block 236 is a standard 64-bit device multiplication of real numbers in double precision. Each of the blocks 241, 244, 280 and 283 consists of two standard 32-bit summation of real numbers single precision. Unit 249 is a standard 64-bit device summation of real numbers in double precision. Architecture blocks 231, 236, 241, 244, 249, 270, 280, 283 meets the requirements of IEEE-754. Block 257 is a standard combinational circuit decoding of instructions for the processor. Register files 252 and 286 is made on the basis of the standard multiport memory.

Boo is ur instructions 1 controls the query instructions, provides temporary storage in the internal buffers, sends commands for execution and processes the command transitions. Buffer instructions 1 sends the request with the address of the control memory 4 via communication lines (output 2 input 3). The control unit memory 4 is the connecting link between the blocks 1, 13, 24 and 47, upon receiving a request from block 1, it checks the presence of instructions in its own cache memory instructions of the first level, in the absence of addresses in the cache memory of the second level 13, and in the absence of it there is in the system controller 47. Instructions from the system controller 47 via communication (exit 50 - input 51 and 52) are in the cache memory of the second level 13 and a memory management unit 4, then where in the buffer instructions 1. Buffer instructions 1, analyzing the received instructions for simultaneous execution, puts them one by one, in pairs or fours in the integer ALU 24 lines (output 22 input 23), integer ALU 24, a memory management unit 4 and the real arithmetic unit 29 via communication lines (exit 25 - inputs 26, 27 and 28), (30 outputs input 31, 32 and 33), integer ALU 24 and the real arithmetic unit 29 via communication lines and (exit 34 inputs 35 and 36). Integer ALU performs simultaneously or two integer instructions, or an integer instruction and calculates the address of an integer or real for the power load/save simultaneously calculates the address for the 128-bit load/store command signal processing. The calculated address lines (exit 40 input 39) enter in block 4. Service information or data the command data are transmitted on the lines (exit 41 input 42) in block 29. The real arithmetic unit 29, designed to perform arithmetic operations on floating-point numbers, contains blocks allocated to single-precision, supplemented by teams of signal processing. The real arithmetic unit 29 executes up to two instructions - arithmetic and load/store - tact, receiving them through the lines of: (exit 34 - entrance 36) arithmetic instructions (exit 25 - entry 28) instruction floating point load/store, and (exit 30 - entry 33) instruction 128-bit load/store command signal processing. The real arithmetic unit 29 is connected 64-bit data bus used for normal load/store, with a memory management unit 4, the communication line (exit 53 - input 54) are used to transmit data in a memory management unit 4, and the lines (exit 55 - input 56) data comes in real arithmetic unit 29. Four 128-bit data bus (exit 57 - input 59), (exit 58 - input 60), (exit 61 - input 63) and (exit 62 - input 64) are connected by the real arithmetic unit 29 with the cache memory of the second level is 13. The cache memory of the second level 13 is used as a cache memory in a normal mode or an internal data memory mode signal processing. The cache memory of the second level 13 is divided into 16 separate memory banks, arranged in four groups of memories, which can work independently. Lines (output 7 input 10), (output 8 - input 11) and (exit 9 - input 12) in the cache memory of the second level 13 receives addresses and requests from the control unit memory 4 to the data, instructions and mapped memory. On the wire (output 14 input 15) enter the data to be stored. Lines (exit 16 - entry 19), (exit 17 - entry 20) and (exit 18 - entry 21) in the control unit memory 4 from the cache memory of the second level 13 receives the data. The control unit memory 4 is connected by lines (exit 48 - input 49) with the system controller 47, which can be monitored coherence of the memory subsystem. Data from a memory management unit 4 to the system controller 47 are passed by lines (exit 45 - entrance 46), and data from the system controller 47 receives simultaneously a memory management unit 4 and the cache memory of the second level (exit 50 - inputs 51, 52). The cache memory of the second level involves an additional tire, which is direct access to memory without CPU, the system controller 47 lines (exit 65 - input 66), (exit 67 - input 68).

The presence of the byte strobes is recording all the cache memories and mechanism writeback cache memory of the second level allows you to refuse the collection of data in an unaligned operations download/save without loss of performance. When non-cacheable operations internal bus does not support unaligned operations, but the integrated memory controller reduces losses of data collection.

Buffer instructions 1 sends a request for output 2 output 111 of the multiplexer selection address 99. The multiplexer 99 is controlled by block prediction of transition 72 (signal address selection output 97 to the input 98): is selected or the address of the next in order of request lines 106-112 stored in the counter 83, or the target address of the jump line 114-113 stored in the counter transition 104. The count of the passage 104 is written from a block of prediction 72 lines 102-103. To calculate the target address of the jump as the base address is the address of the next request (the value of the counter 83, through 106-105). Decisions on predictions are made on the basis of information received from the control unit buffers 69 on line 73-74 and block fetch/decode commands 80 on line 101-100. The block prediction of transition 72, in addition to control the multiplexer selection address 99, 71-70 provides information about the setting request for the predicted address of the control block buffers 69.

The requested instructions are cache instructions on input 5 buffer instructions 11. Next, on lines 88 received instructions written in the buffer transition 87, to the m instructions are stored before deciding to rewrite them in the execution buffer 94. The main buffer is the execution buffer 94, and the instructions which are written through the multiplexer 77 line 92-93. The multiplexer 77 is controlled by a control signal 75-76 from the control unit buffers 69 and chooses to write in the execution buffer 94 or received instructions from the line 5-91, or instructions, pre-recorded in the buffer transition 87, 89-90.

From the buffer the execution of 94 lines 95-96 instructions are selected (deducted) pairs in the block fetch/decode commands 80. The number of instructions required to read (read 1 or 2 teams), is determined by the control signals 78-79. In block fetch/decode commands 80 there is a partial decoding of the types of instructions, and based on this line in block 101-100 prediction of transition 72 exposed information about the decoding branch instructions based on which the target address is calculated transition placed on lines 102-103 in counter transition 104.

From the block fetch/decode commands 80 statements are submitted: line 107-108 in the unit of analysis dependencies 86, which determines the possibility of their implementation in the current time; lines 107-109 in the block select thread 110. The unit of analysis dependencies 86 generates information about the number of instructions that can be executed. This information on line 115-116 transmitted to the control unit buffers 69, which, based on this information, along the lines 81-82 controls incrementing the counter by the counter 83 to request instructions. Information about the dependencies of the currently selected statement of dependency analysis 86 on lines 115-116 is passed to the block select thread 110, which distributes two received lines 107-109 from the block fetch/decode commands 80 instructions for 4 threads. Depending on the instruction type, which is determined when decoding in the block fetch/decode commands 80, the instruction is directed to one of the outputs of the block select thread 110. To exit 117 (line 117-22) exhibited instructions integer arithmetic, which must be executed in the unit integer ALU 24 (transmitted on lines 22-23); exit 118 (line 118-25) exhibited instructions exchange with memory, which must be executed in the unit integer ALU 24 (transmitted on lines 25-26), a memory management unit 4 (transmitted on lines 25-27) and in real arithmetic unit 29 (transmitted on lines 25-28); exit 119 (line 119-30) exhibited instructions double real arithmetic unit 29, which must be performed unit integer ALU 24 (transmitted on lines 30-31), a memory management unit 4 (transmitted on lines 30-32) and in real arithmetic unit 29 (transmitted on lines 30-33); n is the output 120 (line 120-34) put real arithmetic instructions or data exchange between the integer ALU 24 and real arithmetic unit 29, which are to be performed in real arithmetic unit 29 (transmitted on lines 34-36) and integer ALU 24 (transmitted on lines 34-35).

Data on the inputs of the block of the cache memory of the second level 13 come from the following blocks: from the system controller 47 data to populate the rows of the cache memory is fed to the input 52; from the system controller 47, the data in the direct memory access is fed to the input 68, a memory management unit 4 when executing the save command, the data arrives at the input 15; from real arithmetic unit 29 when executing the save command in the vector mode, the data arrives at the input 63; from real arithmetic unit 29 when the command save mode digital signal processing, the data arrives at the input 64.

Address to the inputs of the block of the cache memory of the second level 13 comes from the following blocks: address command load/store comes from a memory management unit 4 to the input 10; address of command, the requested buffer instructions 1, comes from a memory management unit 4 to the input 11; address command load/store mode digital signal processing comes from a memory management unit 4 to the input 12.

Data from the outputs of the block of the cache memory of the second level 13 enter the following blocks: the system controller 47 in the mode of direct memory access data is being received from the output 65; unit driven by the I memory 4 when the command load data received from the output 18; in the control unit memory 4 to fill a line of the cache memory instructions of the first level data comes from the output 16; a memory management unit 4 to fill the row cache data of the first level data comes from the output 17; in real arithmetic unit 29 when the command is loaded in the vector mode, the data comes from the output 57; in real arithmetic unit 29 when the command load mode digital signal processing data received from the output 58.

When the request from the control unit memory 4 to the filling line, the cache data of the first level to the input 10 receives the physical address, the control unit 136 analyzes the physical address, determines whether the requested information in the cache memory of the second level, and if there is information in the cache memory sends control signals to the blocks of groups of memories 125, 126, 127 and 128 and the output buffer 132. The requested information is transmitted to the output buffer 132 to the output 17. In the absence of a cache memory of the second level requested information corresponding row is loaded in one of the blocks 125, 126, 127 or 128 of the system controller 47 through the inlet 52 and one of the input multiplexers 121, 122, 123 or 124.

When the request from the control unit memory 4 to the filling line of the cache memory commands of the first level to the input 11 receives the physical address, the block management the ia 136 analyzes the physical address, determines whether the requested information in the cache memory of the second level, and if there is information in the cache memory sends control signals to the blocks of groups of memories 125, 126, 127 and 128 and the output buffer 131. The requested information is transmitted to the output buffer 131 to the output 16. In the absence of a cache memory of the second level requested information corresponding row is loaded in one of the blocks 125, 126, 127 or 128 of the system controller 47 through the inlet 52 and one of the input multiplexers 121, 122, 123 or 124.

When you run the command load mode of the direct memory access control unit 136 generates control signals for blocks of groups of memories 125, 126, 127 and 128 and the output buffer 129 based on information stored in registers block 135. The requested information is transmitted to the output buffer 129 to the output 65.

When executing load control unit 136 generates control signals for blocks of groups of memories 125, 126, 127 and 128 and the output buffer 130 based on the address received at the input 10. The requested information is transmitted to the output buffer 130 to the output 18.

When the command is run download in vector mode, the control unit 136 generates control signals for blocks of groups of memories 125, 126, 127 and 128 and the output buffer 133 based on information stored in registers block 135. The requested information is transmitted to the output buffer 133 to the output 57.

When you run the command load mode digital signal processing control unit 136 generates control signals for blocks of groups of memories 125, 126, 127 and 128 and the output buffer 134 based on the address received at the input 12. The requested information is transmitted to the output buffer 134 to the output 58.

When executing the command stored in the direct memory access control unit 136 generates control signals for blocks of groups of memories 125, 126, 127 and 128 and the input multiplexers 121, 122, 123 and 124 on the basis of the information stored in registers block 135. Information intended for entry in the cache memory of the second level, is fed to the input 10.

When executing the save command, the control unit 136 generates control signals for blocks of groups of memories 125, 126, 127 and 128 and the input multiplexers 121, 122, 123 and 124 based on the address received at the input 29. Information intended for entry in the cache memory of the second level, is fed to the input 15.

When you run the command save in vector mode, the control unit 136 generates control signals for blocks of groups of memories 125, 126, 127 and 128 and the input multiplexers 121, 122, 123 and 124 on the basis of the information stored in registers block 135. Information intended for entry in the cache memory of the second level, is fed to the input 63.

When you run the command save mode digital education is otci signals the control unit 136 generates control signals for blocks of groups of memories 125, 126, 127 and 128 and the input multiplexers 121, 122, 123 and 124 based on the address received at the input 33. Information intended for entry in the cache memory of the second level, is fed to the input 64.

CPU instructions are received at the inputs 28, 33 and 36 of real arithmetic unit 29. Data loading in real arithmetic unit 29 of the outer blocks are received at inputs 42, 54, 59 and 60 of the real arithmetic unit 29. Unloading data from a real arithmetic unit 29 in the outer blocks is carried out with outputs 55,43, 61 and 62.

The data inputs 42, 54 and 59 of real arithmetic unit 29 is connected to the inputs 223, 224, 225 diagram of the input interface 226. Input 254 of the same block of lines 253-254 receives data from the register file 293. The schema of the input interface 226 performs switching of the input data and the preparation of the operands for the arithmetic units. The set of control signals to the input interface circuit 226 is supplied from the decoder processor instructions 257 line 256-255. The output 250 of the input interface circuit 226 is connected to the input 251 of the register file 252.

With inputs 28, 33, 36 real arithmetic unit 29 CPU instructions are received at the inputs 258, 259, 260 decoder processor instructions 257. In this block decoding of instructions for the processor and produces sets of control signals.

Blocks 231 and 270 are designed for although the frame perform four multiplications of real numbers single precision. Blocks 241 and 280 allow you to simultaneously perform four operations of addition, and blocks 244 and 283 - four operations subtraction of real numbers single precision. Blocks 231, 241, 244, 270, 280 and 283 are fully konveyerizirovan architecture that allows you to start execution of a new instruction on each clock cycle. When executing a multiplication with accumulation and subtraction operands for unit 231 receives from block 226 along the lines 227-229 and 228-230. The results of the multiplication of the block 231 serves to block 241 on line 289-290 for combination with the third operand, and at block 244 on line 289-291 for subtracting the third operand. The third operand is supplied to the blocks 241 and 244 of block 226 along the lines 238-240 and 238-243, respectively. In the vector mode when executing the same statement occurs calculation of two pieces of real numbers single precision in block 270. The operands for the block 270 receives from the block 267 lines 272-274 and 273-275. The results of the multiplication of the block 270 serves to block 280 on line 297-298 for combination with the third operand, and at block 283 line 297-299 for subtracting the third operand. The third operand is supplied to the blocks 280 and 283 of block 267 lines 277-279 and 277-282, respectively.

These advantages allow universal microprocessor to perform up to 12 teams of real arithmetic with single precision per cycle with simultaneous processing management info the information and the exchange of data between the internal memory and RAM.

The proposed solution allows to combine in a single chip high-performance universal CPU, a dedicated computer and system controller, which leads to the possibility to create a cheap, high performance system for processing images and signals and make decisions on the basis of universal microprocessor.

1. The microprocessor hybrid containing buffer instructions, a memory management unit, the cache memory of the second level, integer arithmetical-logical unit (ALU), the block floating point arithmetic and the controller, wherein the buffer of instructions executed with the ability to predict transitions for loss compensation when performing the transition team and the opportunity to deploy to execute up to four instructions in the mode of signal processing hardware control capabilities of simultaneous execution of instructions in the dynamic reorder, a memory management unit includes a cache memory instruction first-level cache memory data first-level cache second level is made in internal memory for reducing losses in exchange with external memory has eight inputs and six outputs, and is divided into 16 separate memory banks with extra tires, integer ALU is configured to perform two zelocal is the R instructions per cycle, and calculating the addresses to 128-bit load/store, the real arithmetic unit configured to perform two dual operations of multiplication, addition and subtraction of real numbers single precision per cycle and operations of multiplication and addition of double-precision numbers, the controller is implemented in an embedded system controller, the output buffer of instructions which generated the request signal and the address connected to the first input of a memory management unit, output unit, memory management, which is formed by the signal input instructions", connected to the first input buffer, output buffer of instructions, which is formed by the signal "integer instruction", connected to the first input of the integer ALU, output buffer instructions on which a signal is generated integer instruction or instruction load/store", is connected with the second input integer ALU, the first input of the block floating point arithmetic and the fifth input of a memory management unit, the output buffer of instructions, which is formed by the signal "extended instruction load/store", is connected with the third input integer ALU, a second input block floating point arithmetic and the sixth input of a memory management unit, the output buffer of instructions, which is formed by the signal "instruction floating point arithmetic instruction or extended floating point arithmetic is, connected to the fourth input integer ALU and the third input of the block floating point arithmetic, the output data of the integer ALU is connected to the fourth input of the block floating point arithmetic, the output of which is connected to the sixth input integer ALU, address, the output of which is connected to the seventh input of the control unit memory, the address output of which is connected to the fifth input integer ALU, the outputs of a memory management unit, which signals are formed queries and addresses, data, instructions, and save operations, as well as the data to be stored are connected respectively to the first, second, third and fourth inputs of the cache memory of the second level, the outputs of the cache the memory of the second level, on which are formed the signal data load cache instruction and data of the first level, and the output mode internal memory, connected respectively with the second, third and fourth inputs of a memory management unit, the output of which is connected to the first input of the system controller, the output of which is designed to generate a control signal coherence, is connected to the eighth input of a memory management unit, the output of the system controller, which is formed by the signal "input"is connected to the ninth input of a memory management unit and the fifth input of the cache memory of the second level, in the process which is connected to an additional bus to the second input of the system controller, the output of which is coupled to the second additional bus with the eighth entry of the cache memory of the second level, which is direct access to memory without CPU load, the output of a memory management unit connected to the fifth input of the block floating point arithmetic, the output of which is connected with the tenth sign of a memory management unit lines, intended for data transmission, two outputs of the cache memory of the second level is connected with the sixth and seventh inputs of block real arithmetic, the two outputs of which are connected with the sixth and seventh inputs of the cache memory of the second level four additional 128 - bit data bus.

2. The microprocessor according to claim 1, characterized in that the buffer contains instructions buffer transition is made with one input and one output, the control unit buffers made with two inputs and four outputs, the execution buffer is made with one input and one output, the block fetch/decode commands executed with two inputs and two outputs, the block prediction of transition, made with three inputs and three outputs, the block dependency analysis is performed with a single input and two outputs, the counter and the counter of the transition, each made with one input and one output, the block selection execution thread, made with two inputs and four outputs, and two multiplex is a, when the input buffer of the transition connected to the first input buffer instructions, and the output to the first input of the first multiplexer, the second input is connected to the first input buffer of instructions, the first output control unit buffers connected to the first input unit to predict the transition, the second output control unit buffers - with the control input of the first multiplexer, the third output control unit buffers - input counter, and the fourth output control unit buffers - with the second input of the block fetch/decode commands, and the first input of the control unit buffers is connected to the first output unit to predict the transition, and the second input the control unit buffers - with the first output block dependency analysis, the input buffer perform coupled to the output of the first multiplexer, and the output of the buffer perform with the first input of the block fetch/decode commands, the output of the counter is connected to the first input of the second multiplexer and the second input block to predict the transition, the output of the counter transition is connected with the second input of the second multiplexer, a counter input transition to the third output block to predict the transition, the second output of which is connected with the control input of the second multiplexer, the first output of the block fetch/decode commands connected with the third input of the block prediction re the ode, and the second output block fetch/decode commands connected to the first input of the block selecting thread and with the input of block dependency analysis, the second output of which is connected with the second input of the block selecting thread of execution, the outputs of which are connected respectively with the second, third, fourth and fifth outputs buffer of instructions, the first output of which is connected to the output of the second multiplexer.

3. The microprocessor according to claim 1, characterized in that the cache memory of the second level contains four input multiplexer, each of which is made with six inputs and one output, the control unit cache memory of the second level, made with five inputs and three outputs, the unit registers of the RAP and vector mode is performed with a single input and two outputs, four groups of memories, each of which is made with two inputs and one output, and six output buffers, each made with five inputs and one output, while the fifth, eighth, fourth, sixth and the seventh input of the cache memory of the second level are connected, respectively, with the first, second, third, fourth, and fifth inputs of the input multiplexers, the sixth inputs of which are connected with the first output control unit, the cache memory of the second level at which the control signals, the outputs of the input multiplexers, which are formed signalizing, connected with the first inputs of the groups of memories, the first, second and third inputs of the cache memory of the second level at which signals are formed addresses, connected respectively with the first, second and third inputs of the control unit, the cache memory of the second level, the second and third outputs of which are formed the control signals and addresses, respectively connected with the second inputs of the groups of memories and the first inputs of the output buffers, the outputs of groups of memories are connected respectively with the second, third, fourth, and fifth inputs of the output buffers whose outputs are connected respectively to the outputs of the cache memory of the second level connected with the first additional bus, with the outputs of the cache memory of the second level, connected with the second, third and fourth inputs of a memory management unit that outputs the cache memory of the second level, connected to the sixth and seventh inputs of the block floating point arithmetic, the outputs of the register unit of the RAP and vector mode, in which data signals are formed, is connected with the fourth and fifth inputs of the control unit, the cache memory of the second level, and the output of the register unit of the RAP and vector mode is connected to the fourth input of the cache memory of the second level.

4. The microprocessor according to claim 1, characterized in that the block floating point arithmetic, contains two asymmetric schemes of the input interface, the first of the which is made with five inputs and nine outputs, and the second one with three inputs and five outputs, the decoder processor instructions executed with three inputs and twelve outputs, two twin-block multiplication of single-precision, each of which has three inputs and one output, the block multiplication of double-precision made with three inputs and one output, two twin-unit addition of single-precision, each of which has four inputs and one output, two twin block subtract single-precision, each of which has four inputs and one output, the block addition of double-precision made with four inputs and one output, two single-ended output interface circuit, the first of which is made with six inputs and four outputs, and the second with four inputs and two outputs, two register files, each of which is made with two inputs and one output, in this case, the first, second and third inputs of the first circuit input interface connected, respectively, with the fourth, fifth and sixth inputs of the block floating point arithmetic, which receives the input data, the first and second data outputs of the first circuit input interface connected respectively with the first and second inputs of the first dual-unit single-precision multiplication the third and fourth data outputs of the first circuit input interface with dynany respectively with the first and second inputs of block multiplication of double-precision, the fifth and sixth outputs the data to the first circuit input interface connected respectively with the first and second inputs of the first dual-unit addition of single-precision and with the first and second inputs of the first dual block subtract single-precision, seventh and eighth data outputs of the first circuit input interface connected respectively with the first and second inputs of the unit of addition of double-precision, the ninth data release of the first circuit input interface connected to the first input of the first register file, the output of which is connected to the fourth input of the first circuit input interface, a fifth input connected to the first output of the decoder instructions for the processor on which are formed the control signals, first, second and third inputs of the decoder instructions of the processor are connected respectively with the first, second and third inputs of the block floating point arithmetic, second and third output control signals of the decoder instructions of the processor are connected to third inputs, respectively, of the first dual block multiplication of single-precision and block multiplication of double-precision, the fourth output control signals of the decoder instructions connected to the first input of the second circuit input interface, the fifth output control signals of the decoder instructions connected to the first input of the second dual of the block is mnogaya single-precision, the second input of the second circuit input interface is connected to the seventh input of the block floating point arithmetic, the first and second data outputs of the second circuit input interface connected respectively with the second and third inputs of the second dual block multiplication of single-precision, third and fourth data outputs of the second circuit input interface connected respectively with the first and second inputs of the second dual block addition of single-precision and with the first and second inputs of the second dual block subtract single-precision, the fifth data release of the second circuit input interface connected to the first input of the second register file, the output of which is connected to the third input of the second circuit input interface, the output of the first dual block multiplication of single-precision forming signal dual of the multiplication of single-precision, connected to the first input of the first circuit output interface and third inputs of the first dual-unit addition of single-precision and the first dual block subtract single-precision, the output of block multiplication of double-precision connected with the third input of the unit of addition of double-precision and with a second input of the first circuit of the output interface, the output of the second dual block multiplication of single-precision connected to the first input of the second circuit of the output of interest is the face and third inputs, respectively, of the second dual block addition of single-precision and the second dual block subtract single-precision, the fourth, fifth and sixth outputs of the decoder instructions for the processor on which are formed the control signals, connected to the fourth inputs, respectively, of the first dual-unit addition of single-precision, the first dual block subtract single-precision and block the addition of double-precision, seventh and eighth outputs of the decoder instruction processor that generates control signals, connected to the fourth inputs, respectively, of the second dual block subtract single-precision and the second dual block addition of single-precision, the outputs of the first dual blocks addition and subtraction of single-precision and block the addition of double precision respectively connected with the third, fourth and fifth inputs of the first circuit of the output interface outputs second double blocks addition and subtraction of single-precision connected respectively with the second and third inputs of the second circuit output interface, ninth and tenth outputs of the decoder processor instructions, which are control signals, respectively connected to the sixth input of the first output interface circuit and the fourth input of the second circuit of the output interface, the first, second and third data outputs of the first circuit of the output interface and the first data release of the second circuit output interface connected to sootvetstvenno the outputs of block floating point arithmetic, the fourth data release of the first output interface circuit and the second output data of the second circuit output interface connected with the second inputs respectively of the first and second register files.



 

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