Three-cascade commutation system

FIELD: information technology.

SUBSTANCE: present invention relates to computer engineering and communications. The system contains input, intermediate and output cascades of corresponding commutation units X, R, Z (X=1,…,x, R=1,…,r, Z=1,…,z). Data inputs of the X units of input cascade form data inputs of the system. Data outputs of the Z units of the output cascade form data outputs of the system. The system works in three modes: tuning, where there is searching and setting up communication channels, information transfer, complete or partial break up of communication channels. The process of setting up new communication channels takes place on the background of information transfer on channels set up earlier. Thirteen control inputs are used to control the system.

EFFECT: more functional capabilities of the three-cascade commutation system due to provision for the process of setting up new communication channels on the background information transfer on channels set up earlier, as well as cutting on time for setting up communication channels due to reduction of the number of steps for setting up the system.

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The device is intended for use in computing and communications.

Known digital switch with spatial division multiplexing (see U.S. patent No. 4417245, 1983). However, in this device there is no possibility of carrying out the process of configuring the switch on the background of information transfer.

The closest in technical essence is a three-stage switching system used in multiprocessor computing systems, consisting of input, intermediate and output stages, each of which contains a group of switching blocks, each block contains a switching matrix cell switching and control node. Each cell switching units switching of the input and intermediate stages contains a node comparison site disassembly of the communication channel, the elements of memory-triggers, items, And and OR. Each cell switching units switching of the output stage node contains disassembly of the communication channel, the memory element trigger elements And. (see A.S. USSR №1226481, 1985).

The disadvantage of this device consists in the impossibility of carrying out the process of configuration of the switching system on the background of information transfer, as the phase settings of the communication channels, information transfer and disassembly of communication channels are clearly demarcated.

Technical goal: create a schematic three-stage switching system with PA the allelic configuration and transmission of information, performing a simultaneous search of all necessary communication channels, the transmission of information from inputs to outputs educated on the communication channels, and ensuring the process of setting up new communication channels for the background transmission of information on a previously-configured channels.

Effect: increased functionality of the three-stage switching system by providing a process set up new communication channels for the background transmission of information on a previously-configured channels and reducing the setup time of the communication channels by reducing the number of steps in the system configuration.

It is achieved by the fact that each switching unit of the output stage known three-stage switching system entered the buffer storage device. The address inputs of the buffer memory devices (RAM) connected to the outputs of the counters. Inputs installation of the buffer RAM in the third state is connected to the additional vertical coordinate tires. The outputs of cells switching, located in the same vertical row switching unit output stage, connected to the corresponding additional vertical bus.

Installed additional triggers (with inverted inputs), input setup

"" which is connected on the one hand to the outputs of the elements And to the E. are connected to these outputs to the inputs of the respective cyclic shift registers, on the other hand, the inputs settings "" are connected with an additional tire, which is connected to the inverter output, the input of which is applied a control potential H0. Input reset "" more triggers connected to one of the outputs of the buffer RAM, and the data outputs of the triggers are connected with the inputs of the additional element And the output signal of which is fed to the Central control device (CUU).

In addition to all the switching blocks of the intermediate cascade entered inverters, the number of which is equal to the number of triggers on the inputs "S" which is potential initial setup the initial state of the system SI. In the proposed switching system instead of this potential to the inputs of the installation "S" triggers served potential H0. The input of each inverter is connected on the one hand with the output node of the accelerated expansion of the busy signal, the input coordinate bus, and on the other hand - with the reset inputs R of the triggers, the output of the inverters is connected to the inputs of the installation "S" triggers.

In addition, all the switching blocks in the input stage used elements of two-input And, the number of which is equal to the number of communication lines between the blocks of the input and intermediate cascade, and permanent storage device (ROM) with a third state at the output is e, the number of which is equal to the number of information inputs of the system. In addition, the proposed device introduced additional vertical and horizontal bus connected to one output of the respective cell switching. Auxiliary input(input setup item in the third state) of each input element And connected its output to one vertical the data bus, is connected with additional vertical bus, and additional inputsA ROM connected to the same horizontal information bus connected to the corresponding additional horizontal bus.

In addition, each cell switching of the switching blocks of the output stage introduced two additional input element And. To one input of the first input element And is served tuning potential, the second input of the same element connected to the inverse output of the trigger cell switching, and the output to the input of one already installed in the existing switching system elements chetyrehhodovogo I. the First input of the second additional element And connected to the direct output of the trigger to the second input of this element is potential fixation of communication channels, and the output is connected with an additional coordinate bus of the switching unit of the output cascade is.

In each cell switching of the switching blocks of the intermediate cascade introduced an additional element of two-input And, one input of which is connected to the inverse output trigger control, the second input is the potential configuration of the switching system, and the output connected to the input node of the comparison cell switching. In each cell switching of the switching blocks in the input stage introduced an additional element of two-input And, one input of which is connected to the inverse output of the trigger, the second input is the potential configuration of the switching system, and the output connected to the input node of the comparison cell switching.

The signal from the direct output of the trigger cell switching of the switching blocks in the input stage is removed and fed to two additional horizontal and vertical coordinate bus switching unit input stage.

Figure 1 shows the structural diagram of three-stage switching system, figure 2-4 - functional block map switching, respectively, output, intermediate input and cascades, figure 5-7 - functional circuit cell switching, respectively, output, intermediate input and cascades, Fig - functional diagram of the buffer RAM figure 9 - timing diagram of control signals.

The proposed switching system (Phi is .1) contains z switching blocks 1.1, 1.2, ..., 1.Z forming the output stage r block switching 2.1, 2.2, ..., 2.R, forming an intermediate cascade × blocks switching 3.1, 3.2, ..., 3.X, forming the input stage, R×x information inputs of the system (U.x.p), which simultaneously inputs the data blocks switching 3.X input stage, m×z information system outputs (V.z.m.), which simultaneously outputs the data blocks of the switching output stage, lines of communication (Chg.) between blocks 3.X and 2.R input and intermediate stages, connecting the outputs of the data blocks 3.X input stage with input data blocks 2.R intermediate cascade, and communication lines (D.r.z.) between blocks 2.R and 1.Z intermediate and output stages, connecting the respective outputs of the data blocks 2.R with inputs data blocks 1.Z.

When Z=1, ..., z; P=1,..., p; R=1, ..., r; X=1, ..., x; M=1, ..., m.

The switching system also includes the following control inputs: t-clock input; H0 is the input set of triggers switching blocks of the input and intermediate stages in the state "1"; SI - entry initial setup status registers cyclic shift; p input settings; P1 is the first synchronization input corresponding to the first palusalu settings; P2 - the second synchronization input corresponding to the second palusalu settings; plucked, produces C1 is the first log run to run comparison sites; CU2 - input unlock DL the resolution of the conflict with the occupation lines C.X.R; SI - second input of the start to run sites comparison in the second half step tuning; SI input fixation of communication channels; SI - input search nonblocking communication channels; P3 - input disassembly of communication channels; A4 - entry permit transmission of information.

Each block 1.Z output stage (figure 2) consists of a matrix of cells 4.R.M. switching and control node that contains the group of registers cyclic shift M, the first group of elements AND 6.R., the second group of elements AND M a block 1.Z. through S.m.r. marked direct outputs r-s bits cyclic shift registers M

In addition, each block 1.Z. contains M buffer storage devices RAM FIFO type, which is written as it is read from external RAM. Each buffer RAM has four inputs that control the operation of this RAM and two output data. The first output data is connected to the information output system (V.z.m.), and the second output data is connected to "" inputs of flip M Entrance(input setup the buffer RAM in the third state of each storage device are connected to a common coordinate bus L.z.m. The CS input of each RAM M connected to the output of the clock generator control device, and the enable input read commands switching of each buffer RAM M W/R is connected to the output p. Direct output is s triggers M connected to the inputs of the element AND 10.Z., the potential output of which is fed to the Central control device. Potential H0 applied to the inputs "" triggers M through the inverter 11.Z.

Each block 2.R. intermediate cascade (figure 3) consists of nodes accelerated propagation of employment H, the matrix of cells 13.Z.X. switching trigger group H and group items AND H

In addition, each block 2.r. consists of elements AND H

Each block H (figure 4) in the input stage consists of a matrix of cells switching 17.P.R., item H ID of the switching unit, the group of keys (elements) 19.R. and memory elements R identifiers inputs R.

In turn, each cell 4.R.M. (figure 5) consists of the trigger 21 of the switching node disassembly of the communication channels 22, items, And 23-26, as well as elements And 27 and 28. Through T.r.m. marked inverted output of the trigger 21, which is output employment cell.

Each cell switching unit intermediate cascade 13.Z.X. (6) consists of an element OR 29, node comparison, 30, triggers, 31 switching and 32 control element barring 33, node 34 disassembly of communication channels, items, And 35-38.

In addition, the cell consists of element And 39. At the first input element And 39 is potential settings p, and the second input is connected to the inverted output trigger control 32.

To the ome, in each switching node 13.Z.X. is the entrance F.Z.X. characteristic employment coordinate input bus and the output E.Z.X. employment cells that are necessary to resolve the conflict in the distribution lines SHG.

Each cell switching unit input stage 17..R (figure 5) consists of item 40, node 41 disassembly of the communication channel, item, OR 42, node comparison, 43 and trigger switching 44. In addition, the cell contains the element And 45, at the first input of which is applied a potential configuration P2, a second input connected to the inverse output of the trigger 44, and the output connected to the input node of the comparison 43. With direct trigger output switching 44 is removed signal.

The proposed three-stage switching system with a parallel configuration and transmission can operate in three modes: in configuration mode, which is the search and lock channels of communication, in the transmission mode information mode disassembly of communication channels, become unnecessary. When this transfer of information can go on the background setting and disassembly of communication channels.

The operation of the switching system begins with the installation in the direct state triggers H and M It is the impulse applied to the input H0 switching system. Setting the switching system in this initial state prepares to configure Cana is s connection.

The pulse also sets H0 in inverted condition triggers 21 through nodes disassembly of the communication channels 22 in each cell 4.R.M., triggers 31 through nodes disassembly communication channels 34 and the element OR 29, the trigger 32 through the nodes disassembly communication channels 34 in each cell 13.Z.X. and triggers 44 through the nodes disassembly channels of communication elements 41 and 42 in each cell 17.P.R.

Setting mode switching system begins with the installation of all registers cyclic shift M to its original state. This is done by impulse applied to the input SI switching system.

This impulse, acting on the inputs of registers cyclic shift M, write the appropriate code, containing only one unit in that category, to the direct input of which is connected to the input SI. Thus, after recording these codes in registers M located within one block 1.Z. will not be the same codes. In the shift registers 5.1. the unit recorded in the first position, the shift registers 5.2 - second, etc. Finally, in the shift registers M unit recorded in the range M After entry codes capacity with direct access S.m.r. discharge containing unit, each register M is supplied to the corresponding elements 23 and 24, and prepare them to receive information.

Search and lock channels in the configuration mode is carried out in switching systems is under the influence of program switching and control signals, appearing on the respective control inputs of the system in accordance with the time chart shown in Fig.9. Program switching is an ordered in accordance with the location of exits V.z.m. switching system many teams switching, representing a pair (BC)identifying those inputs U.x.p. switching system with which you want to connect the corresponding output V.z.m. Thus x is the address of the block H, which is the required input, and p is the address of the desired entry within that block. In the memory elements H and R everybody block H contain the identifier x of these blocks and the ID of the p inputs U.x.p. switching system.

Team switching consists of m=log₂(P×X) bits. When writing commands switching in the buffer RAM external RAM bus I.M to m-bit command switching added an extra zero bittaker way, each RAM M stored N (m+1)-bit pairs (BC). Functional diagram of the buffer RAM presents on Fig. Information from the external RAM is written in the buffer RAM running counter M connected to the address inputs of RAM M To the input data DI RAM M do (m+1)-bit command switching from the external RAM bus I.M. Outputs Q1-Qn of the counter connected to the address inputs A1-An of RAM M input CS OF THE AT M (which allows or denies his work) receives clock pulses. On the enable input write/read W/R RAM M receives control signals p. Each buffer RAM M has two output data. One output is connected with the information output of the switching system V.z.m., and a second output connected to the reset inputtrigger M

Further operation of the switching system in setup mode directly associated with finding and fixing communication channels in accordance with the routine switching. Routine switching is the set of (m+1)-bit pairs (BC), at the same time coming to the outputs of the buffer RAM M Feature of the proposed switching system in this mode is that the system is a search simultaneously all the necessary communication channels in accordance with the routine switching.

Each configuration step is two half-step. During the first half-step search communication channels through blocks 2.R. intermediate cascade to blocks H input stage. In the second half step is the search of the communication channels for specific inputs U.x.p. in block commutation H, education branching units switching 2.R. communication channels with the outputs V.z.m., if they are connected to the buffer RAM M kept the same address information and the fixation on the established channels in all blocks of the switching of the switching system.

When configuring accumulated to this point in time many teams switching, which is a sub-program switching in parallel is read from the buffer RAM M and comes on available information, the system outputs V.z.m.

The first half step of the first step of the configuration begins by applying to the inputs of p, P1 and plucked, produces C1 control signals depicted in the timing diagram.

The signal p doing to the input of the write/read information W/R buffer RAM M, authorized the issuance stored in them commands the switching to the appropriate outputs V.z.m. the switching system. This same signal is applied to the inputs of all elements And 27 in all cells 4.R.M. as a result, those elements And 27, the second input of which is received a signal "1" with inverted outputs of the trigger 21 will be prepared to receive configuration information. In turn, the signal from the outputs of the elements And 27, the signal from the direct outputs S.m.r. those bits cyclic shift M that store unit, and enables the output signal VG. elements AND 6.R. coming on the third control inputs of elements And 24, are preparing these items for the reception of configuration information.

Among all elements And 24, connected by an input to the same output V.z.m., there will be only one prepared to receive information. Similarly, among all elements And 24, are connected to one communication line D.r.z will only typothetae to the transmission of information.

Potential p permit issuance (m+1) bits teams switching from the buffer RAM M the Last zero bit switching commands "0" is supplied to the reset input "" triggers M and translates them into the zero state. The remaining m bits of teams switching bitwise will start flowing in is connected to the buffer RAM M output V.z.m through the prepared item And 24 to link D.r.z. the inputs of the nodes comparison 30 located in the cell 13.Z.X. connected to one communication line. Naturally, first of all will be the address bits X 3 blocks-X.

Only those nodes comparison 30, which receives a positive potential p through the element And 39, will be prepared for comparison address X. In turn, only those elements And 39, the second inputs of which received the signal "1" with inverted outputs of the triggers control 32 will be prepared to receive the tuning potential p.

On the other hand, the input P1 acting on the inputs of the memory elements H in blocks 3-H., allows bitwise transfer addresses X all blocks 3-X. the Address X of the memory element H in each block H through public key 19.R. (element), acts simultaneously on all available from the information transmission line connection C.x.R associated with this block. Key 19.R is in the closed state (the third state at the output) in the case of the AE, if at least one cell switching 17.P.R. connected to the communication line C.x.R, set the communication channel. In this case, the signal from the direct output of the trigger 44 cell switching 17.P.R. passes on the bus J.x.R to the entrancekey 19.R. and sets the element 19.R. in the third state, thereby prohibiting the transfer addresses X block X on the appropriate line of communication C.x.R.

Free links SHG. address X arrive at the second input node of the comparison of 30 prepared for comparison information.

The signals existing at the inputs p and plucked, produces C1, allow comparison of the first bits of the address X of the switching commands.

Depending on the results of comparison of the trigger 31 will be set in direct or remain in the inverted condition. Those nodes comparison 30, the inputs of which receive the same values of the first bits of the address X, the set connected with them triggers 31 in the forward state, and the signals appearing on the direct inputs of these triggers allow further comparison of the address digits X commands switching on these sites comparison. Each signal the following equality confirms the direct state of the trigger 31. The signal inequalities generated by node comparison 30 at any step of the comparison, after passing through the element OR 29, will set the trigger 31 in inverted condition, thereby stop further comparison of the bits of the address is s X in this node comparison 30. After issuing comparing all bits of the address X in accordance with the time chart is input P1 and temporarily removed from input p. As a result of direct state will remain only triggers 31, on which all the time was received signals are equal to the node comparison 30.

Since the addresses X, received one block 2.R., clearly define lines of communication SHG., connecting this unit with the blocks H input stage, one would assume that the communication channel through the intermediate block is defined. However, due to the fact that one block commutation H connected to R inputs, there is a high probability of receipts from different blocks 1.Z. on cell 13.Z.X. connected to one communication line SHG. pairs (BC) is equal to X, but unequal R. In the first half step tuning these pairs it is impossible to distinguish, i.e. all the triggers 31 cells 13.Z.X. received equal to X, not dependent on further R will be installed in the direct condition. Thus, there is a conflict over the occupation of the communication line SHG. To resolve this conflict and to create the search capabilities of the communication channel in blocks switching H in the second half step of setting you need to decide what kind of highlighted in the first half step of setting a setting triggers 31 in the direct state lines D.r.Z be connected to the communication line SHG.

In the proposed switching system is IU accepted that open line of communication SHG. from all claiming a connection to the database in this step, the communication line is selected, in which the value of the parameter Z is the least. This selection is done during the pulse to the input of CU2. This pulse is fed to the input elements AND H, which receives signals from the direct outputs of the respective triggers H

If all cells 13.Z.X. connected to the bus F.Z.X. remain unoccupied, the trigger H maintains a positive potential to direct the output. If through the cell 13.Z.X. in the following steps, the settings will be set to the communication channel, the busy signal coordinate bus will reset the trigger H, as its reset input "R" will be supplied to the positive potential bus F.Z.X, and the input setup trigger in one state "S" is a negative potential through the inverter H

Output G.X. elements AND H prepared triggers H, a pulse that enters the elements 33 and 38 all cells 13.Z.X. connected to the corresponding lines of communication SHG.

Suppose that triggers 31 cell switching 13.1-H., 13.2 Agricultural, ..., 13.Z*-1.X., connected respectively to the lines D.r.l., D.r.2., ..., D.r.Z*-1., installed in the inverted condition, the trigger 31 of the cell 13.Z*.X. installed in the forward condition, and triggers 31 and all other cells 13.Z.X. (when Z>Z*), connected to the same line is due SHG., set in either direct or inverted state.

Then the elements of the prohibition 33 in cells 13.Z.X. (Z<Z*) will be blocked by the signals from the direct outputs of the trigger 31. Item ban 33 in the cell 13.Z*.X. will be prepared to pass the information as to its control input receives an enable signal from the direct output of the trigger 31. By blocking the entrance of this element of the ban 33 signal is not received, as in cells 13.Z.X. (Z<Z*) signal F.Z.X. employment input bus is not generated, i.e. their triggers 31 are inverted state into force adopted the above assumptions. Therefore, the output F.Z*-1.X host H accelerated expansion of the busy signal, the input coordinate bus with no signal. Thus, the pulse received from the output of the corresponding element AND H passing through the element barring 33 in the cell 13.Z*.X., will throw in a live state of the trigger 32. In addition, in the same cell on the item And 38 will form the basis of employment of the input bus. This feature will be available with output E.Z*.X cell 13.Z*.X to the corresponding input node H and for one measure will apply to all inputs F.Z.X cells 13.Z.X. when Z>Z*blocking elements prohibition 33 located in these cells, and thus will prevent the forward condition of the trigger 32 in all cells 13.Z.X. (Z>Z*) regardless of the status of the trigger 31. ignal employment, arising in the element 38 any cell 13.Z.X. passing through the node H accelerated propagation of employment will come to an inverse input of the corresponding trigger H and translate it into an inverted state.

Thus, until the cell switching unit switching the intermediate stage is busy, the zero state at the output of the trigger H will block installation chain trigger 32 in the forward state and the circuit generating signals conflict resolution in cells 13.Z.X.

In the above steps, if any of the cells 13.Z.X. connected to one line of communication SHG., there were some many cells, triggers, 31 of which were in direct condition, only one of these cells 13.Z.X., the trigger 32 will move in the forward condition and will remain in this state until the end of the work. The trigger 32 will prepare the item And 35 to the passage of information in the second half step of the configuration.

The second half-step configuration begins with the receipt of signals at the inputs of P2, SI and resume input p switching system. The reappearance of the signal at the input p allows further bitwise transfer configuration information from the buffer RAM M Remaining in the buffer RAM M configuration information represents the address P of the switching commands.

These addresses are entered on the outputs V.z.m., are the via elements And 24 in cells 4.R.M. lines D.r.z. through the elements And 35 prepared by the output signal P2 on the line SHG. With lines of communication SHG. address P bitwise arrive at the inputs of the nodes comparison 30 in cells 13.Z.X. and 43 in cells 17.P.R.

On the other hand, at the second input node of the comparison 30 receives address lines D.r.Z. from the buffer RAM M different cells 1.Z. At those sites comparison 30, the inputs of which has an enable signal from the direct outputs of the triggers 31, a bitwise comparison of the address codes will continue in the same way as described above.

On the sites comparison 43 on the second input will be received address P. But they will come from the memory elements R running input P2 through inputs U.x.p. system. This address will be received only from those memory elements R, inputwhich receives an enable signal "0" on the bus Chr otherwise, the elements R will be located in the third (closed) state. Item R is in the closed state if at least one cell switching 17.P.R. connected to one input of an information bus U.x.p., set the communication channel.

Comparison of the first digits in the comparison sites 43 will be allowed by the signals appearing at the inputs P2 and SI. Only those nodes comparison 43, which receives a positive potential P2 cher the C element And 45, will be prepared to compare addresses R. In turn, only those elements And 45, the second inputs of which received positive potential with inverse outputs of the triggers 44, will be prepared to receive the tuning potential P2.

Further comparison in the comparison sites 43 will be the same as in the comparison sites 30. The process of comparing the address P of the teams switching ends after passing through the last bits of address R. then removed signals from inputs p and P2 of the switching system.

As a result, the triggers 31 and 44, which received signals only equality of nodes comparison 30 and 43, will be in direct condition.

For fixing the found communication channels in cells 13.Z.X. a signal is generated fixation. The formation of this signal is those elements And 37, the control inputs of which are filed with the signals from the direct outputs of the trigger 31. Impulse SI passes through these elements And 37 on the corresponding lines of communication D.r.Z. and it arrives at the inputs of elements And 23 in cells 4.R.M. Through the elements And 23, the second inputs of which are signaled with direct access S.m.r, r-th digit of the corresponding shift register M, the signal-commit is on direct inputs trigger 21 and installs the latest in a live state. The signal from the inverted output T.r.m. trigger 21 is removed, and thus through e the cops And 6.r. blocked from passing configuration information through the elements And 24 in all cells 4.R.M connected to one communication line D.r.Z. in Addition, the trigger 21 is installed in the direct state through the elements AND M block the passage of the pulse cyclic shift SI on the cyclic shift registers M

In addition, the triggers 21 cells switching of the switching blocks of the output stage installed in the direct state transfer buffer RAM M connected to the outputs of the cells in the third (closed) condition via coordinate bus L.z.m. In this case, the coordinate bus L.z.m receives a positive potential through the element And 28, at the first input of which receives the signal from the direct output of the trigger 21, and the second signal fixing CI. Thus, in the next step of the configuration is locked buffer RAM M will not participate in the configuration process.

In addition to the actions performed on the second half step of setting the switching system is performed preparatory work to complete the next step. Preparation is the shift towards high-order bits of content unlocked items AND M shift registers M Shift is carried out by giving pulse to the input of SI switching system. Let the result of the shift unit, previously recorded at r*-th digit of the shift register M, go in (r*+1)-th RA is the number and accordingly the signal direct output (r*+1)-th bit of this register will be available at the entrance of the cell 4.r*+M, connected to the communication line D.r*-1.Z. If this line is connected cell GM (r=r*+1), in which the trigger 21 is in direct condition, any changes in the cells 4.r*+M not going to happen. If among cells 4.R.M. connected to the communication line D.r*+1.Z., there is no node with a direct condition of the trigger 21, the And gate 24 cells 4.r*+M will be prepared to transfer configuration information from the output V.z.m. on line D.r*+1.Z.

As a result of the action of the switching system is ready for the next step of the configuration on which you are checking the possibility of building is locked at the current step of setting up communication channels through other blocks 13.Z.X. intermediate stage.

The next step of the configuration is basically the same as described for the first step. The only difference lies in the fact that recorded in the previous steps communication channels through the cell 13.Z.X. can add new branches, if previously recorded channels of communication and new branches enters the same configuration information. For previously recorded channel tuning information is supplied from the corresponding buffer RAM M on the following route: exit V.z.m. switching system, element, And 25 cells 4.R.M. with the trigger 21 in the forward condition, the communication line D.r.Z., the And gate 35 in the cell 13.Z.X. with the trigger 32, located right in the state, lines of communication SHG., the inputs of the respective nodes comparison 30. Tuning information for new branches goes on further routes: the buffer RAM M, outputs V.z.m. switching system, unlocked items And 24, the communication line D.r.Z., the inputs of the respective nodes 30 comparison.

Further, the matching process is also as previously described. It should be emphasized that the state commit already found the channel in the switching system is confirmed at each configuration step.

The process of configuring a switching system will continue until, until you have found the communication channels for the whole routine switching, received information on the outputs from the buffer RAM in the first configuration step. This process is controlled by ZUO which is the potential of the output element AND 10.Z. block of the switching output stage. The inputs of the element AND 10.Z. connected to the direct output of the trigger M IN the initial state of the system, when its control inputs comes the potential H0, triggers M are installed in the direct state negative potential, filed with the inverter 11.Z. on the input set of triggers in one state ""with the item AND 10.Z. served a single potential on CUU. In the first step of setting at the time of reading out of the first zero bit "0" of the team switching the z buffer RAM M triggers M reset thus the output of the element AND 10.Z appears zero potential, which sends a signal to the Central control device about the beginning of the configuration process. If in the process of searching on the first configuration step for the team switching, issued on the information output V.Z.M, found a free channel, then the zero potential from the output element M is supplied to the reset input "" trigger M and sets it in a live state. Thus, as for all switching commands issued on the information outputs V.z.m, there are no available communication channels, the search process communication channels will not end, because the output element AND 10.Z will be zero potential.

The maximum number of configuration steps that you must perform to complete the process of finding and fixing all the required communication channels, is equal to R. This is due to the fact that for each pair (BC) there are R different communication channels via a cascade switching system. For non-blocking three-stage switching system, at least one of them will be unlocked regardless of in which order to search these channels.

After i run the setup steps when blokiramo three-stage switching system will record all required by the subroutine comm is to adapt the communication channels, output element AND 10.Z. appears singular potential, giving the signal ZUU on the termination of the process of setting up communication channels.

Phase information transfer begins by applying to the input A4 of the respective signal, information passes from input U.X.P. through the communication line C.X.R, the And gate 36, the communication line D.R.Z., the And gate 26 to the output V.Z.M. switching system.

The signal disassembly communication channels comes from CUU. Mode disassembly communication channels control signals fed to the input P3 of the switching system and at the entrance U.X.p., the communication channels from which you want to parse.

As a result, through node 22 disassembly of communication channels will be reset to the inverse state of the trigger 21, via the node 34 disassembly of communication channels and the element OR 29 - triggers 31 and 32, and through the node 41 disassembly of communication channels, and the item OR 42 - trigger 44 and, thus, will be dismantled appropriate channels of communication through the switching system.

The next phase configuration of the switching system is initiated by the signal from CUU. When this accumulated to this point in time many teams switching is read in parallel from the "unlocked" buffer RAM M and comes on available information, the system outputs V.z.m. While on the already established communication channels continues to be transmitted information, and occupied the line V.z.m., D.z.m. and SHG. blocked for before the Chi configuration information at this stage settings.

The proposed three-stage switching system allows you to search simultaneously all M×Z communication channels connecting the R×X inputs with M×Z outputs for the first steps of operation of the system. Step operation of the system consists of a number of clock cycles needed to complete the m+1-bit code, plus two additional clock cycle, due to the algorithm. Thus, search M×Z communication channels in the proposed switching system takes (log₂(P×X)+3)×i of ticks.

Sources of information

1. U.S. patent No. 4417245, 1983

2. USSR author's certificate No. 1226481, 1985 (prototype)

Three-stage switching system containing the input, intermediate and output stages, each of which contains a group of blocks switching, the input data blocks switching input stage are informational inputs system outputs data blocks switching of the output stage are information system outputs, outputs data of each block switching input stage connected to the corresponding inputs of the data blocks of the intermediate switching stage, the data outputs of each block of intermediate switching cascade connected to the corresponding inputs of the data blocks of the switching output stage, each switching unit includes a matrix of cells switching, information inputs of the cells switching of Kazahstana matrix are combined to form the input of the corresponding bit data of the switching unit, information outputs of cells switching each row of the matrix are combined to form the output of the corresponding bit data of the switching unit, each block of the switching output stage further comprises a control node, which contains a group of cyclic shift registers, synchronization inputs of which are connected to the input of the initial installation status registers cyclic shift SI, the first group of elements And the outputs are connected to the serial data inputs of the respective registers of cyclic shift groups, the output bits are connected to the inputs of the cell selection switching of the respective cell switching S.m.r., the input elements And the first group is connected to the input of the search nonblocking communication channels SI, and the other inputs connected to the outputs of employment cell switching T.r.m, the second group of elements And the inputs of which are connected to the outputs of the employment cell switching T.r.m., and outputs with the inputs of the block of cells switching V.G., each switching unit of the intermediate cascade additionally contains a group of nodes accelerated expansion of the busy signal, the trigger group and the group of items, and the first inputs of elements And groups connected to the respective outputs of the trigger group, the reset inputs of which are connected to the input of the initial installation of the system which we have H0, the second inputs of elements And groups connected to the input of the unlock system CU2, the outputs of the elements And groups connected to the inputs of the sign of the absence of a communication channel of the cell switching unit switching the intermediate cascade of the corresponding column of the matrix G.x., the outputs of employment cell switching each column of the matrix of intermediate cascade E.z.x. connected to the inputs of the respective schemes accelerated propagation employment group, the outputs of the last digits are connected to the inputs set the appropriate trigger switching blocks of the intermediate stage, and the rest of the outputs to the inputs of the sign employment coordinate bus F.z.x. from the second to the last cell switching of the corresponding column of the matrix of the switching unit, each unit switching input stage further comprises a group of memory elements of the IDs of the inputs, the outputs are connected to inputs of respective bits of the data block switching memory elements of the identifier of the switching unit and the group of keys (elements)whose outputs are connected to the outputs of the respective bits of the data of the switching unit, the input key group connected to the outputs of the bits of the memory element ID of the switching unit, the input of the reading of which is connected to the first input of the synchronization system P1, inputs the read element of the s memory IDs of the inputs of the group United and connected with the second synchronization input system P2; cell switching of the switching blocks of the input, intermediate and output stages contain the trigger and the first switching element And whose output is an information cell output, the first and second inputs of the first element And is connected to the direct output of the trigger switching and information input cell switching, respectively, the cell switching unit switching the output stage further comprises a node disassembly of channel bundles, with the second through fourth elements, and in each cell switching unit switching the output stage of the first input of the third element And is the entrance lock of the cell switching outputs of the third and fourth elements And cell switching output stage combined and connected to the information input node disassembly of the communication channel and the first inputs of the second element And the second input is combined with a second input of the third element And is the input sample cell switching output stage S.m.r., output employment which is connected to the inverse output of the trigger switching inputs set and reset which is connected to the output node disassembly of the communication channel and the second element And, respectively, a third input connected to the input of fixing channels of communication systems SI, direct trigger switching cell switching output stage connection is with the enable input node disassembly of the communication channel and to the first input of the fourth element, And the second input is combined with the third input of the third element And is connected to the output of the first element And the third and fourth inputs, respectively, the third and fourth elements And cell switching output stage connected to the input of the system setup p, the first and second inputs of the synchronization of all nodes disassembly of communication channels connected to the input of disassembly communication channels P3 and to the input of the initial system installation H0, respectively, the first and second input nodes of the comparison input stage connected to the second inputs of the synchronization P2 and running SI accordingly, each cell switching units switching of the input and intermediate stages further comprises a host comparison site disassembly of the communication channel and the element OR the output of which is connected to the reset input of trigger switching, the output of which is connected to the input node of the comparison site and disassembly of the communication channel, the output node of the comparison and the output node disassembly of the communication channel connected to the first and second inputs of the element OR, respectively, the output element OR is connected with the input set trigger switching, and the first information input node of the comparison is connected with the information input node disassembly of the communication channel and information input cell switching, the output of the first element And connected to the second information input node of the comparison, tretheway first elements And all cells connected to the switching entrance permit information transfer system A4, each cell switching intermediate cascade additionally contains from the second through fourth elements And the element of the ban And trigger control, and reset inputs of the installation which is connected to the output element of the ban and node disassembly channel cell switching intermediate cascade connection, respectively, and output to the first input of the second element And whose output is connected to the second input of the first element And whose output is combined with the output of the third element And is connected to the second input of the second element And the trigger output switching cell switching intermediate cascade connected to the first input element of the ban, characterized in that each block switching output stage entered M buffer of the storage device, each of which contains a counter and a RAM (random access memory), the output of the counter is connected to the address inputs of RAM, the data input of RAM is connected to the output of the external RAM, the synchronization input of the counter and the input of the chip select CS buffer RAM combined and connected to the output T of the clock generator, the enable input write buffer RAM is connected to the enable input settings p, the first output buffer RAM is connected with the information output of the switching system, introduced M vertical coordinate of the tire, each of which is connected with the input set to require the rd state the corresponding buffer RAM in each switching unit of the output stage is entered M flip-flops with inverted inputs, reset inputs of which are connected with the second output of the corresponding buffer RAM, and the inputs setup triggers in one state United and connected with the output put of the inverter, the input of H0 which is corresponding to the control potential, and outputs the elements And units of the switching output stage, to the input of the search nonblocking communication channels SI which served the appropriate control potential to the remaining inputs of elements And the signal of employment cell, the element M-argument And, the inputs of which are connected to the outputs of the M triggers and the output signal of which is fed into a Central control device for authorizing the issuance of control signals to the respective blocks in a certain time; in each switching unit of the intermediate cascade introduced X elements, the input of which is connected to the output node of the accelerated propagation of employment, and with the reset input of trigger the switching unit of the intermediate cascade, the output of each of the elements And is connected with the input set to trigger the switching unit of the intermediate cascade in one state, to which is fed the control signal H0; in each switching unit in the same cascade introduced R horizontal and y vertical bus, each of R horizontal bus are connected to the outputscell switching, located in the same horizontal row, and with the signROM (read only memory device)that stores the corresponding input number in the switching unit, each of r vertical busbars are connected to the outputscell switching, located in the same vertical row, and with the signitem two-input And connected by its output to the communication line connecting the switching units of the input and intermediate stages, and the input - output ROM that stores the number of the switching block input stage; in each cell switching unit switching output stage introduced two elements of two-input And, one input of the first input element And is supplied to the enable input of the configuration process p appropriate management capacity, and the second input is connected to the inverse output of the trigger switching cell, the output of the first input element And is connected to the input element chetyrehhodovogo And the first input of the second input element And connected to the direct output of the trigger switching cell, the second input is the management capacity at the entrance of the fixing communication channels SI, and outputs the second elements of the two-input And all cells of commutate the output stage, located in the same vertical row are connected with a vertical coordinate bus switching unit output stage, which is connected to the inputa buffer storage device; in each cell of the switching unit of the intermediate cascade has introduced an element of two-input And, one input resolution process settings p which is the appropriate management capacity, the second input is connected to the inverse output trigger control cells, and the output of the input element And is connected to the input node of the comparison cells; each cell unit switching input stage has introduced an element of two-input And, at the synchronization input P2 corresponding to the second palusalu settings, which is the appropriate management capacity, and the second input is connected to the inverse output of the trigger switching cell, the output of the input element And is connected to the input node of the comparison cell signalwith direct trigger output of each switching cell switching input stage is removed and transferred by the horizontal bus of the switching unit in the input stage to the inputsThe ROM stores the number of inputs of the switching block input stage, and vertical tire on inputselements And connected in the second is the od to the ROMs, where is the number of the switching block input stage.