Self-correcting memorizing device

FIELD: computer engineering, possible use in combination devices, and also in devices for storing and transferring information.

SUBSTANCE: device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, inversion block, decoder, corrector.

EFFECT: increased trustworthiness of device operation.

1 dwg, 1 app

 

The invention relates to computer technology and can be used to improve the reliability in the functioning of the combinational devices, as well as the storage and transmission of information (operational and permanent storage of the computer devices and the like).

Known discrete self-correcting device [1], which uses the decoding device correcting unit (byte) of the error based on application of the reed-Solomon codes with the original schema, the encoder, the redundant circuit, a decoding device that includes a circuit calculations syndrome, shaper imaginary syndromes decoder errors in a byte, the scheme of calculation of a malformed byte, switches, errors, offset errors, the input devices are connected to the inputs of the original scheme and to the inputs of encoder outputs encoder devices are connected to the inputs of redundant circuits, the outputs of which are connected to first inputs of the circuit computing the syndrome, the outputs of the original circuit connected to the second inputs of the circuit computing the syndrome and to the first inputs of the offset, the output schema of the calculation of the syndrome are connected to the inputs of decoder errors, the outputs of which are connected to second inputs of the offset, the outputs of the corrector are the outputs of the device.

The disadvantage of this device is the low reliability of funkcionirovanie the device, since reed-Solomon allow you to correct the error in one byte of information, and to detect an error in two bytes.

The closest technical solution is self-correcting discrete device [2], containing the original schema, the first encoder, a diagram of the syndrome of the error, the decoder error corrector, second, third and fourth encoders, the first through fourth convolution scheme, the scheme of the sign of the error, the element OR the input device is connected to a source schema and to the inputs of the first encoding device, to the second inputs of encoder and outputs of the original circuit connected to the inputs of the third and fourth coding device, to the first input of the corrector whose outputs are the outputs of the device, the outputs from the first to the fourth coding devices connected respectively to the inputs of the first through fourth circuits convolution, the outputs of the first and third circuits convolution is connected to the input circuit of the syndrome of the error, the outputs of the second and fourth circuits convolution connected to the inputs of the circuit characteristic of the error, the output circuit of the syndrome of the error and the error indicator connected to the inputs of decoder errors, the first group of outputs of decoder errors connected to the second inputs of the offset, and the second group of outputs connected to the input of the OR element, the output of which is removed signal is "failure".

The disadvantage of this device is the low reliability of operation, so as not corrected errors that occur simultaneously in the information and check bits.

The aim of the invention is to increase the reliability of operation of the device due to the correction of 72% of the detected errors does not exceed the multiplicity k-1, subject to a maximum detection number of errors in the code set.

This objective is achieved in that the device contains the original scheme, the encoder, the scheme of the syndrome of the error, the decoder, the corrector, the information input device connected to the first inputs of the original scheme, the outputs of which are connected to first inputs of the offset, the outputs of the corrector are the outputs of the device, characterized in that it further comprises between the first and fifth elements And, from first to eighth elements OR block inversion, the register, the element does NOT address inputs, input write input read input "Reset", and the information input device connected to the first inputs of the first element And, the address inputs connected to the second inputs of the original circuit and to the first inputs of the register, the input record is connected to the third input of the source schema to the second input of the first element And to the second input register, input reading is connected to the fourth input of the source schema to the first is at the input of the second element, And to the first input of the third element And to the first input of the fourth element And to the third input register, input "Reset" is connected to the fifth input source circuit and to the fourth input of the register, the outputs of the original circuit connected to the second inputs of the second element And whose outputs are connected to first inputs of the first element OR the second input of which is connected to the outputs of the first element, And outputs connected to the inputs of the block inversion and to the first input of the coding device, the outputs of encoder connected to the second inputs of the third element And the fifth inputs of the register, the outputs of the block inversion connected to the second inputs of encoder, the input circuit of error syndromes are connected to the outputs of the third element And the second inputs connected to the outputs of the register, and outputs connected to the inputs of the decoder and to the inputs of the second element OR the output of which is connected to the first input of the fifth element And the first group of outputs of the decoder are connected to the inputs of the third element OR the second group of outputs of the decoder are connected to the inputs of the fourth element, OR the third group of outputs of the decoder are connected to the inputs of the fifth element OR the fourth group of outputs of the decoder are connected to the inputs of the sixth element OR group of outputs of the decoder are connected to the inputs of the seventh element OR outputs with tre is LEGO sixth elements OR connected respectively with the second, fourth and fifth inputs of the fourth element And first to fourth inputs of the eighth element OR the output of the seventh element OR is connected to the fifth input of the eighth element OR the output of which through the element is NOT connected to the second input of the fifth element And the fifth input element And an output device that outputs the fourth element And connected to the second inputs of the offset.

The drawing shows a block diagram of the device. The device includes: a source schema 1, the first element 2 And the second element 3 And the third element 4 And the fourth element 5 And the fifth element 6 And the first element 7 OR the second element 8 OR the third element 9 OR the fourth element 10 OR the fifth element 11 OR the sixth element 12 OR the seventh element 13 OR the eighth element 14 OR the encoder 15, a diagram of the syndrome of the error 16, a decoder 17, the corrector 18, block inversion 19, the register 20, the element 21 is NOT, informational inputs 22, the address input 23 input 24 entries, entry 25 reading input 26 reset, the outputs 27 of the device, the output 28 "Failure".

An information input device 22 is connected to the first inputs of the first element 2 And to the first input source circuit 1, the outputs of which are connected to the first input of the corrector 18, the address input 23 is connected to the second input source circuit 1 and to the first inputs of the register 17, the input 24 of the account connected to the third input source circuit 1 to the second input of the first element 2 And to the second input of the register 20, the input 25 of the reader connected to chetvert is the input source circuit 1, to the first input of the second element 3 And to the first input of the third element 4 And to the first input of the fourth element 5 And to the third input of the register 20, entry 26 "Reset" is connected to the fifth input source circuit 1 and to the fourth input of the register 20, the outputs of the original circuit 1 is connected to the second inputs of the second element 3 And whose outputs are connected to first inputs of the first element 7 OR the second input of which is connected to the outputs of the first element 2, And outputs connected to the inputs of the block inversion 19 and to the first inputs of encoder 15, the outputs of encoder 15 is connected to the second inputs of the third element 4 And to the fifth input of the register 20, the outputs of block 19 of the inversion is connected to the second inputs of encoder 15, the input circuit 16 syndromes errors connected to the outputs of the third element 4 And second inputs connected to the outputs of the register 20, and outputs connected to the inputs of decoder 17 and to the inputs of the second element 8 OR the output of which is connected to the first input of the fifth element 6 And the first group of outputs of the decoder 17 is connected to the inputs of the third element 9 OR the second group of outputs of the decoder 17 is connected to the inputs the fourth element 10 OR the third group of outputs of the decoder 17 is connected to the inputs of the fifth element 11 OR the fourth group of outputs of the decoder 17 is connected to the inputs of the sixth element 12 OR fifth gr is the PAP outputs of the decoder 17 is connected to the inputs of the seventh element 13 OR the outputs from the third 9 on the sixth of 12 items OR connected respectively with the second, fourth and fifth inputs of the fourth element 5 And first to fourth inputs of the eighth element 14 OR the output of the seventh element 13 is connected to the fifth input of the eighth element 14 OR the output of which through the element 21 is NOT connected to the second input of the fifth element 6 And the input of the fifth element 6 And an output device that outputs the fourth element 5 And is connected to the second input of the corrector 18.

Block 19 of the inversion is to invert the values of the information bits of the outputs of the first element 7 OR, respectively, when reading and writing information.

In the encoding device 15, the information bits are represented as two-line information matrix:

where yi,respectively the direct and the inverse of the i-th information bit. Relative to the formed matrix encoding device 15 are the right and left diagonal checks.

The number of diagonal checks (number of control bits) is determined by the formula:

RD=2k+2.

When reading the information coding unit 15 generates (similarly) vector control bits RPadopted code set.

Thus, p is the period of recording and reading information, the output of the coding device 15, are respectively the vectors of control bits:

Scheme 16 syndrome errors represent a bitwise comparison and is designed to generate values of the syndrome of the error based on the transmitted and received information. The result of the addition in mod 2 values of the signals transferred and formed the control bits will give the syndrome of the error:

The decoder 17 contains 2k+2 log (number of bits of the error syndrome) and L=l1+l2+l3outputs (number of schema matching, representing 2k+2-input And schema), where

- l1-group elements And for the various syndromes that characterize the error in the information bits;

- l2-group elements And for the various syndromes that characterize the errors in the check bits;

- l3-group elements And (for syndromes that characterize the errors that occur simultaneously in the information and check bits.

In case of an error on one of its outputs is formed of a single signal.

The outputs of the decoder 17 combined respectively into one output using third element 9 OR the fourth element 10 OR the fifth element 11 OR sixth (k-th) element 12 OR for formation control is their signal to the corrector, accordingly, for the correction of the first, second ...the k-th information bits.

The seventh element 13 OR combines the outputs of the decoder 17 outputs schemes And)belonging to the subset of l2and the corresponding errors only check bits (which do not require the formation of control signals for concealer).

Corrector 18 includes k elements disparities and is designed to repair errorsappearing at the outputs of the original circuit 1. When error correction is implemented function with respect to control signals ui outputs of elements OR:

The register 20 is designed for storage of signal values of the vector control bits generated when recording information in the source scheme 1.

When errors occur, belong to the subset of n1for the same syndromes, indicating an error in a variety of informational bits (having the same value of syndromes and additional checks, see Appendix), characterized by the presence of singular values on the output of the circuit 16 syndromes of errors and the absence of unit values on the outputs from the third 9 on the seventh of 13 items, OR using the second element 8 OR the eighth item 14 OR item 21, the fifth element 6 And is formed with the persecuted "Failure".

The device operates as follows. Before you begin to input 25 signal that sets the device to its original state. When the input information to the information input 22, the address inputs 23 and signal "Write" input 24 information is written to the specified address in the source scheme 1. At the same time she arrives at the inputs of the first element 2 And open the input 24, and then through the element 7 OR the input information is supplied to the first inputs of encoder 15 and the inlet 19 of the inversion. On the second input of the coding device 15 receives the inverse values of the information bits. Of the direct and inverse values of the information bits is formed two-line information matrix, against which in the encoding device 15 based on the group of adders for mod 2, are arranged right and left diagonal checks.

With outputs of encoder 15 is a vector of control bits received at the input of register 20 and written to the specified address.

When reading information on the address signals from the output of the source circuit 1, through the second element 3 And is opened by the signal "Read" input 25, item 7, OR re-fed to the input of the coding device 15, which are formed of the values of signals in the control bits of the formation matrix, formed on the received information.

The information from the outputs of the coding device 15 through the third element 4 And is supplied to the input circuit 16 of the syndrome of the error, on the second input of which receives the information read from the register 20.

Scheme 16 syndrome of the error made on the adders for mod 2 and is intended for bitwise comparison of the values taken control of discharges generated relative to the received information.

As a result, the output of the circuit 16 syndrome errors are generated value of the syndrome of the error.

The decoder 17 when an error generates at one of its outputs a single signal in accordance with the incoming value of the syndrome of the error. Depending on the number of information digits, having an error control signal appears at the output of the corresponding (9...12) OR. This signal through the open fourth element 5 And is fed to the input of the corrector 18, where the correction of erroneous information bits.

If the error occurred only in the control bits of the signal appears at the output of the seventh element (13) OR (not required to apply control signals to the corrector).

The outputs of the decoder 17 combined respectively into one output using third element 9 OR the fourth element 10 OR the fifth element 11 OR sixth (k-what about the element 12 OR to generate control signals for the corrector, accordingly, for the correction of the first, second ...k-ro information bits.

The seventh element 13 OR combines the outputs of the decoder 17, the outputs of circuits And belonging to subset of l2and corresponding errors only check bits (which do not require the formation of control signals for concealer).

Corrector 18 includes k elements disparities and is designed to repair errorsappearing at the outputs of the original circuit 1. When error correction is implemented function with respect to control signals ui outputs of elements OR:

When errors occur, belong to the subset of n1for the same syndromes, indicating an error in a variety of informational bits (having the same value of syndromes and additional checks, see Appendix), characterized by the presence of singular values on the output of the circuit 16 syndromes of errors and the absence of unit values on the outputs from the third 9 on the seventh of 13 items, OR using the second element 8 OR the eighth item 14 OR item 21, the fifth element 6 And a signal is generated "Failure".

Application

Correction of errors of a given multiplicity, provided error detection in other bits of information, m which can be achieved on the basis of the iterative code.

The procedure of constructing a two-dimensional iterative code is as follows [3]. Given a set of information symbols are divided into groups (blocks, modules) information, b-bits in each group. Received information modules are in the form of the information matrix (1):

Next, the encoding information according to the method of parity (by adding on mod 2 characters of rows and columns of the resulting matrix). The result is a two-dimensional iterative code to detect and correct any single error:

where H=h1h2,...,hmthe vector of parity rows; Z=z1,z2,...,zbthe vector of parity columns. Vector parity rows and columns form a set of control bits R1={r1,r2,rm,rm+1,...,rb}. When receiving a code combination regarding information bits of the re-formed values of the control bits={r1,r2,rm,rm+1,...,rb}. In this case, the difference between the transmitted control bits and received after the receipt of the information forms the syndrome of the error E:

When this bit of the syndrome of the error e1e2...em(received regarding the sustained fashion vector parity lines) indicate the module information having an error, and the digits of emem+1...eb(received regarding the vector of parity columns) indicate an erroneous discharge in the module information.

As the code combinations of the rows and columns have minimum distance d=2, then the minimum distance of this code is d=4. This code allows you to correct any single error and detect a significant share of multiple-error.

Patterns of errors not detected two-dimensional iterative code shown:

Figure 1 Patterns of errors not detected two-dimensional iterative code: (a) errors of multiplicity 4; b) errors of multiplicity 6.

Fig.2 the structure of the errors of the two-dimensional iterative code, leading to erroneous correction: (a) the error ratio of 5; (b) error ratio 7.

In the General case, one can construct an iterative codes higher dimensions (three-dimensional, four dimensional, and so on), where each information symbol will be the component simultaneously of two different code words. The parameters of iterative codes the dimension of x as follows [3]:

where ni,kidirespectively the length, the number of information bits, the minimum distance between the code sets of rows and columns.

On this basis, to build an iterative codes the following is the duty to regulate the use of checks, with the highest detection capability.

So, the organization diagonal checks consider the matrix will identify patterns of errors not detected by the iterative code that implements parity rows and columns.

The structure of the diagonal checks that detect considered the error presented on Fig.3.

Fig.3 Structure of diagonal checks:

- results-right diagonal inspections;the results of the left diagonal checks

Left diagonal checks are generated by the rule:

The results of the right diagonal checks are formed by summing the values of the following information categories:

In this case, the total number of diagonal checks equal to 2l, or:

Example 1. Let's consider the word consists of four information bits, which have zero values. For this code set information matrix has the form:

In this case, the parity rows and columns of the information matrix will give a zero value and in addition will have zero values, the results of all the right and left diagonal checks. If an error occurs, all the information bits have odd error not detected two-dimensional iterative code, since parity rows and columns of the information matrix are zero values:

At the same time, right and left diagonal checks will result 101.

Approval 1. Iterative code that implements the right and left of the diagonal scan detect all odd errors not detected two-dimensional iterative code and identifies odd errors, perceived two-dimensional iterative code as corrected.

In turn, there are patterns of errors not detected by the iterative code that implements the right and left diagonal check and parity check rows and columns. Structure of the considered errors are presented in Fig.4.

Fig.4 Structure of errors not detectable diagonal checks and inspections of rows and columns.

For example, regarding the information matrix with zero diagonal checks will not be detected following structure errors.

In order to exclude the appearance of the considered errors, the information matrix should contain no more than two lines.

2 approval. For the information is Noah matrix b× 2 iterative code that implements the right and left of the diagonal scan detect the maximum number of possible errors (except for sets 2k-1 forbidden code sets that can be transformed enabled code sets).

Thus, when using iterative code that implements the right and left diagonal check and parity, code set is transmitted in the form:

For the considered example, the encoding information is as follows:

r1=y1; r2=y2⊕ I3; r3=y4; r4=y3; r5=y1⊕ I4; r6=y2.

The result of the addition of signal values of the control bits sent and received, will give the syndrome of the error:

where the bits of the error vector r1,r2.........rl- match the right diagonal checks, rl,rl+1............r2l- left and formed relative to the received information bits;

values obtained control bits.

Property 1. There are configuration errors in the information and check bits, for which the error syndromes have the same value.

To distinguish between these errors is formirovanii values of the syndromes of errors there are extra diagonal checks:

Thus, each error from a variety of errors M=(2n)k can be put into correspondence with the value of the syndrome of the error and the value of additional diagonal checks.

Property 2. Each set of values of the syndrome and error values for additional inspections corresponds to a subset of the Q-error of different configurations.

Corollary 1. To distinguish between errors that belong to this subset, it is necessary to limit the ratio of corrected errors and to increase the number of control bits (to implement the additional coding information bits).

In this regard, the proposed encoding method includes the following provisions:

1) in order to ensure the correction of 70% of the errors, it will be limited to bug fixes, the multiplicity does not exceed k-1;

2) of the direct inverse values of the information bits of the information matrix is formed:

3) to the obtained information of the matrix are arranged right and left diagonal checks. The number of diagonal checks (number of control bits) is determined by the formula:

4) code set is transmitted in the form:

) the result of addition of values of the signals transferred and formed the control bits will give the syndrome of the error:

6) during the formation of the syndrome of the error relative to the received and generated values of the control bits are organized additional diagonal scan, the number of which is determined by the expression:

7) as a result we have a lot of errors of a given multiplicity (in this case from a single to multiplicity k-1, defined by the expression:characterized by a certain value of the syndrome of the error and additional checks.

8) the set N is divided into four subsets of N=n1+n2+n3+n4where

n1- syndromes that have the same additional checks (unrecoverable error, a sign of failure);

n2- a subset of groups (each group consists of 2k-the same values of the syndromes) in the presence of errors in the information bits;

n3- a subset of groups (each group consists of 2k-the same values of the syndromes) if there are errors only in the control bits;

n4- a subset of groups (each group consists of 2k-the same values of the syndromes) when errors occur simultaneously in the information and check bits.

Note that for errors not exceeding multiplicity k-1, no erroneous code sets, cord is reremix permitted (working) code sets.

On the basis of the received encoding rules formed the decoding strategy that solves the problem of recognizing errors in the information and check bits, and rules for the correction of errors, which includes the following items:

1) revealed the same additional checks, which of the set N is excluded the error syndromes belonging to the subset of n1observed (uncorrected errors in which a signal is generated "Failure");

2) to define groups of similar syndromes (indicating an error in the corresponding information bits) for a subset of n2;

3) define groups of syndromes of errors belonging to the subset of n3that do not require correction of information bits;

4) identify clusters of similar values of the syndromes of errors belonging to the subset of n4and to correct errors in the corresponding information bits.

For this example, implements the proposed encoding method are:

- total number of error - 7504;

- the number of common syndromes of errors, with the same additional checks (a subset of n1) - 2096 (the number of detected errors);

- 5408 - the number of corrected errors (72%);

- the number of errors in the information bits - 224 (l1=14-g is PP, each of which includes 16 of the same syndromes);

- the number of errors in the check bits - 2016 (l2=126-groups, each of which includes 16 of the same syndromes);

- the number of errors that have distortion at the same time in the information and check bits - 3168 (l3=198-groups, each of which includes 16 of the same syndromes).

In table 1 presents the values of the syndromes of error for subsets of n2n3n4, (excluded syndromes errors subset of n1that have the same value additional checks).

The proposed encoding method allows you to:

to correct the error specified ratio;

to find the maximum number of errors (with the exception of the erroneous code sets that can be transformed enabled code sets);

to signal a malfunction of the memory device when the occurrence of the unrecoverable error.

Sources of information

1. Shcherbakov NS Reliability of digital devices. Moscow: Mashinostroenie, 1989, 224 S. 39, is.

2. A positive decision on the application (21)99111190/09 from 15.01.03 (filed 31.05.09), authors: Tsarkov A.N., Kinless BY, Novikov N., Romanenko Y.A., Pavlov A.A.

3. Has had I. A. Rudnev P. improving the reliability of digital devices methods of redundant coding. M: uh who argia, 1974, 270 S.

Self-correcting storage device containing the storage device, encoder, designed to exercise the right and left diagonal checks and forming vector control bits, the syndrome of the error, the decoder, the corrector is designed to correct errors that occur at the outputs of the storage device, the information input device connected to the first inputs of the storage device, the outputs of which are connected to first inputs of the offset, the outputs of the corrector are the outputs of the device, characterized in that it further comprises the first through fourth groups of elements And the fifth element And the first group of elements, OR from second to eighth elements OR block inversion, the register, the element does NOT address inputs, input write input read input "Reset", and information inputs of the storage device connected to the first inputs of elements And the first group of address inputs connected to the second inputs of the storage device and to the first inputs of the register, the input record is connected to the third input of the storage device, to the joint second inputs of elements And the first group and to the second input register, input reading is connected to the fourth input of the storage device, to the United first inputs of the elements of the Second group, to United first inputs of elements And the third group, United to the first input element of the fourth group and to the third input register, input "Reset" is connected to the fifth input of the storage device and to the fourth input of the register, the outputs of the storage device connected to the second inputs of elements And the second group, the outputs are connected to first inputs of elements OR a first group of elements OR, the second inputs of which are connected to the outputs of the elements And the first group, and outputs connected to the inputs of the block inversion and to the first input of the coding device, the outputs of encoder connected to the second inputs of elements And the third group and fifth inputs of the register, the outputs of the block inversion is connected to the second inputs of encoder, the input circuit of the syndrome of the error connected to the outputs of the elements And the third group, the second inputs connected to the outputs of the register, and outputs connected to the inputs of the decoder and to the inputs of the second element OR the output of which is connected to the first input of the fifth element And the first group of outputs of the decoder are connected to the inputs of the third element OR the second group of outputs of the decoder are connected to the inputs of the fourth element, OR the third group of outputs of the decoder are connected to the inputs of the fifth element OR the fourth group of outputs of the decoder are connected to the inputs W the buffer of net element OR the fifth group of outputs of the decoder are connected to the inputs of the seventh element, OR the outputs from the third and sixth elements OR connected respectively to the second inputs of the elements of the fourth group and first to fourth inputs of the eighth element OR the output of the seventh element OR is connected to the fifth input of the eighth element OR the output of which through the element is NOT connected to the second input of the fifth element And the output of the fifth element And is output "Failure", the outputs of the elements And the fourth group is connected to the second inputs of the offset.



 

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FIELD: automatics and computer science, possible use for controlling and correcting errors during relaying of information, and also for performing arithmetical operations by computer.

SUBSTANCE: device has two blocks for calculating error syndrome on basis of control bases, made on two-layer neuron network, register, memory block, output adder, and also due to application of polynomial residuals system, in which as system base, minimal polynomials are used, determined in extended Galois fields GF(2ν) and in terms of neuron network technologies.

EFFECT: decreased dimensions of equipment, higher speed of detection and correction of errors.

3 dwg, 2 tbl

FIELD: computer science.

SUBSTANCE: network has end ring neuron network, Hopfield neuron network, demultiplexer and multiplexer.

EFFECT: broader functional capabilities, higher efficiency, higher speed of operation.

1 dwg

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