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Statistical analyzer of quality and recording of electric power flow

Statistical analyzer of quality and recording of electric power flow
IPC classes for russian patent Statistical analyzer of quality and recording of electric power flow (RU 2260842):

G06F17/18 - for evaluating statistical data
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FIELD: computer science.

SUBSTANCE: device has current input clamp and mating input clamp, current counter with inbuilt pulse sensor, converter of alternating voltage to direct voltage, analog=digital converter, register, digital memory block, pulse counter, selection pulse generator, second and first D-triggers, first, second and third and fourth AND elements, SR-trigger, OR element, clock pulse generator, pulse distributor.

EFFECT: simplified construction, higher reliability, higher efficiency.

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The invention relates to the field of information-measuring and computing techniques and can be used in the power industry to account for the energy consumption in its various quality.

A device for measuring the parameters of voltage quality [1], which contains the measuring bodies, elements of the ban, the elements of the startup time of the device, the electric power meters.

The disadvantages are the counterpart complexity, low reliability, lack of accuracy, large size and weight, due to the fact that his definition block histogram of the deviations of the voltage contains in each channel mechanical timing device, performed on synchronous motors, for counting the number of revolutions which used totalizers from electricity meters, and based on Electromechanical relays launch elements, and each channel for energy consumption based on Electromechanical electricity meters.

The closest technical solution to offer is statistical quality analyzer voltage [2], containing the current input and voltage input, the meter with built-in sensor pulses, the inverter AC voltage to DC, the block defining a histogram of the deviations of the voltage, the group counter pulse is s to account for the energy consumption in different variations of voltage, moreover, the block defining a histogram of the deviations of the voltage contains a pulse generator sampling, n (where n is the number of levels of analysis of variance voltage) elements And n of the pulse counter.

The technical problem solved by the invention is the simplification of the analyzer and increase its reliability.

The mentioned technical problem is solved by the fact that in statistical quality analyzer voltage containing the current input terminal and the input clamp voltage, the inverter AC voltage to DC, the pulse generator sampling/pulse counter, the first to fourth elements And the electricity meter with built-in sensor pulses, a current input and a voltage input which is connected to the corresponding input terminals of the analyzer input clamp voltage connected to the input of the inverter AC voltage to DC, added digital memory block, SR-flip-flop, the first and second D-flip-flops, register, element OR generator of clock pulses, pulse distributor and analog-to-digital Converter, an information input of which is connected to the output of the inverter AC voltage to DC, and the information output is connected with the information input register, the output of which is connected with a group of least significant bits of the address input of the digital memory block and, the output of which is connected to the information input of the pulse counter, the output of which is connected to the information input of the digital memory unit, the output of pulse generator sample is connected to the control input of the write register and a clock input of the first D-trigger information whose input is combined with the information input of the second D-flip-flop and connected to the bus unit capacity, output meter with built-in sensor pulses is connected to a clock input of the second D-flip-flop, the input set of zero which is connected to the output of the second element And the second input is combined with the second input of the fourth element And connected to the inverse output of the SR-trigger direct the output of which is connected with senior level address input of the digital memory block and the joint second inputs of the third and first elements And the yield of the latter is connected to the input of the zero of the first D-flip-direct the output of which is connected to the first input of the third element And whose output is connected to the first input of the OR element, the second input is connected via the fourth element And to direct the output of the second D-flip-flop, and the output element OR is connected to a clock input of the counter pulse, the generator output clock pulses is connected to a clock input of the pulse distributor, the outputs of which connect the ENES, accordingly, the first with a control input record count pulses, the second combined with third inputs of the third and fourth elements, And the third - with the input of the control recording digital memory block and the first combined inputs of the first and second elements And the fourth clock input of the SR flip-flop.

Significant differences of the proposed technical solution is the introduction of new elements in the schema analyzer (digital memory block, SR-flip-flop, first and second D-flip-flops, register, element OR generator of clock pulses, the pulse distributor and analog-to-digital Converter), the organization of the new structure analyzer and the introduction of new relationships between the elements of his scheme; this is a significant decrease in the total number of components of the element base analyzer and reducing the number of connections between the elements. These significant differences achieve a positive effect - simplify and improve the reliability of the analyzer.

The drawing shows a diagram of the analyzer.

The analyzer includes a current input terminal 1 input terminal 2 of the voltage connected to the corresponding inputs of the counter 3 energy (SE) with built-in sensor pulse input terminal 2 of the voltage connected to the input of the inverter 4 AC voltage in p is constant (PNP), the output of which is connected to the information input of the analog-to-digital Converter 5 (ADC), the information output of which is connected to the information input of the register 6, the output of which is connected with a group of least significant bits of the address input of the digital memory block 7 (PPI), the output of which is connected to the information input of the counter 8 pulses (C), the output of which is connected with the information input PPI 7, the pulse generator 9 sample (Gibeah), the output of which is connected to the control input of the write register 6, and a clock input of the first D-flip-flop 10, the information input is combined with the information input of the second D trigger 11 and connected to the bus of a single potential, the output of the solar cell 3 is connected to a clock input of the second D-flip-flop 11, the input set of zero which is connected to the output of the second element And 12, the second input is combined with the second input of the fourth element And 13 and is connected to the inverse output of the SR flip-flop 14, and the outlet of which is connected with senior level address input PPI 7 and the joint second inputs of the third 15 and the first 16 elements And the yield of the latter is connected to the input of the zero of the first D-flip-flop 10, the direct output of which is connected to the first input of the third item And 15, the output of which is connected to the first input of the OR element 17, the second input is connected via the fourth element, And 13 to PR is the MW output of the second D-flip-flop 11, and the output of the OR element 17 is connected to a clock input C 8, the output of the generator 18 clock pulses (GTI) is connected to a clock input of the distributor 19 pulses (RI), the outputs of which are connected, respectively, with the control input record C 8, the second combined with third inputs of the third 15 and 13 fourth elements And the third with the control input record PPI 7 and the first combined inputs of the first 16 and second 12 elements And the fourth clock input of the SR flip-flop 14.

In the pulp and paper industry 7 analyzer collects information to build a histogram of the deviations of the voltage and energy consumption corresponding to each discharge histogram: 1) in the cells of the pulp and paper industry 7 addresses 10000-11111 stored information to build the histogram; 2) in the cells of the pulp and paper industry 7 addresses 00000-01111 stored data on energy consumption.

The boundaries of the digits of the histogram are set by the ADC 5 - in this example, the number of digits of the histogram 16 and they can be measured 4-bit ADC 5.

The frequency of the output rectangular voltage pulses ke3 proportional to the power consumption of the controlled network.

Used in the analyzer Gibeah 9 is quartz, its frequency can be set equal to 1 Hz.

The frequency of the GIT 18 may be unstable and is set in the range from 1 kHz to 10 MHz.

In PNP 4 [3, 4] ASU is coming selection of curve AC voltage u(t) low-frequency component deviations δ Ut(t) effective voltage value

where U(t) is the effective value of the voltage at the current time t;

Un(t) - rated voltage value.

The voltage U4output PNP 4 is supplied to the information input ADC 5 and converts them into binary code, for example, 0010.

This code is applied to the group of least significant bits of the address input PPI 7.

Coming every second output DIED 9 pulses carry the i-th sample variance of the voltage at which the first D-flip-flop 10 fit the unit in the register 6 is the code from the ADC output 5 (in this example code 0010).

Coming from the variable frequency output from the solar cell 3 pulses translate the second D-flip-flop 11 in one state when the count of each j-quantum the energy consumed.

Frequency GTI 18 by 3-5 orders of magnitude higher than the frequency of the pulses KILLED 9 and ke3. The pulses from the output of the GTI 18 is fed to the input RI 19, the outputs of which continuously scan control signals. SR-flip-flop 14 at the end of each cycle RI 19 changes its state to the opposite, promoting alternate order of removal of information from the first 10 and second 11 D-triggers.

Consider next cycle RI 19.

Appearing on the first output RI 19 pulse enters from the cell PPI 7 address 10010 (when a single state is Sri SR-flip-flop 14) C 8 information, n 2(i-1)accumulated in the previous statistical analysis of the variations of voltage in the discharge of the histogram number 0010.

The pulse from the second output RI 19 strobilus elements 13 and 15. In the case before this cycle RI 19 was another sample variance of the voltage, the D-flip-flop 10 is in a single state. When the pulse from the second output RI 19 passes sequentially through the elements And 15 OR 17 on the clock input C 8, increasing its content of n2(i-1)

per unit, which equals

The pulse from the third output RI 19, passing through the element And 16 is set to the zero state of the D-flip-flop 10, as well as acting on the control input record CPD 7, returns to his cell with the address 10010 increased per unit information, n2i.

The momentum from the fourth output RI 19 SR-flip-flop 14 is turned over to the zero state.

Appearing in the next cycle of operation on the first output ri 19 pulse enters from the cell PPI 7 address 00010 (SR-flip-flop 14 is now in the zero state) in C 8 m2(j-1), which accumulated in the previous energy consumption when the deviation voltage corresponding to the discharge histogram number 0010.

The pulse from the second output RI 19 strobiles element And 13. In that case, the AE, if before this cycle RI 19 at the outlet ke3 appeared the next pulse, the D-flip-flop 11 is in a single state. When the pulse from the second output RU 19 passes sequentially through the elements And 13 OR 17 on the clock input C 8, increasing its content of m2(j-1)per unit, which equals

The pulse from the third output RI 19, passing through the element And 12 is set to the zero state of the D-flip-flop 11 and acting on the control input record CPD 7, returns to his cell with the address 00010 increased by one m2j.

The momentum from the fourth output RI 19 SR-flip-flop 14 is tilted towards one state, etc.

In those cycles RI 19, in which D-triggers 10 and 11 are in the zero state, the pulses from the third output RI 19 in the corresponding cells in the pulp and paper industry 7 C 8 the following information is returned nkior mkj(where k is the code on the output of the ADC 5, corresponding to the number of discharge histogram) unchanged, i.e. without increasing per unit.

After completion of the measurements, which extend the time T (day, week, month), the contents of the cells in the pulp and paper industry 7 addresses 10000-11111 construct a histogram of the deviations of the voltage δUtthe ordinate of each k-th digit of which is determined by the formula

where nk- the content is imoe k-th cell PPI 7 in the 10000-11111;

N is the total contents of the cells of the pulp and paper industry 7 addresses 10000-11111;

T - measurement time expressed in seconds.

f9- frequency Gibeah 9.

The contents of the cells in the pulp and paper industry 7 addresses 00000-01111 is determined by the number released to the consumer of electricity, corresponding to each k-th rank histogram of the deviations of the voltage

where C3- price output pulse SE 3, kW*h/pulse;

mk- the contents of the k-th cell PPI 7 in the 00000-01111.

On the total content of cells PPI 7 addresses 00000-01111 may be determined by the total amount of electric power W is released to the consumer for the time dimension T, and the amount of electric power W consumed by the consumer if permitted by GOST 13109-97 the variations of voltage and WND- when an invalid voltage deviations.

After measurements are completed by the histogram is checked if the deviations of the mains voltage to the standards of GOST, and by the values of WDand WNDcalculation of value of consumed energy consumer.

Advantages of the proposed analyzer in comparison with the known are simpler and more robust scheme, smaller size and weight. Diagram of the analyzer can be performed on integrated circuits domestic production.

The source of the information

1. Litvak V., Prokopchik CENTURY Way of measuring quality parameters voltage //proceedings of the Tomsk Polytechnic Institute. - 1973. - So 202. - P.21-23.

2. A.S. 1073777 the USSR, MKI G 06 F 15/36. Statistical quality analyzer voltage /Vthermal and Vindicitive. - 1984, bull. N 6 (prototype).

3. Ermakov V.F., Hamalis AI high speed inverter AC voltage to DC, " Izv. higher education institutions. Electromechanics. - 1989. - N 11. - P.64-67.

4. Ermakov V.F., Kushnaryov F.A., Prize M.V., Prokopenko A.G., Reshetnikov, Y.M., Semykin C.V., Fedorov B.C. Interfaces AC voltage microelectronic devices of relay protection, automation and control and measuring devices //proceedings of the II between Nar. nauch.-the practical. proc. "Computer technology in science, industry, social and economic processes", Novocherkassk, November 25, 2001: 6 piece /s.-Grew up with. state technology. University (NPI). - Novocherkassk: NPO "TEMP", 2001. - 6 o'clock. - P.45-47.

Statistical quality analyzer and energy consumption, containing the current input terminal and the input clamp voltage, the inverter AC voltage to DC, the pulse generator sampling pulse counter, the first to fourth elements And the electricity meter with built-in sensor pulses, a current input and a voltage input which is connected to the corresponding input terminals on the analysis of the Torah, input clamp voltage connected to the input of the inverter AC voltage to DC, characterized in that it additionally introduced digital memory block, SR-flip-flop, the first and second D-flip-flops, register, element OR generator of clock pulses, the pulse distributor and analog-to-digital Converter, an information input of which is connected to the output of the inverter AC voltage to DC, and the information output is connected with the information input register, the output of which is connected with a group of least significant bits of the address input of the digital memory unit, the output of which is connected to the information input of the pulse counter, the output of which is connected to the information the input of the digital memory unit, the output of pulse generator sample is connected to the control input of the write register and a clock input of the first D-trigger information whose input is combined with the information input of the second D-flip-flop and connected to the bus unit capacity, output meter with built-in sensor pulses is connected to a clock input of the second D-flip-flop, the input set of zero which is connected to the output of the second element And the second input is combined with the second input of the fourth element And connected to the inverse output of the SR flip-flop, a direct output of which is connected with a hundred the PWM discharge address input digital memory block and the joint second inputs of the third and first elements, And the yield of the latter is connected to the input of the zero of the first D-flip-direct the output of which is connected to the first input of the third element And whose output is connected to the first input of the OR element, the second input is via the fourth element And connected to the direct output of the second D-flip-flop, and the output element OR is connected to a clock input of the counter pulse, the generator output clock pulses is connected to a clock input of the pulse distributor, the outputs of which are connected respectively to the first with a control input record count pulses, the second combined with third inputs of the third and fourth elements And the third with control input record digital memory block and the first combined inputs of the first and second elements And the fourth clock input of the SR flip-flop.

 

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