Device for measuring two-dimensional distributions of random processes
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 Device for measuring distributions of random processes / 2249851Device has ADC, address multiplexer, memory block, combination adder, division block, counts number counter, control block, quality control block, indication block. |
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Device for measuring distributions of random processes / 2249851 Device has ADC, address multiplexer, memory block, combination adder, division block, counts number counter, control block, quality control block, indication block. |
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Device for determining characteristics of a random process / 2253147 Device has buffer memory register, pulse generator, switches, register, commutators, pulse counter, inversions number counter, comparison circuit, AND elements group, subtraction elements group, scale amplifiers group, adders group, delay elements groups, delay elements, cycles counter, OR elements group, reverse value computation blocks group, square-ware generators group. |
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 Probability device / 2276402Probability device contains indicator of random series 1, block for forming non-integer indicator values 2, correction block 3, block for forming values of matrix 4, control block 5, threshold devices block 6, block for forming indicator values 7, clock pulses generator 8, DENY element 9, AND elements block 10, memory block 11, decoder 12, time setting block 13, OR element 14, block 15 for increasing trustworthiness. Device makes it possible to model controllable semi-markov circuits with high trustworthiness with consideration of controlling effects, and dynamically changes threshold values of states, set both numerically and qualitatively, and untrustworthily, due to serial comparison of source data, received as binary code; taking of decision is possible about their mathematical nature and also transformation of source data in block 15, given in incorrect manner, to form, useable for parametric modeling procedure realization. |
 Device for parametric estimation of message streams distribution law / 2279125Device for parametric estimation of message streams distribution law contains: input amplifier, parameters computation block, average arithmetic values computation block, block for determining distribution type, distribution computing device, control block, intensiveness analysis block, block for analyzing trustworthiness of messages. Thus, it is possible to estimate parameters of distribution of homogeneous and heterogeneous streams of multi-packet messages with high trustworthiness, specific signs of pauses for which may be identified both quantitatively and qualitatively - untrustworthily, due to comparative analysis in block of bit series received in binary code from position of their match to signs of pauses and mathematically correct transformation, on basis of neuron networks theory, of untrustworthily identified signs of pauses to form, useable for performing procedure of parametric estimation of message streams distribution law. |
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FIELD: computer science.
SUBSTANCE: device has ADC, address multiplexer, adder, AND element, OR element, two memory blocks, quality control block, division block, indication block, count number counter, reverse counter, control block, quality control block.
EFFECT: measurement of two-dimensional distribution of random process with given quality in minimal time due to quality control during measurement of distribution and finish of measurement, if quality criterion is lower than preset value.
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The inventive device refers to information-measuring and computing and can be used to measure two-dimensional probability density functions, random processes.
A device for three-dimensional analysis of random processes (ed. St. USSR № 417791, IPC 6 G 06 F 17/18, 1974)containing analog-to-digital Converter and the processing unit density probability distribution that contains a block of memory and an adder.
The drawbacks are the lack of quality control measurements and the inability to specify a time offset.
A device for determining the laws of probability distributions of random processes (ed. St. USSR № 834709, IPC 6 G 06 F 17/18, 1981), containing analog-to-digital Converter, a counter of the number of samples and display unit.
The drawbacks - the lack of quality control measurements, sequential measurement of two-dimensional distribution of the random process, the inability to specify a time offset and a fixed number of samples of a random process.
Known multi-channel statistical analyzer (ed. St. USSR № 1215119, IPC 6 G 06 F 17/18, 1986) for measuring two-dimensional distributions of random processes containing analog-to-digital Converter, the multiplexer address counter of the number of counts, the counter, egistr, the control unit and computer unit includes a memory unit and an adder.
The disadvantages of this analyzer are the lack of quality control measurements, sequential measurement of two-dimensional distribution of the random process and a fixed number of samples of a random process.
Known two-dimensional statistical analyzer level and the derived voltage (RF patent No. 2053550, IPC6G 06 F 17/18, 1996) for measuring two-dimensional distribution level and the derived voltage containing analog-to-digital Converter, a register, a reversible counter, counter and block the accumulation of two-dimensional distribution, which includes an adder and a memory block.
The disadvantage of the analyzer is the lack of quality control measurements.
Known taken as a prototype device for determining two-dimensional probability density of the random process (ed. St. USSR № 1698897, IPC6G 06 F 17/18, 1991), containing analog-to-digital Converter, the information input by the information input device, and the output is connected to the information input of the second memory block, the first memory block, the multiplexer address register, the count counts a clock input which is combined with the input of the start of analog-to-digital Converter, a reversible counter, element “And And”, element “And”, the adder and the unit.
The prototype disadvantages are the need for multiple measurements to obtain the result, inability to obtain two-dimensional distribution of a random process with a given time-shift, a fixed number of samples of a random process, the criterion for the end of the measurement does not allow to minimize the measurement time, satisfying the criterion of completion of the measurement leads to the change of the time difference, the criterion for the end of the measurement is not checked in the process of measuring two-dimensional distribution of the random process.
The task, which directed the inventive device is measuring two-dimensional distribution of a random process with a given value for the minimum time due to quality control in the process of measuring two-dimensional distribution of the random process and the completion of the measurement, if the quality criterion is below the specified value.
This problem is solved due to the fact that in a device containing an analog-to-digital Converter, the information input by the information input device, and the output is connected to the information input of the second memory block, the first memory block, the multiplexer address register, the count counts a clock input which is combined with the input of the start of analog-the number of the Converter, reversible counter, element “OR”element “And”, the adder unit, unlike the prototype, introduced additional control unit, a display unit, a counter unit quality control information input unit quality control coupled to the output unit and the second information input of the display unit, the first information input of which is connected to 2k younger bits of the output count of the number of counts, the clock input of which is combined with subtractive input of the reversible counter and is connected to the first output control unit, the first input which is the input “start” device, the output the quality testing unit connected to the second input of the control unit and to the fourth input of the display unit, the input clocking of which are combined with the input clocking unit quality control and is connected to the third output of the control unit, the second output of which is connected to the control input of the multiplexer address, the output of the analog-to-digital Converter connected with the older bits of the first data input of multiplexer address, the output of which is connected to the address input of the first memory block, the output of which is connected to the first information input of the adder and to the input of the fissionable unit, to the input of the divider which is connected to the output count of the number of samples, information wholersale memory block is connected to the output of the adder, on the second information input of which is filed with the unit, the output of the second memory block is connected to the low bits of the first data input of multiplexer address, the second information input of which is connected to 2k younger bits of the output count of the number of samples, the address input of the second memory block is connected to the output of the reversible counter, the output of “Less than zero” which is connected to the enable input parallel load reversible counter and to the first input element “OR”, the output of which is connected to the clock input of the counter, the first discharge outlet of which is connected to a second input element “OR” and with the first input element And whose output is connected to the input of the read/write of the first memory block, the input parallel load reversible counter connected to the output of the register, the input of which is the input of the Shift device, the input to the read/write of the second memory block is connected to the fifth output control unit, the fourth output of which is connected with the second input element And the input of the start of analog-to-digital Converter connected to the first output of the control unit.
These additional blocks and connections allow us to monitor quality and to minimize the time measuring two-dimensional distribution of the random process.
Figure 1 shows the structural scheme is and devices figure 2 shows a block diagram of the control unit.
The device (see figure 1) contains an analog-to-digital Converter (ADC) 1, the information input by the information input device, and the output is connected to the older bits of the first information input of the multiplexer 2 address and with the information input of the second block 3 of memory. The output of the multiplexer 2 addresses connected to the address input of the first block 4 memory, the output of which is connected to the first information input of the adder 5, the output of which is connected to the information input of the first block 4 memory. On the second information input of the adder 5 filed unit. Low-order bits of the first information input of the multiplexer 2 addresses connected to the output of the second block 3 memory address input of which is connected to the output of the reversible counter 6. Input parallel load reversible counter 6 is connected to the output of the register 7, the inlet of which is the entrance of “Shift” device. The release of “Less than zero” reversible counter 6 is connected to the enable input parallel load reversible counter 6 and to the first input element “OR” 8. The second input element “OR” 8 connected to the first discharge output of the counter 9. The clock input of the counter 9 is connected to the output element OR 8. The first bit output of the counter 9 is connected to the first input element “And”10, the output of which is connected to the input of read/write of the first block 4 memory. The output of the counter 11 of counts connected to the input of the divider block 12 division, the log dividend which is connected to the output of the first block 4 memory. Junior 2k bits from the output of the counter 11 of counts connected to the second information input of the multiplexer 2 and addresses to the first information input unit 13 of the display. The output of block 12 division connected with the second information input unit 13 of the display and information input unit 14 quality control, the output of which is connected to the second input of the control unit 15 and to the fourth input unit 13 of the display. The first input of the control unit 15 is input “start” device. The first output control unit 15 is connected to the input of the start-ADC 1, input subtracting the reversible counter 6 and a clock input of the counter 11 number of samples. The second output of the control unit 15 is connected to the control input of the multiplexer 2 addresses. The third output of the control unit 15 is connected to the clocking inputs of the block 14 quality control unit 13 of the display. The fourth output control unit 15 is connected with the second input element “And” 10. The fifth output control unit 15 is connected to the input of the read/write of the second block 3 of memory.
The control unit 15 may be implemented as shown in figure 2. It contains the generator 16 clock pulses is law, the output of which is connected to the first input element And 17, a second input connected to the direct output of the RS flip-flop 18. The input set of a single state of the RS-flip-flop 18 is the input “start” device. Input zero-state RS-flip-flop 18 is the second input of the control unit 15. The output element And 17 is connected to a clock input of the counter 19, the output of which is connected to the address input of the random-access memory (ROM) 20. The outputs of the ROM 20 are outputs 1-5 unit 15 of the control.
The device operates as follows.
In the initial state (chain-set the initial state is not shown) in all cell blocks 3 and 4 of the memory contains zeros, the reversible counter 6, the counter 9 and the counter 11 of counts set to zero. In case 7 the recorded code T time shift τ. The outputs of the control unit 15 are zero signal levels. Blocks 12 division 13 display 14 quality control prepared for reading out the information.
On a start signal at the first input of the control unit 15 at its first output pulse appears, which starts ADC 1, the output of “Less than zero” reversible counter 6 receives the impulse, recording in the reversible counter 6 code T time shift τ from the register 7 and increasing per unit content of the counter 9. The pulse at the first output unit 15, the management is of the contents of the counter 11 number count is incremented.
ADC 1 discrete transforms a realization of a random process in binary code, the number of digits k which specifies the number of intervals N for each of the dimensions of the two-dimensional histogram:
The value of the lower significant bit ADC 1 defines the width of the interval grouping of the two-dimensional histogram. The triggering frequency of the ADC 1 is set by the control unit 15 determines the sampling rate of the random process in time and frequency range analyzed realizations of a random process.
In register 7 stores the code of the T time shift τ between the analyzed samples of the random process, expressed in number of samples between them.
Reversible counter 6 specifies the address of the cell of the second block 3 of memory. During operation of the device is reversible counter 6 is rotated from T to 0. Upon reaching the contents of the reversible counter 6 zero value of the next counting pulse from the first output of the control unit 15 causes the output of “Less than zero” reversible counter 6 pulse that writes in the reversible counter 6 is So
In the second unit 3 are stored in the memory counts that define the second dimension of the two-dimensional histogram of the random process. In place of reference, used for p the structure of a two-dimensional histogram, writes a new reference.
The counter 9 counts the number of downloads reversible counter 6 and when it becomes equal to two, through the element “And” 10 enables the first block 4 memory in which is stored a two-dimensional histogram of the random process. When the accumulation in the counter 9 number 2 his work is blocked by a single value of the first digit from the output of the counter 9 is supplied to the second input element “OR” 8.
The prohibition of using counter 9 and item “And” 10 forming a two-dimensional histogram in the first block 4 memory is necessary in order for the first T+2 counts realization of the random process was the formation of two-dimensional histograms, because there is no reference to the second dimension of the two-dimensional histogram.
The counter 11 number count counts the number of samples of the random process used to build a two-dimensional histogram.
The number of cells of the first block 4 memory used to store two-dimensional histogram of the random process is equal to N2or 2k2.
Then on the second output unit 15 of the control unit appears level and the multiplexer 2 addresses skips to the output information of the second information inputs. The contents of the cell of the first block 4 memory, the address of which is set 2k least significant bit of the mi counter 11 number of samples, fed to the input of the dividend unit 12 division. Then in block 12 is calculated dividing chastoty Pijcolumn two-dimensional histogram in accordance with the expression
where mij- the number of samples of the random process belonging to a corresponding interval grouping of the two-dimensional histogram, the contents of the cell of the first block 4 memory;
i,j - the numbers that define the interval grouping of the two-dimensional histogram respectively for the first and second dimensions of the two-dimensional histogram;
n is the total number of samples of the random process, as counted by the counter 11 number of samples.
Next on pulse to the third output unit 15 controls a particular value of Pijcolumn two-dimensional histogram and the code for this column is read unit 13 of the display. Unit 14 quality control reads chastoty Pijcolumn two-dimensional histogram.
Periodically, after the cycle of reading the values of the relative Rijcolumns two-dimensional histogram, that is, after you change the code 2k least significant bits of the counter 11 of counts from 0 to N2-1 or after receipt of the N2pulsing pulses to the input unit 14 quality control they calculated the quality criterion of measuring two-dimensional distribution of the random process and, if its value IU is the more specified 3-5 cycles of the read two-dimensional histogram, is issued to signal the end of the measurement in units of 15 management and 13 of the display. The first cycle of the read values of the particular Rijcolumns two-dimensional histogram consists of N2-1 pulsing pulse (read columns from 1 to N2-1, because after the first run ADC 1 counter 11 number of samples takes a single value and it is not used to calculate the criterion of quality.
The quality criterion of measuring two-dimensional distribution of the random process can be, for example, standard deviation σ changes in particular Rijcolumns two-dimensional histogram:
where N2- the number of columns of the two-dimensional histogram;
ΔPijn=Pijn-Pij(n-1)the difference chastoty ij-th column of a two-dimensional histogram of n and (n-1)-th cycles of the read two-dimensional histogram;
Pijn- chastoty ij-th column of a two-dimensional histogram for n-th cycle of reading a two-dimensional histogram;
Pij(n-1)- chastoty ij-th column of a two-dimensional histogram with (n-1)-th cycle of reading a two-dimensional histogram.
If the standard deviation σ changes in particular Rijcolumns two-dimensional histogram does not exceed the preassigned values of 3-5 cycles of the read two-dimensional histogram, block 14 quality control is issued to signal the end of the measurement. P is this signal the control unit 15 stops working unit 13 of the display indicates the end of a measurement.
Simultaneously with the pulse at the second output unit 15 of the management at its second output is zero and the multiplexer 2 address transmits output information with its first data input. The contents of the cell of the first block 4 memory high-order bits of the addresses which are specified by a code from the ADC output 1, and the youngest - code output of the second block 3 of memory is supplied to the first information input of the adder 5 and increases by one, then the pulse at the fourth output control unit 15, the new value is written to the first block 4 memory at the same address.
Code ADC output 1 specifies the first dimension of a two-dimensional histogram, and the code output of the second unit 3 memory - second.
Then on impulse at the fifth output unit 15 of the control code from the ADC output 1 is written into the cell of the second block 3 of memory, the address of which is set reversible counter 6.
Then again pulse appears at the first output control unit 15 and the described process is repeated.
Thus, for measuring two-dimensional distribution of the random process is controlled by the build quality of the two-dimensional distribution of the random process and, upon reaching a given quality, a signal is generated measurement is finished. For a given quality time measurement the Oia will be minimal. Data is continuously displayed by the display unit.
If necessary, read the two-dimensional histogram other computing facilities code values and a particular column of a two-dimensional histogram can be obtained from the information input unit 13 of the display. The signal clocking the read two-dimensional histograms can be obtained from the third output unit 15 of the control.
Unit 13 unit can be implemented as described in the patent of the Russian Federation No. 2130199, IPC6G 06 F 17/18, 1999 Unit 13 of the display contains the decoder of binary code in a unitary position code elements “OR NOT”, registers, encoders, indicators.
Unit 14 quality control can be performed based on the on-chip microcomputers. The information input unit is the first port on-chip microcomputers, the input clocking block is connected to the interrupt input of the microcomputer, and the output is zero bit of the second port of the microcomputer. Programming and design of devices with the use of microcomputers outlined in the Handbook: on-Chip microcomputers: a Guide / Boborykin A.V. and others - M.: MIKAP, 1994. - 400 C. the Scheme of inclusion of microcomputers in the same figure 2.12, page 143.
1. Device for measuring two-dimensional distributions of random processes containing analog-to-digital Converter, an information input which has the information input device, and the output is connected to the information input of the second memory block, the first memory block, the multiplexer address register, the count counts a clock input which is combined with the input of the start of analog-to-digital Converter, a reversible counter, element, OR element, And the adder unit, characterized in that it additionally introduced a control unit, a display unit, a counter, a quality testing unit that is designed to compare the values of the changes in distribution of random processes and signal measurement is finished when the preset value, the data input unit quality control coupled to the output unit, and with the second information input of the display unit, the first information input of which is connected to 2k younger bits of the output count of the number of counts, the clock input of which is combined with subtractive input of the reversible counter and is connected to the first output control unit, the first input which is the input of the start device, the output quality testing unit connected to the second input of the control unit and to the fourth input of the display unit, the input clocking of which are combined with the input clocking unit quality control and is connected to the third output of the control unit, the second output of which is connected to the control input of the multiplexer hell is ena, the output of the analog-to-digital Converter connected with the older bits of the first data input of multiplexer address, the output of which is connected to the address input of the first memory block, the output of which is connected to the first information input of the adder and to the input of the fissionable unit, to the input of the divider which is connected to the output count of the number of samples, the information input of the first memory block is connected to the output of the adder, the second information input of which is filed with the unit, the output of the second memory block is connected to the low bits of the first data input of multiplexer address, the second information input of which is connected to 2k younger bits of the output count of the number of samples, the address input of the second memory block connected to the output of the reversible counter, the output of "Less than zero" which is connected to the enable input parallel load reversible counter and to the first input of the OR element, the output of which is connected to the clock input of the counter, the first discharge outlet of which is connected to the second input of the OR element and to the first input element And the output of which is connected to the input of read/write of the first memory block, the input parallel load reversible counter connected to the output of the register, the input of which is the input of the Shift device, the input to the read/write of the second memory block under the offline to the fifth output control unit, the fourth output of which is connected with the second input element And the input of the start of analog-to-digital Converter connected to the first output of the control unit.
2. The device according to claim 1, characterized in that the control unit comprises a generator of clock pulses, And RS-flip-flop, a counter, a persistent storage device, the generator output clock pulses connected to the first input element And to the second input of which is connected to the direct output of the RS flip-flop input set a single state which is the first input of the control unit, the input to the zero-state RS-flip-flop is the second input of the control unit, the output element And is connected to a clock input of the counter, the output of which is connected to the address input of a permanent storage device whose outputs are the outputs of the block control.