Device for measuring distributions of random processes. RU patent 2249851.
 Device for measuring distributions of random processes / 2249851Device has ADC, address multiplexer, memory block, combination adder, division block, counts number counter, control block, quality control block, indication block. |
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 Device for parametric estimation of message streams distribution law / 2279125Device for parametric estimation of message streams distribution law contains: input amplifier, parameters computation block, average arithmetic values computation block, block for determining distribution type, distribution computing device, control block, intensiveness analysis block, block for analyzing trustworthiness of messages. Thus, it is possible to estimate parameters of distribution of homogeneous and heterogeneous streams of multi-packet messages with high trustworthiness, specific signs of pauses for which may be identified both quantitatively and qualitatively - untrustworthily, due to comparative analysis in block of bit series received in binary code from position of their match to signs of pauses and mathematically correct transformation, on basis of neuron networks theory, of untrustworthily identified signs of pauses to form, useable for performing procedure of parametric estimation of message streams distribution law. |
 Device for parametric estimation of partition law of message streams / 2281548Device for parametric estimation of message streams partition law contains input amplifier, parameters calculation block, block for calculation of average arithmetic values, block for determining type of partition, calculator of partition, control block, intensiveness analysis block, packet sign analysis block, block for transformation of type of packet sign, thus making it possible to estimate parameters of partition of homogeneous and non-homogeneous (mixed) streams of multi-packet messages with high trustworthiness, distinguishing marks of which packets (signs of beginning and end of information part of packets) may be identified both quantitatively and qualitatively - ambiguously, in uncertain manner, with utilization of linguistic variable, due to comparing analysis in block of incoming bit series for matching with signs of packets, appropriate for implemented exchange protocol and taking a decision about logic-mathematical nature of their identification attributes, which is mathematically correct, on basis of methods of theory of fuzzy sets, transformation in block of source data, characterizing signs of packets and identified in fuzzy form as type, useable for parametric estimation of message streams partition law. |
FIELD: computers.
SUBSTANCE: device has ADC, address multiplexer, memory block, combination adder, division block, counts number counter, control block, quality control block, indication block.
EFFECT: higher efficiency.
2 cl, 2 dwg
The inventive device refers to information-measuring and computing and can be used to measure the probability density functions of stochastic processes.
A device for analysis of the distributions of random processes (ed. St. USSR №830399, IPC 6 G 06 F 17/18, 1981), containing analog-to-digital Converter, a memory unit, a combinational adder and a control unit.
A device for analyzing the distribution of the random process (ed. St. USSR №1095191, IPC 6 G 06 F 17/18, 1984), containing analog-to-digital Converter, the multiplexer address, the memory block count of number of times, the unit and the adder.
A device for analysis of the distributions of random processes (ed. St. USSR №1164734, IPC 6 G 06 F 17/18, 1985), containing analog-to-digital Converter, a counter of the number of samples, the multiplexer addresses, memory unit, control unit and combinational adder.
A well-known statistical analyzer deviations of the mains voltage (ABT. St. USSR №1262524, IPC 6 G About F 17/18, 1986) to measure the distributions of random processes containing analog-to-digital Converter, the multiplexer address, a memory unit, a display unit and an adder.
A device for monitoring and statistical analysis of the variations of voltage (RF patent No. 2130199, IPC 6 G 06 F 17/18, 1999), involved the measurement of the distributions of random processes containing analog-to-digital Converter, the multiplexer address, a memory unit, a display unit and an adder.
The disadvantage of these devices is the lack of quality control measurements.
Known taken as a prototype device for the analysis of the distributions of random processes (ed. St. USSR №1226487, IPC 6 G 06 F 17/18, 1986), containing analog-to-digital Converter, the information input by the information input device and an output connected to the second information input of the multiplexer address, the output of which is connected to the address input of the memory block, the output of which is connected to the input of the combinational adder, a counter of the number of samples, the control unit, the first input which is the input “start” device, the first output control unit connected to the input of the start of analog-to-digital Converter, and a display unit.
The disadvantage of the prototype is the lack of control over the quality of the distribution of the random process and a great time of measurement. To build the distribution you are using a fixed number of samples of the random process. During operation of the device the results are not checked for compliance with quality criteria.
The challenge which seeks the proposed device is the measurement of the distribution of the random process is given as the minimum time at the expense of quality control in the process of measuring the distribution of the random process and the completion of the measurement, if the quality criterion below a preset value.
This problem is solved due to the fact that in a device containing an analog-to-digital Converter, the information input by the information input device and an output connected to the second information input of the multiplexer address, the output of which is connected to the address input of the memory block,
the output of which is connected to the input of the combinational adder, a counter of the number of samples, the control unit, the first input which is the input “start” device, the first output control unit connected to the input of the start of analog-to-digital Converter, a display unit, unlike the prototype, introduced additional unit, the input of the divider which is connected to the output count of the number of counts, the clock input of which is combined with the input of the start of analog-to-digital Converter and connected to the first output control unit, the input of the fissionable unit is connected to the output of the memory unit and to the input of the combinational adder, the output of which is connected to the information the input of the memory block, the k least significant bits from the output count of the number of counts connected with the first information input of the multiplexer address, the control input of which is connected to the second output of the control unit, quality testing unit, an information input connected to the output unit and the second information input of the display unit, the first information input of which is connected with Junior k-bit output count of the number of samples, the clocking inputs of quality control and indication unit of the joint and is connected to the fourth output control unit, quality testing unit connected to the second input of the control unit and the fourth input of the display unit, the input reading/write memory block is connected to the fifth output control unit, a third output of which is connected to the input clocking block division.,
These additional blocks and connections allow us to monitor quality and to minimize the measurement time distribution of a random process.
Figure 1 shows the block diagram of the device, figure 2 shows a diagram of the control unit.
The device (see figure 1) contains an analog-to-digital Converter (ADC) 1, the information input by the information input device and an output connected to the second information input of the multiplexer 2 addresses. The output of the multiplexer 2 addresses connected to the address input unit 3 to the memory, the output of which is connected to the input of the combinational adder 4, the output of which is connected with the information input unit 3 memory.
The output of the counter 5 counts connected to the input of the divider block 6 division entrance dividend which is connected to the output of block 3 of memory. The output of block 6 division connected to the information input unit 7 quality control. The first output of the control unit 8 is connected to the input of the start ADC 1 and the clock input of the counter 5 counts, the second output of the control unit 8 is connected with the control input of the multiplexer 2 addresses. The third output of the control unit 8 is connected to the input clocking unit 6 division, the fourth output control unit 8 is connected to the clocking inputs of the block 7 quality control and block 9 display, the fifth output control unit 8 is connected to the input of the read/write unit 3 memory. The first input of the control unit 8 is input “start” device. The output unit 7 quality control is connected to the second input of the control unit 8 and the fourth input unit 9 display. Junior k bits from the output of the counter 5 counts connected to the first information input unit 9 display and to the first information input of the multiplexer 2 addresses. The second information input unit 9 display coupled to the output unit 6 division.
Unit 7 quality control can be performed based on the on-chip microcomputers. The information input unit is the first port on-chip microcomputers, the input clocking block is connected to the interrupt input of the microcomputer, and the output is zero bit of the second port of the microcomputer. Programming and design of devices with the use of microcomputers outlined in the Handbook: on-Chip microcomputers: a Guide / Boborykin A.V. and others - M.: MIKAP, 1994. - 400 S.: ill. The circuit of the micro-computer in the same figure 2.12, page 143.
The control unit 8 may be implemented as shown in figure 2. It contains the generator 10 clock pulses, RS-flip-flop 11, and the outlet of which is connected to the second input element And 12, the first input connected to the output of the generator 10 clock pulses. The input set of a single state of the RS-flip-flop 11 is the input “start” device.
Input zero-state RS-flip-flop 11 is the second input of the control unit 8. The output element And 12 is connected to the clock input of the counter 13, the output of which is connected to the address input of the random-access memory (ROM) 14. The outputs of the ROM 14 are outputs 1-5 unit 8 controls.
The implementation of block 9 of the display shown in the patent of Russian Federation №2130199, IPC 6 G 06 F 17/18, 1999 figure 3. Block 9 of the display contains the decoder of binary code in a unitary position code elements OR NOT, registers, encoders, indicators.
The device operates as follows.
In the initial state (chain-set the initial state is not shown) to each cell block 3 of memory contains a zero, the counter 5 counts reset to zero. The outputs of the control unit 8 are zero signal levels. Unit 7 quality control prepared for information readout.
On a start signal at the first input of the control unit 8 at its first output pulse appears, which starts the ADC 1 and the content of the counter 5 counts incremented.
ADC 1 converts the realization of a random process in binary code, the number of digits which k specifies the number of intervals N of the measured histogram:
The value of the lower significant bit ADC 1 defines the width of the interval grouping of the histogram. The triggering frequency of the ADC 1 determines the sampling rate of the random process in time and frequency range analyzed the realization of a random process.
The counter 5 counts counts the number of samples of the random process used to build the histogram.
Then on the second output unit 8 of the control unit appears level and the multiplexer 2 addresses skips to the output information from your first data entry. The contents of the cell block 3 of memory, the address of which is set Junior k-bit counter 5 number of samples received at the input of the dividend unit 6 division. Then the pulse at the second output unit 8 of the control unit 6 is calculated dividing chastoty R i column histogram in accordance with the expression
where m is the number of samples of the random process belonging to a corresponding interval grouping of the histogram, the contents of the cell block 3 memory;
n is the total number of samples of the random process, as counted by the counter 5 counts.
Next on pulse to the fourth output unit 8 controls a particular value R of the first column of the histogram and the code for this column is read in block 9 of the display unit 7 quality control reads chastoty R i column of the histogram.
Periodically, after the cycle of reading the values of the relative R i columns of the histogram, that is, after you change the code k least significant bits of the counter 5 counts from 0 to N-1 or after receipt N pulsing pulses to the input of block 7 quality control they calculated the quality criterion to measure the distribution of a random process and, if its value is less than the specified 3-5 cycles to read the histogram, is issued to signal the end of the measurement in units of 8 control and 9 display. The first cycle of the read values relative R i columns of the histogram consists of N-1 pulsing pulse (read columns 1 through N-1, because after the first run ADC 1 counter 5 counts accepts a single value and it is not used for the calculation of the quality criterion.
The quality criterion to measure the distribution of the random process can be, for example, standard deviation σ changes relative R i columns of the histogram
where N is the number of columns of the histogram;
ΔP in =P in-P i(n-i) - difference between chastoty i-th column of the histogram n and (n-1)-th cycles to read the histogram;
P in - chastoty i-th column of the histogram for n-th cycle of reading of the histogram;
P i(n-i) - chastoty i-th column of the histogram at (n-1)-th cycle of reading the histogram.
If the standard deviation σ changes relative R i columns of the histogram does not exceed the preassigned values of 3-5 cycles to read the histogram, block 7 quality control is issued to signal the end of the measurement. On this signal the control unit 8 stops, unit 9 displays the current histogram and signals the end of the measurement.
Simultaneously with the pulse at the fourth output of the control unit 8 at its second output is zero and the multiplexer 2 addresses skips to the output information from his second information inputs. The contents of the cell block 3 of memory, the address of which is indicated by a code ADC output 1 comes in combinational adder and incremented, then the pulse at the fifth output unit 8 controls the new value is written to block 3 memory at the same address.
Then again pulse appears at the first output of the control unit 8, and the described process is repeated.
Thus, during the measurement of the distribution of the random process is controlled by the build quality of the distribution of the random process and, upon reaching a given quality, a signal is generated measurement is finished. For a given quality time measurement is minimal. Data is continuously displayed by the display unit.
If necessary, read the other histogram computing means code values and a particular column of the histogram can be obtained from the information input unit 9 display. The clocking signal read histograms can be obtained from the fourth output of the control unit 8.
1. Device for measuring distributions of random processes containing analog-to-digital Converter, the information input by the information input device and an output connected to the second information input of the multiplexer address, the output of which is connected to the address input of the memory block, the output of which is connected to the input of the combinational adder, a counter of the number of counts, the display unit, the control unit,
which contains a generator of clock pulses, the element And whose output is connected to a clock input of the counter, RS-trigger input set a single state which is the first input of the control unit and the input of the start device, the first output control unit connected to the input of the start of analog-to-digital Converter, characterized in that it contains a unit, the input of the divider which is connected to the output count of the number of counts, the clock input of which is combined with the input of the start of analog-to-digital Converter and connected to the first output control unit, the input of the fissionable unit is connected to the output of the memory block and to the input of the combinational adder, the output of which is connected to the information input of the memory block, the k least significant bits from the output count of the number of counts connected with the first information input of the multiplexer address, the control input of which is connected to the second output of the control unit, quality testing unit that is designed to compare the values of the changes in distribution of random processes and signal measurement is finished when the preset value, an information input connected to the output unit and the second information input of the display unit, the first information input of which is connected with Junior k-bit output count of the number of samples, the clocking inputs of quality control and the display unit of the joint and is connected to the fourth output control unit, quality testing unit connected to the second input of the control unit and the fourth input of the display unit,
input read/write memory block is connected to the fifth output control unit, a third output of which is connected to the input clocking block division., 2. The device according to claim 1, characterized in that the control unit includes a persistent storage device, an address input of which is connected to the output of the counter, the output of the generator of clock pulses connected to the first input element And to the second input of which is connected direct RS-flip-flop, the input to the zero state which is the second input of the control unit, outputs a persistent storage device are outputs of the control unit.