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Caching runtime generated code Invention relates to runtime generated code. A program entity that generates code but does not alter global state is identified. Code produced by the identified program entity can be assigned an identifier and cached the first time it is executed. Subsequent executions of the program entity can allow generation of the code and/or translation of the generated code into native binary code. The runtime generated code and native binary code can be cached in a machine-wide cache, or can be added to the metadata of the assembly generated from the source code of the program entity. |
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Microprocessor core memory subsystem Memory subsystem which is connected to a central processing unit, a system controller, external memory and which includes cache memory, a set of data and instruction buffers, consisting of a stored data buffer, a write-back buffer, a downloaded data buffer, wherein the memory subsystem has additional stored data buffers, wherein the cache memory is two-layered, the first layer being connected to the central processing unit, the second-layer cache memory and the write-back buffer, and the second layer is connected to stored data buffers, the downloaded data buffer and the write-back buffer, wherein the buffer for stored data falling in the second-layer cache memory has parity bits for noiseless coding and is connected to the write-back buffer. |
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Apparatus for buffering data streams read from ram Apparatus for buffering data streams transferred between two interfaces which are RAM and CPU data buses, respectively, and having a buffer which is based on memory or registers and accumulates data for transmission thereof upon request from a second interface without accessing the first interface, wherein the apparatus has additional buffers, a tag controller and an output multiplexer, the tag controller being connected to a multiplexer, a buffer based on memory or registers and additional buffers for tracking relevancy of data stored therein, and buffer inputs of the apparatus are connected to RAM. |
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Method of executing an expanded instruction in a system with a rename table, a free list, and a constituent instruction rename table comprising converting the expanded instruction into a plurality of separately executable constituent instructions including a first constituent instruction and a second constituent instruction; assigning a physical register number associated with a physical register to the first constituent instruction by mapping an identifier of the first constituent instruction to the physical register number in the constituent instruction rename table, wherein the first constituent instruction generates an intermediate result; and associating the assigned physical register number with the second constituent instruction receiving the intermediate result. |
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Cleaning of segmented conveyor for wrongly predicted transitions Processor conveyor is segmented into an upper part, prior to commands that follow not in a program order, and one or more lower parts downstream the upper part. The upper conveyor is cleaned after detection of the fact that the transition command was wrongly predicted, minimising delay in selection of commands from a target address of the right transition. Lower conveyors may continue execution until the command of the wrongly predicted transition is confirmed, besides, at this moment of time all non-fixed commands are cleaned from the lower conveyors. Existing mechanisms of conveyor cleaning elimination may be used with the help of adding the identifier of the wrongly predicted transition, at the same time complexity and cost of hardware for lower conveyors cleaning are less. |
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Instruction and logical circuit to carry out dot product operation System to carry out dot product operation includes the following: the first memory device designed to store instruction of a dot product of "single instruction - multiple data flows" type (SIMD); a processor connected to the first memory device to execute instruction of SIMD dot product, in which instructions of SIMD dot product include an indicator of source operand, an indicator of target operand, at least one indicator of direct value, at the same time the direct value indicator includes multiple control bits. |
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Delay in launching certain applications can enhance overall system performance. Applications which must be delayed may be placed in a container object or packaging to that they can be monitored and so that other applications, which depend on the delayed applications, can be processed appropriately. |
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Methods and apparatus for emulating branch prediction behaviour of explicit subroutine call Apparatus has a first input which is configured to receive an instruction address, and a second input which is configured to receive predecoded information which describes the instruction address as being related to an implicit subroutine call in a subroutine. In response to the predecoded information, the apparatus also includes an adder configured to add a constant to the instruction address defining a return address, causing the return address to be stored to an explicit subroutine resource, thus, facilitating subsequent branch prediction of a return call instruction. |
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Pre-decoding variable length instructions Method involves the following: identification of a property of a first instruction, where the property differs from other properties encoded in a first set of pre-decoding bits, for which all available encodings are defined or reserved; coding the first instruction in a second format, whose length differs from that of the first format, including part of the first instruction and the first set of pre-decoding bits, where the second format contains part of the second instruction and a second set of pre-decoding bits, encoding the second set of pre-decoding bits using one of the available encodings. |
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Expansion of stacked register file using shadow registers Method of managing shadow register file system involves the following steps: allocating one or more multi-port registers from a physical register file to a first procedure, corresponding to part of the logic stack of registers, storing data associated with the first procedure in the allocated multi-port registers; selectively saving data associated with the first procedure from one or more multi-port registers to one or more registers of the first file of shadow registers of the shadow register file system, wherein one or more registers has independent data reading/recording ports, and freeing up corresponding allocated multi-port registers for allocating the second procedure; storing data associated with the first procedure from the first shadow register file to the second shadow register file; storing at least part of data associated with the first procedure from a specific register of the second shadow register file in backing memory, and then extraction of said part of data associated with the first procedure from the backing memory to a specific register of the second shadow register file; extracting data from the second shadow register file into one or more registers of the first shadow register file; and before continuing to execute the first procedure, retrieving data associated with the first procedure from one or more registers into one or more multi-port registers, and reallocating the first procedure one or more multi-port registers. |
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Methods and device for ensuring correct pre-decoding Method involves defining a granule which is equal to the smallest length instruction in the instruction set and defining the number of granules making up the longest length instruction in the instruction denoted MAX. The method also involves determining the end of an embedded data segment, when a program is compiled or assembled into the instruction string and inserting a padding of length MAX-1 into the instruction string to the end of the embedded data. Upon pre-decoding of the padded instruction string, a pre-decoder maintains synchronisation with the instructions in the padded instruction string even if embedded data are randomly encoded to resemble an existing instruction in the variable length instruction set. |
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Error handling for early decoding through branch correction Invention relates to processors with pipeline architecture. The method of correcting an incorrectly early decoded instruction comprises stages on which: the early decoding error is detected and a procedure is called for correcting branching with a destination address for the incorrectly early decoded instruction in response to detection of the said error. The early decoded instruction is evaluated as an instruction, which corresponds to incorrectly predicted branching. |
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Present invention relates to computer engineering and can be used in signal processing systems. The device contains an instruction buffer, memory control unit, second level cache memory, integral arithmetic-logic unit (ALU), floating point arithmetic unit and a system controller. |
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Processing of message digest generation commands Command of message digest generation is selected from memory, in response to selection of message digest generation command from memory on the basis of previously specified code of function, operation of message digest generation, which is subject to execution, is determined, at that previously specified code of function defines operation of message digest calculation or operation of function request, if determined operation of message digest generation subject to execution is operation of message digest calculation, in respect to operand, operation of message digest calculation is executed, which contains algorithm of hash coding, if determined operation of message digest generation subject to execution is operation of function request, bits of condition word are stored in block of parameters that correspond to one or several codes of function installed in processor. |
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Present invention pertains to digital signal processors with configurable multiplier-accumulation units and arithmetic-logical units. The device has a first multiplier-accumulation unit for receiving and multiplying the first and second operands, storage of the obtained result in the first intermediate register, adding it to the third operand, a second multiplier-accumulation unit, for receiving and multiplying the fourth and fifth operands, storage of the obtained result in the second intermediate register, adding the sixth operand or with the stored second intermediate result, or with the sum of the stored first and second intermediate results. Multiplier-accumulation units react on the processor instructions for dynamic reconfiguration between the first configuration, in which the first and second multiplier-accumulation units operate independently, and the second configuration, in which the first and second multiplier-accumulation units are connected and operate together. |
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Processing of message authentication control commands providing for data security Invention pertains to the means of providing for computer architecture. Description is given of the method, system and the computer program for computing the data authentication code. The data are stored in the memory of the computing medium. The memory unit required for computing the authentication code is given through commands. During the computing operation the processor defines one of the encoding methods, which is subject to implementation during computation of the authentication code. |
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Method and device for shuffling data In accordance to shuffling instruction, first operand is received, which contains a set of L data elements, and second operand, which contains a set of L shuffling masks, where each shuffling mask includes a "reset to zero" field and selection field, for each shuffling mask, if the "reset to zero" field of shuffling mask is not set, then data indicated by shuffling mask selection field are moved, from data element of first operand, into associated data element of result, and if "reset to zero" field of shuffling mask is set, then zero is placed in associated data element of result. |
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Expandable communication control means Expandable communication control means is used for maintaining communication between computing device and remote communication device. In a computer program adapted for using expandable communication control means, information about contacting side is found, and on basis of found contact information it is determined which types of transactions may be used for communication with contacting side at remote communication device. As soon as communication setup function is determined using contacting side information, communication setup request, associated with such a function, is dispatched to communication address. After receipt, expandable communication control means begins conduction of communication with remote communication device. |
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Device consists of two computing device units, each of them divided into at least four subunits, which consist of a quantity of unit cells. Named units are spatially located so that the distance between unit cell of first unit and equal unit cell in the second unit is minimal. Computing device configuration can be changed using configurational switches, which are installed between device subunits. |
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Method for processing with use of one commands stream and multiple data streams System is disclosed with command (ADD8TO16), which decompresses non-adjacent parts of data word with utilization of signed or zero expansion and combines them by means of arithmetic operation "one command stream, multiple data streams", such as adding, performed in response to one and the same command. Command is especially useful for utilization in systems having a data channel, containing a shifting circuit before the arithmetic circuit. |
Another patent 2513052.