 |
First component code is decoded from information bits and first check bits; the information part of the code word is then selected and depending on the code word syndrome value, a rigid decision is taken for bits from the information part or said information part is interleaved and a second component code is decoded from the interleaved information part and second check bits, after which the information part of the code word is selected and second interleaving is performed, which is inverse to the first interleaving law, and depending of the code word syndrome value, a rigid decision is taken for bits from the information part or the information part is sent for generating the first component code, after which the entire cycle is repeated once more, wherein before the first interleaving, depending on the code word syndrome value, "cycling" situations are detected and eliminated in the first component code, which is decoded once more, and after decoding the second component code, depending on the code word syndrome value, "cycling" situations are detected and eliminated in the second component code, which is decoded once more or second interleaving is performed. |
 |
Method and apparatus for decoding low-density generator matrix code Invention relates to a method of decoding low-density generator matrix codes (LDGC). The method of decoding involves adding L-K known filling bits into a received sequence R of code words and deleting code word symbols deleted in the channel from that sequence R to obtain Re. Rows corresponding to code word symbols deleted in the channel are also deleted from the matrix Gidgct obtained by transposing the LDGC generator matrix to obtain a matrix Ge. Transposition of columns of the matrix Ge is then performed in order to generate a matrix where A is a lower triangular square matrix of the order M, and D B record the transposition of columns corresponding to the relationship between Ge and Ga. Gaussian elimination is performed on matrix Ga to generate a matrix G* in which the first L rows make up an identity matrix, and transposition and summation operations are simultaneously performed on corresponding elements Re in accordance with operations for transposing and summation of rows in the Gaussian elimination in order to generate Re. I't is then obtained from the relationship Gb ∗I't = R'e and inversion is carried out in I't to obtain O't; st is obtained from GIdgct(0:L-1.0; L-1)O't=st and L-K known filling bits are deleted from st to obtain K information sequence bits. |
 |
Invention relates to a communication system using Low-Density Parity-Check (LDPC) codes and particularly apparatus and method for channel encoding/decoding in order to generate LDPC codes with different lengths of the codeword and different coding speeds from the LDPC code, given in higher-order modulation. In the encoding method, the modulation scheme for transmitting symbols is determined; the shortening pattern is determined based on the determined modulation scheme; columns corresponding to the information word in the parity-check matrix of the LDPC code are grouped into a plurality of column groups; the column groups are ordered; the range of the resultant word, which is desirably obtained by shortening the information word, is determined; based on the range of the resultant information word, group after group in the ordered column groups of the information word are shortened according to the shortening pattern; and LDPC encoding is performed over the shortened information word. |
 |
Invention relates to a method and apparatus for transmitting control information in a wireless communication system using a low-density parity-check code (LDPC). The number of LDPC blocks, through which posteriori overhead L1 must be transmitted, is determined according to the total number of bits of the posteriori overhead L1. The number of input data bits of each LDPC block is calculated when the defined number of LDPC blocks is more than one. The number of decimation bits from parity bits of each LDPC block is determined based on the modulation order. The frame, which includes one or more LDPC blocks, formed during the previous steps, is transmitted. |
 |
Channel encoding method in a communication system involves determining the number parity bits for deletion; separating parity bits through predetermined intervals and determining the number of deleted parity bits which are deleted in said predetermined intervals; determining the modulation scheme; determining positions of the deleted parity bits corresponding to said determined number of deleted bits in said predetermined intervals according to the modulation scheme; performing multiple deletions of the deleted parity bits corresponding to said determined positions in said predetermined intervals; and transmitting the rest of the bits, except the deleted bits, according to the modulation scheme. |
 |
Apparatus and method for encoding a channel in a communication system using a low-density parity-check (LDPC) code are disclosed. Parameters for developing the LDPC code are determined and a first parity-check matrix of a quasi-cyclic LDPC code is generated in accordance with said determined parameters. A second parity-check matrix is generated by deleting a predetermined portion of the parity part in the first parity-check matrix and a third party-check matrix is generated by reordering the second parity-check matrix. |
 |
Coding and decoding of ldpc packages of variable sizes FIELD: communications. SUBSTANCE: method for support of coding and decoding the low density parity checking (LDPC). According to the one aspect, coding and decoding of LDPC packages of variable sizes may be supported using the set of basic parity checking matrixes of different size and the sets of lifting value that are equal to the different power of number 2. Basic matrix G of parity checking sized mBxnB can be used for coding the package out of kB=nB-mB information bits to get code word out of nB bits of code. This basic matrix for parity checking can be “lifted” by lifting value L to get lifted parity checking matrix H sized L*mBxL*nB. The lifted parity checking matrix can be used for coding of the package if up to L*kB information bits to get code word of L*nB code bits. Wide range of package size can be supporting using the sets of basic parity checking matrixes and lifting values sets. EFFECT: provision for effective coding and decoding of LDPC packages of variable sizes. 15 cl, 15 dwg |
 |
In the method, the number of parity bits subject to deletion is determined; the parity bits are divided into predetermined intervals and the number of deleted bits, which are subject to deletion in these predetermined intervals, is determined; positions of the deleted parity bits corresponding to the specified number of deleted bits are determined; deletion is repeatedly applied to said deleted parity bits corresponding to said determined positions in said predetermined intervals. Said predetermined intervals are defined by dividing the length of parity bits into a length of one group of columns in a parity check matrix. |
 |
Method and apparatus for encoding low-density generator matrix code Method involves the following steps: S102, constructing a generator matrix Gidgc of L rows and N+L-K columns, where the square matrix Gidgc (1:L, 1:L) of L rows and first L columns of the given matrix is an upper or lower triangular matrix, K, L, N are positive whole numbers and K<L<N; S104 adding L-K known slack bits into the sequence of information bits of length K requiring encoding, generating a sequence of information bits m of length L; S106, in accordance with the equation Gidgc (1:L, 1:L)=m, using the square matrix Gidgc (1:L, 1:L) of L rows and first L columns of this matrix, and the sequence of information bits m of length L, a temporary variable I is generated, while for C=I × Gidgc, the temporary variable I is encoded using the matrix Gidgc, an encoded sequence of length N+L-K is generated; S108, the L-K added known slack bits are removed from the encoded sequence of length N+L-K, an encoded sequence of length N is then generated. |
 |
Disclosed is a novel structure of irregular LDPC codes, which enables to obtain several of codes with different length from a single prototype code with a parity check matrix, given as H=[Hz Hi], where Hz defines a well-known pattern of the corresponding Tanner graph. The parity check matrices for longer codes are obtained as [Hz' "П" diag(Hi,…,Hi), where Hz' defines a longer zigzag pattern depending on the number of used matrices Hi and "П" represents a certain permutation. |
 |
Invention relates to a mobile communication system and is meant for coding/decoding block codes for low density parity check (LDPC) with variable block length. The device and procedure involve reception of data words and coding the data words in the LDPC block code in accordance with the first or second parity check matrix depending on the length used for generating data words in the LDPC block code. |
 |
Device and method for block code encoding with low density of parity control (LDPC-code) featuring variable coding rate. The device receives data word and encodes data word into block LDPC-code on the basis of one of two matrices - the first parity control matrix and the second parity control matrix - depending on coding rate to be used in transforming data word into block LDPC-code. |
 |
Device and method for coding and decoding of block code of low density parity check Invention is related to device and method for coding of block code of low density parity check (LDPC). Substance of invention consists in the fact that during reception of information word vector coder codes vector of information word into block code of LDPC in compliance with preset generating matrix. Modulator modulates block code LDPC into modulation symbol using preset modulation pattern. Transmitter sends modulation symbol. |
 |
Device and method of encoding/decoding discharged even-parity check with variable block length Proposed device and method involve reception of a data word and encoding the data word into a LDPC block structured code based on one of the first even-parity check matrices and a second even-parity checking matrix depending on the length, which should be used when encoding the data word into a LDPC block structured code. |
 |
Decoding of highly excessive code with parity check, using multithreshold message transfer Multithreshold circuit for iterative decoding of accepted highly-excessive code word with parity check includes comparison of updated bit safety to threshold of accepted code word recovery. In each iteration, bit safety and recovered code word based on comparison involving threshold updated for this iteration are updated. Invention embodiment versions involve methods of decoding and/or relevant coding and device using threshold taking two or more values during iterative coding. |
 |
Method and apparatus for error code correction The method of ECC comprises a first directional first decoding, a first directional second decoding, a second directional first decoding, a second directional second decoding, wherein the error tolerant ability of first directional second decoding is greater than the second directional first decoding's. The ECC method comprises the following steps: read a data to be decoded; and if there exists at least one solution cannot be efficiently solved after continuous executing the first directional first decoding and the second directional second decoding, and execute the decoding action in the ECC decoding of the present invention according to a predetermined flow control rule, if there exists no correction performed during the ECC decoding and switch to the other directional decoding, the un-modified value is added by one; and if the un-modified value reached a maximum un-modified value, an ECC failure is confirmed and then stop the ECC decoding. |
 |
In the encoding device, first LDPC encoder generates first LDPC component code in accordance with received information bits, interleaving device interleaves information bits in accordance with given interleaving rule, second LDPC encoder generates second LDPC component code in accordance with interleaved information bits, controller executes control operation in such a way, that information bits, first LDPC component code, which represents first even parity check bits, matching information bits, and second LDPC component code, which represents second even parity check bits, matching information bits, are all combined according to given code speed. |
 |
Method for encoding sparse parity control code Proposed method for encoding sparse parity control code formed from information-section matrix and from parity-section matrix includes steps of information-section matrix conversion into array code structure and assignment of exponent sequences to each column of sub-matrix; extension of two-diagonal matrix corresponding to parity-section matrix so that amount of displacement between diagonals were of random value; enhancement of normalized two-diagonal matrix; evaluation of degree of displacement for cyclic shift of columns in each sub-matrix of higher normalized two-diagonal matrix; and definition of parity symbol corresponding to column in parity control matrix. |
 |
Device contains original circuit, four groups of AND elements, group of OR elements, encoding device, folding circuit, register, error syndrome circuit, checks circuit, three decoders, corrector. |
 |
Fault-tolerant memorizing device Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector. |
 |
Fault-tolerant information storage device Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, inversion block, decoder, even parity check circuit, corrector. |
 |
Device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, corrector. |
 |
Self-correcting memorizing device Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, inversion block, decoder, corrector. |
 |
Device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, even parity check circuit, corrector. |
 |
Self-correcting information storage device Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector. |
 |
Device contains original circuit, four groups of AND elements, group of OR elements, encoding device, register, error syndrome circuit, checks circuit, three decoders, corrector. |
 |
Device contains original circuit, three groups of AND elements, AND element, group of OR elements, OR element, encoding device, register, error syndrome circuit, checks circuit, three decoders. |
Another patent 2513080.