RussianPatents.com
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Coding and decoding of ldpc packages of variable sizes. RU patent 2443053. |
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FIELD: communications. SUBSTANCE: method for support of coding and decoding the low density parity checking (LDPC). According to the one aspect, coding and decoding of LDPC packages of variable sizes may be supported using the set of basic parity checking matrixes of different size and the sets of lifting value that are equal to the different power of number 2. Basic matrix G of parity checking sized mBxnB can be used for coding the package out of kB=nB-mB information bits to get code word out of nB bits of code. This basic matrix for parity checking can be “lifted” by lifting value L to get lifted parity checking matrix H sized L*mBxL*nB. The lifted parity checking matrix can be used for coding of the package if up to L*kB information bits to get code word of L*nB code bits. Wide range of package size can be supporting using the sets of basic parity checking matrixes and lifting values sets. EFFECT: provision for effective coding and decoding of LDPC packages of variable sizes. 15 cl, 15 dwg
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Method and apparatus for channel encoding and decoding in communication system using low-density parity check codes / 2439793 In the method, the number of parity bits subject to deletion is determined; the parity bits are divided into predetermined intervals and the number of deleted bits, which are subject to deletion in these predetermined intervals, is determined; positions of the deleted parity bits corresponding to the specified number of deleted bits are determined; deletion is repeatedly applied to said deleted parity bits corresponding to said determined positions in said predetermined intervals. Said predetermined intervals are defined by dividing the length of parity bits into a length of one group of columns in a parity check matrix. |
Method and apparatus for encoding low-density generator matrix code / 2439792 Method involves the following steps: S102, constructing a generator matrix Gidgc of L rows and N+L-K columns, where the square matrix Gidgc (1:L, 1:L) of L rows and first L columns of the given matrix is an upper or lower triangular matrix, K, L, N are positive whole numbers and K<L<N; S104 adding L-K known slack bits into the sequence of information bits of length K requiring encoding, generating a sequence of information bits m of length L; S106, in accordance with the equation Gidgc (1:L, 1:L)=m, using the square matrix Gidgc (1:L, 1:L) of L rows and first L columns of this matrix, and the sequence of information bits m of length L, a temporary variable I is generated, while for C=I × Gidgc, the temporary variable I is encoded using the matrix Gidgc, an encoded sequence of length N+L-K is generated; S108, the L-K added known slack bits are removed from the encoded sequence of length N+L-K, an encoded sequence of length N is then generated. |
Method for encoding data message for transmission from transmitting station to receiving station and decoding method, transmitting station, receiving station and software / 2438236 Disclosed is a novel structure of irregular LDPC codes, which enables to obtain several of codes with different length from a single prototype code with a parity check matrix, given as H=[Hz Hi], where Hz defines a well-known pattern of the corresponding Tanner graph. The parity check matrices for longer codes are obtained as [Hz' "П" diag(Hi,…,Hi), where Hz' defines a longer zigzag pattern depending on the number of used matrices Hi and "П" represents a certain permutation. |
Device and method for coding/decoding block code for low density parity check with variable block length / 2369008 Invention relates to a mobile communication system and is meant for coding/decoding block codes for low density parity check (LDPC) with variable block length. The device and procedure involve reception of data words and coding the data words in the LDPC block code in accordance with the first or second parity check matrix depending on the length used for generating data words in the LDPC block code. |
Device and method for encoding and decoding block codes with low density of parity control with variable coding rate / 2354045 Device and method for block code encoding with low density of parity control (LDPC-code) featuring variable coding rate. The device receives data word and encodes data word into block LDPC-code on the basis of one of two matrices - the first parity control matrix and the second parity control matrix - depending on coding rate to be used in transforming data word into block LDPC-code. |
Device and method for coding and decoding of block code of low density parity check / 2348103 Invention is related to device and method for coding of block code of low density parity check (LDPC). Substance of invention consists in the fact that during reception of information word vector coder codes vector of information word into block code of LDPC in compliance with preset generating matrix. Modulator modulates block code LDPC into modulation symbol using preset modulation pattern. Transmitter sends modulation symbol. |
Device and method of encoding/decoding discharged even-parity check with variable block length / 2341894 Proposed device and method involve reception of a data word and encoding the data word into a LDPC block structured code based on one of the first even-parity check matrices and a second even-parity checking matrix depending on the length, which should be used when encoding the data word into a LDPC block structured code. |
Decoding of highly excessive code with parity check, using multithreshold message transfer / 2337478 Multithreshold circuit for iterative decoding of accepted highly-excessive code word with parity check includes comparison of updated bit safety to threshold of accepted code word recovery. In each iteration, bit safety and recovered code word based on comparison involving threshold updated for this iteration are updated. Invention embodiment versions involve methods of decoding and/or relevant coding and device using threshold taking two or more values during iterative coding. |
Method and apparatus for error code correction / 2318294 The method of ECC comprises a first directional first decoding, a first directional second decoding, a second directional first decoding, a second directional second decoding, wherein the error tolerant ability of first directional second decoding is greater than the second directional first decoding's. The ECC method comprises the following steps: read a data to be decoded; and if there exists at least one solution cannot be efficiently solved after continuous executing the first directional first decoding and the second directional second decoding, and execute the decoding action in the ECC decoding of the present invention according to a predetermined flow control rule, if there exists no correction performed during the ECC decoding and switch to the other directional decoding, the un-modified value is added by one; and if the un-modified value reached a maximum un-modified value, an ECC failure is confirmed and then stop the ECC decoding. |
Device and method for encoding/decoding a channel with usage of parallel cascade even parity check code with low density / 2310274 In the encoding device, first LDPC encoder generates first LDPC component code in accordance with received information bits, interleaving device interleaves information bits in accordance with given interleaving rule, second LDPC encoder generates second LDPC component code in accordance with interleaved information bits, controller executes control operation in such a way, that information bits, first LDPC component code, which represents first even parity check bits, matching information bits, and second LDPC component code, which represents second even parity check bits, matching information bits, are all combined according to given code speed. |
Self-controlled device / 2297028 Device contains original circuit, three groups of AND elements, AND element, group of OR elements, OR element, encoding device, register, error syndrome circuit, checks circuit, three decoders. |
Self-correcting device / 2297029 Device contains original circuit, four groups of AND elements, group of OR elements, encoding device, register, error syndrome circuit, checks circuit, three decoders, corrector. |
Self-correcting information storage device / 2297030 Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector. |
Fault-tolerant device / 2297031 Device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, even parity check circuit, corrector. |
Self-correcting memorizing device / 2297032 Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, inversion block, decoder, corrector. |
Self-correcting device / 2297033 Device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, corrector. |
Fault-tolerant information storage device / 2297034 Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, inversion block, decoder, even parity check circuit, corrector. |
Fault-tolerant memorizing device / 2297035 Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector. |
Fault-tolerant device / 2297036 Device contains original circuit, four groups of AND elements, group of OR elements, encoding device, folding circuit, register, error syndrome circuit, checks circuit, three decoders, corrector. |
Method for encoding sparse parity control code / 2308803 Proposed method for encoding sparse parity control code formed from information-section matrix and from parity-section matrix includes steps of information-section matrix conversion into array code structure and assignment of exponent sequences to each column of sub-matrix; extension of two-diagonal matrix corresponding to parity-section matrix so that amount of displacement between diagonals were of random value; enhancement of normalized two-diagonal matrix; evaluation of degree of displacement for cyclic shift of columns in each sub-matrix of higher normalized two-diagonal matrix; and definition of parity symbol corresponding to column in parity control matrix. |
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