RussianPatents.com
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Method for encoding sparse parity control code. RU patent 2308803. |
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FIELD: data encoding methods. SUBSTANCE: proposed method for encoding sparse parity control code formed from information-section matrix and from parity-section matrix includes steps of information-section matrix conversion into array code structure and assignment of exponent sequences to each column of sub-matrix; extension of two-diagonal matrix corresponding to parity-section matrix so that amount of displacement between diagonals were of random value; enhancement of normalized two-diagonal matrix; evaluation of degree of displacement for cyclic shift of columns in each sub-matrix of higher normalized two-diagonal matrix; and definition of parity symbol corresponding to column in parity control matrix. EFFECT: enhanced encoding efficiency. 9 cl, 25 dwg, 5 tbl
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![]() Device contains original circuit, four groups of AND elements, group of OR elements, encoding device, folding circuit, register, error syndrome circuit, checks circuit, three decoders, corrector. |
![]() Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector. |
![]() Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, inversion block, decoder, even parity check circuit, corrector. |
![]() Device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, corrector. |
![]() Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, inversion block, decoder, corrector. |
![]() Device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, even parity check circuit, corrector. |
![]() Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector. |
![]() Device contains original circuit, four groups of AND elements, group of OR elements, encoding device, register, error syndrome circuit, checks circuit, three decoders, corrector. |
![]() Device contains original circuit, three groups of AND elements, AND element, group of OR elements, OR element, encoding device, register, error syndrome circuit, checks circuit, three decoders. |
![]() Device contains original circuit, three groups of AND elements, AND element, group of OR elements, OR element, encoding device, register, error syndrome circuit, checks circuit, three decoders. |
![]() Device contains original circuit, four groups of AND elements, group of OR elements, encoding device, register, error syndrome circuit, checks circuit, three decoders, corrector. |
![]() Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector. |
![]() Device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, even parity check circuit, corrector. |
![]() Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, inversion block, decoder, corrector. |
![]() Device contains original circuit, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, corrector. |
![]() Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, inversion block, decoder, even parity check circuit, corrector. |
![]() Device contains memorizing device, four groups of AND elements, AND element, group of OR elements, seven OR elements, encoding device, register, error syndrome circuit, NOT element, decoder, inversion block, even parity check circuit, corrector. |
![]() Device contains original circuit, four groups of AND elements, group of OR elements, encoding device, folding circuit, register, error syndrome circuit, checks circuit, three decoders, corrector. |
![]() Proposed method for encoding sparse parity control code formed from information-section matrix and from parity-section matrix includes steps of information-section matrix conversion into array code structure and assignment of exponent sequences to each column of sub-matrix; extension of two-diagonal matrix corresponding to parity-section matrix so that amount of displacement between diagonals were of random value; enhancement of normalized two-diagonal matrix; evaluation of degree of displacement for cyclic shift of columns in each sub-matrix of higher normalized two-diagonal matrix; and definition of parity symbol corresponding to column in parity control matrix. |
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