ethods or arrangements for processing data by operating upon the order or content of the data handled (G06F7)

Functional structure of least significant bit of adder f_cd(Σ)_ru for arguments of terms ^±[^1,2n_j]f(2ⁿ) and ^±[^1,2m_j]f(2ⁿ) of "complementary code ru" format (versions of russian logic)

Invention relates to computer engineering and can be used in designing arithmetic devices and performing arithmetic procedures for summation of positional arguments of terms ±[1,2nj]f(2n) and ±[1,2mj]f(2n). In one version, the adder is based on logic elements executing logic functions NOT and NAND.

Neuron-based ripple carry parallel adder-subtractor

Invention relates to information and computer engineering equipment and can be used to create arithmetic logic units for designing high-speed and efficient digital devices for summation and subtraction of numbers in a binary number system in direct codes. The device has a number input unit, a comparator unit, an adder unit, a larger number register unit, a summation-subtraction unit, a smaller number register unit, a result register unit and a control unit.

Method of generating logic-dynamic process of converting conditionally minimised structures of arguments of analogue signals of terms ^±[n_i]f(+/-)_min and ^±[m_i]f(+/-)_min in functional adder structure ^±f₁(Σ_ru)_min without ripple carry f₁(^±←←) and process cycle ∆t_Σ → 5∙f(&)-and five conditional logic functions f(&)-and, realised using procedure for simultaneous conversion of arguments of terms through arithmetic axioms of ternary number system f_ru(+1,0,-1) and functional structures for realisation thereof (version of russian logic)

In one version, the functional structure is realised on logic elements AND, OR, NOR, NAND.

Device for filtering moving digital images in limited aprior data volume conditions

In the device, the output of an input realisation storage unit is connected to the input of a frame selection unit, the output of which is connected to the first inputs of switches; the output of an arithmetic adder is connected to the input of a frame storage unit, the output of which is connected to the input of a frame averaging unit, the output of which is connected to the input of a useful component estimate storage unit.

Method and apparatus for supporting alternative computations in reconfigurable system-on-chip

Group of inventions relates to microelectronics and computer engineering and can be used to design high-performance computer systems for processing data streams in real time. The apparatus has pairs of external single-bit inputs and outputs, a setting code register, an input switch, a data processing unit and an output switch, controlled by corresponding setting code fields, wherein the input and output switches and the data processing unit are controlled by pairs of alternative setting code fields, one of which is selected by a corresponding multi-bit multiplexer, controlled by a single-bit condition variable signal.

Logic converter

Device is designed to execute any of four simple symmetric Boolean functions, which depend on four arguments - input binary signals, and can be used in digital computer systems as a code conversion means. The device has five majority elements.

Logic converter

Device is designed to realise any of five simple symmetric Boolean functions, which depend on five arguments - input binary signals, and can be used in digital computer systems as a code conversion means. The device has twelve majority elements.

Method of generating quasi-structured models of factographic information content of documents

Invention relates to computer engineering and can be used in creating databases. The method of generating quasi-structured models of factographic information content of documents involves determining effect parameters and a target function. The chosen effect parameters are model validation, model granularity, uniformity of distribution of structural units across the document, saturation of structural units in the document and model flexibility. The chosen target function is effect parameter convolution. Values of all effect parameters and the target function are calculated for each document and the average value of the target function is then calculated. Content of structural units of the obtained model is analysed in order to make changes and values of the effect parameters and the target function are calculated for each document, and the average value of the target function is then calculated. Average values of the target function are then compared. If the average value of the target function had dropped, the new corrected model is optimal.

F3 adder functional structure (sigmacd) of arbitrary "g" digit implementing decoding procedure for arguments of summands [1,2sgh1]f(2a) and [1,2sgh2]f(2n) of position format "extra code ru" by arithmetic axioms of ternary notation f(+1,0,-1) and double logical differentiation d1,2/dn-f1,2(+-)d/dn of active arguments of "level 2" and removal of active logical zeroes "+1""-1"-"0" in "level 1" (versions of russian logic)

Set of inventions relates to computers and can be used for construction of arithmetic devices and execution of arithmetic procedures of adding of position arguments of analogue signals added with application of arithmetic axioms of ternary notation f(+1,0,-1). In compliance with one of versions, functional structure is constructed with application of logical elements AND, OR, NO.

Method and system for searching for copyright infringements on image

Method of searching for copyright infringements on an image, executed on a computer system, involves calculating a descriptor for an image N1, situated in a memory unit N1; calculating a descriptor for an image N2, situated in a memory unit N2; comparing the values of the descriptors of images N1 and N2; if said values are equal, images N1 and N2 are compared, after which the comparison results are displayed on an information display device.

Coincidence adder

Device includes eight XOR elements and six AND elements.

Device for conversion from polynomial system of residue classes to position code

Device has a device start input, a group of shift registers, a synchronisation unit, a device output, three-input AND element units, a modulo 2 adder, a group of data inputs, a group of control inputs of the device, a group of orthogonal base computing units, each having memory units, a modulo adder, a register, an index-to-element converter and a multiplier.

Apparatus for performing division and square-rooting

Apparatus enables to perform division and square-rooting in a floating point format according to the IEEE 754 standard with single or double accuracy. Input operands can be presented in a floating point format with both single and double accuracy. The apparatus includes a unit for selecting the power and mantissa of input operands, a circuit for controlling a three-step conveyor of an input register unit, an input register unit, a circuit for controlling an adder unit and a multiplier unit, a multiplier unit, an adder unit and a unit for generating computation results.

Method of facilitating multiplication of two numbers in modular-position presentation format with floating point on universal multi-core processors

Method is realised on a universal multi-core computer, having g k-bit cores, each facilitating a system of f operations which include algebraic multiplication and algebraic addition of numbers presented in position integer data formats. When facilitating multiplication operations, each number, multiplier and multiplicand, is presented in a modular-position format with a floating point in form of a (1+k+q·n)-element vector.

Device for comparing binary numbers

Device for comparing binary numbers is designed to recognise relationships A>B, A=B, A<B, where A=an-1…a0, B=bn-1…b0 - n-bit binary numbers, defined by binary signals a0,…an-1, b0, …, bn-1∈{0,1}, and has 3n switches (11,…,3n).

Image processing method and apparatus

Invention relates to computer engineering. The image processing apparatus has motion compensation means for performing motion compensation using as reference frames a plurality of frames formed by images obtained from decoding encoded images, and using motion vectors included in the encoded images, and for generating a plurality of images with motion compensation, which correspond to the predicted image based on different reference frames; first filtering means for applying a low-pass filter to a difference image between the plurality of images with motion compensation, generated by the motion compensation means; second filtering means for applying a high-pass filter to the image obtained by the first filtering means by applying the low-pass filter; and means of generating a predicted image for generating a predicted image by adding the image obtained by the first filtering means and the image obtained by the second filtering means to one of the plurality of images with motion compensation, generated by the motion compensation means.

Detection method and apparatus

Disclosed method and apparatus relate to electronic detectors which detect changes in ambient electromagnetic background. The main field of application is determining the emotional state of consciousness, entertainment and electronic games with interactive control, equipment for solutions in the field of decorative and designer works, for interior installations and lighting devices. The detection method is characterised by that an initial electric signal is emitted from a noise source which, through amplification and filtration, is converted to a random pulse sequence consisting of high- and low-level voltage pulses, which is converted to a sequence of numerical values; the numerical values from said sequence are sampled over a certain time interval and the detected signal is obtained by analysing the numerical values in the sample, wherein the sequence of numerical values is obtained by calculating over a given time interval the difference between duration of the high- and low-level voltage pulses of the random pulse sequence, and the detected signal is obtained by calculating the variance of numerical values in the sample. The apparatus comprises a noise signal source, three amplifiers, a microprocessor unit which calculates variance and analyses it, two frequency-dependent circuits and a LED indicator.

Methods of performing elementary computational operations and apparatus for realising said methods

Apparatus has in each binary bit one RS flip-flop, seven AND logic elements, five OR elements, four NOT elements, a data input, first and second data outputs and six control inputs. The method and apparatus for realising the method facilitate the execution of such logic operations as receiving a code in register flip-flops, code inversion for register flip-flops, an operation for shifting the received code to the left, a modulo 2 summation operation, logic addition of two binary codes and logic multiplication.

Boolean function variable signal generator

Signal generator comprises log2N unit transformation steps, where N is the number of bits of the transformed sequence, each step comprising a shift register, AND coincidence group elements; outputs of the AND coincidence group elements of each step are connected to inputs of the shift register of the next step and a control unit, outputs of which are connected to second inputs of AND coincidence group elements of all unit transformation steps; each unit transformation step includes an XOR element, the first input of which is connected to the input of the shift register of the same step, and the second input is connected to the output of the shift register of the same step, wherein outputs of the XOR elements are connected to the first inputs of the ND coincidence group elements of the same unit transformation step.

Logic computer

Device includes n D flip-flops, n NOR elements, n opening switches and n closing switches.

Device for comparing binary numbers

Device can be used to design automation apparatus and functional parts of control systems. The device includes four XOR elements, four closing switches and four opening switches.

Single-bit full adder with multidigit internal signal notation

Disclosed is a single-bit full adder with multidigit internal signal notation, having first, second and third input current I0 quanta switches having first, second and third current outputs, first, second and third input logic signal sources, first and second auxiliary reference current sources which control the status of the corresponding current I0 quanta switches, wherein the circuit includes first, second and third current mirrors, each having two inverting identical current outputs, and three additional current mirrors.

Device for determining sign of modular number

Device includes input registers for temporary storage of bits of the initial number, memory for storing products and a parallel adder.

Method for nonlinear three-dimensional many-round conversion of data dozen

Method involves presenting input 1 and output 2 data blocks, all intermediate results S of conversions and round keys (RoundKeys) 30, 31 32, 33 in form of a cubic array of bytes 4×4×4, defining a Layer 4 concept - quadratic array of bytes 4×4, presenting the first round key in form of four sub-keys (RoundSubKeys) 3i0, 3i1, 3i2, 3i3, i=1, 2, 3, each of which is in essence a quadratic array of bytes 4×4, adding 10 (XOR) the data block 1 with round key 30, three-dimensional conversion of the data block on layers 4x0, 4x1, 4X2, 4x3, 4y0, 4y1, 4y2, 4y3, 4z0, 4z1, 4z2, 4z3 respectively along x, y and z axes, including, in the procedure for two-dimensional conversion of layer 5 (T-Layer), four steps: replacing 6 bytes (SubBytes), mixing 7 rows (MixRows), mixing 8 columns (MixColumns), adding (XOR) 9 to a round sub-key (AddRoundSubKey).

Programmable logic device

Device includes groups of D flip-flops, function calculating units, a counter, a decoder, conjunction units, conjunction value units, wherein the function calculating units, conjunction units and conjunction value units are based on 2·2NOT-AND-OR elements which execute the function

Device for comparing numbers presented in residue number system

Device includes input registers, sign determining circuits, number polarity shifting circuits, look-up tables (memory) for storing constants and an adder, an XOR element and a number sign analysis circuit.

Device for matching exponents of m binary numbers

Device includes a unit for determining the maximum exponent, which consists of an m-input XOR element and m cells, each having AND elements, an XOR element, flip-flops, and a subtracting unit consisting of m cells, each having AND elements, XOR elements, an OR element, a NOT element and flip-flops.

Systems and methods for optimisation of real-time extraction operations

In one version, a moving time horizon based parametric model provides fast predictions for extraction optimisation in a short-term configuration. In another version, multiple technologies are selected in connection with asset performance workflows that are uniquely implemented in a multi-phase approach.

Method of facilitating multiplication of floating-point numbers represented in residue number system

Method comprises steps of: concurrently writing the remainder on base p1 of a multiplicand in memory elements; concurrently counting the number of units bi in each column of the i-th matrix; shifting the binary number b1 one bit to the right; summing with a number b2; shifting the obtained sum b 2 s one bit to the right and summing with a number b3. Similarly, the obtained sums are shifted and summed with subsequent numbers to obtain a sum b 2 * m − 1 s , wherein the least significant bit of the number b1 is the first multiplication bit s1, the least significant bit of each obtained sum b i s is the i-th multiplication bit. The binary number b 2 * m − 1 s is shifted; the least significant bit of the obtained number is the (2*m)-th bit of the determined product s2*m. If s is greater than p1, the obtained product s is corrected by successive subtraction of the base p1 from s until s is less than p1, otherwise correction is not performed; similarly, products of m-bit residues on the rest of the bases are calculated and corrected; the powers of multipliers are simultaneously summed up and the resultant sum is the power of the determined product.

Modulo adder-accumulator

Device has an n-bit adder, an (n+1)-bit adder, a multiplexer and a register.

Method of exact division of integer binary numbers, starting from least significant bit

Method includes stages, at which a divisor is recorded in parallel into matrix cells on memory elements, the first bit of the quotient becomes equal to the sum of module two of the least significant bit in the first column of the matrix and the first bit of the dividend, other bits of the quotient become equal to zero; the number of units b2 is counted in a vector equal to bit-by-bit logical multiplication of the appropriate bits of the second column of the matrix and bits of the quotient, at the same time the second bit of the quotient becomes equal to the sum of module two for the least significant bit b2 and the second bit of the dividend; similarly, the number of units bi is counted in a vector, which is equal to the bit-by-bit logical multiplication of the appropriate bits of the i column of the matrix and quotient bits, afterwards the sum ci of the vector bi and the vector bi-1 shifted by one bit to the right is calculated, at the same time the i bit of the quotient becomes equal to the sum of module two of the least significant bit ci and the i bit of the dividend, as a result the m-bit quotient of initial numbers will be generated.

Device to predict exceptional situation "accuracy loss" of "multiplication with accumulation" operation unit

Device comprises a subblock of prediction of a sum of fractional parts, a counter of senior zeros of the sum of fractional parts, registers of fractional parts of numbers, input registers of number exponents, a counter of junior zeros of the summand fractional parts, a subblock of calculation of a shift of levelling and prediction of a shift of preliminary normalisation, a comparator of early loss of accuracy, a counter of junior zeros of a sum of fractional parts, a comparator of late loss of accuracy.

Logic module

Logic module has six closing switches and six opening switches.

Apparatus for boundary composite coding in interval computations

Apparatus includes flip-flops, registers, ROM, subtractors, adders, multiplexers, shifters, a comparator unit, modulo two adders, AND and OR elements and a priority encoder.

Apparatus for decoding jointly stored boundaries in interval computations

Apparatus includes an encoder, a decoder unit, ROM, shifters, subtractors, multiplexers, an adder, modulo two adders, an inverter, AND and OR elements.

Ternary logic-based random number generator

Device consists of identical combinational circuits operating in ternary logic, having two input and one output, combined into a ring circuit, wherein the output of each circuit is connected to the input of the same circuit and the input of the next circuit in a ring connection. A ternary signal with uniform distribution is obtained from any output of the circuit.

Method by kuvyrkov for information processing and calculation (versions) and device "generaliser" for method realisation

In one of versions the method includes parallel-serial processing of a signal in a block of triggers of an input register; in a matrix device; in a unit of logical elements, preferably logical elements "AND"; in a unit of triggers of an output register. At the same time the signal processing in the matrix device is performed in accordance with the geometric model of the signal processing, representing a combination of graphs that forms at least one right triangle, which is divided into three parts, with lines stretching from the tops of the triangle angles.

Logic processor

Disclosed is a logic processor designed to execute eight simple symmetrical Boolean functions which depend on eight arguments - input binary signals, which can be used in digital computer systems as a code converting means, and also having nineteen computational cells (11,…,119), each having an OR element (2) and an AND element (3).

Method of calculating sum n of m-bit numbers

Method includes steps for parallel counting of the number of units bi (i=1 m) in m n-bit binary vectors, shifting the binary number b1 one bit to the right, summing with a number b2, shifting the obtained sum bs 2 one bit to the right and summing with a number b3. Similarly, the obtained sums are shifted and summed with the next numbers until a sum bs m is obtained. The least significant bit of the number b1 is the first bit s1 of the sum and the least significant bit of each obtained sum bs i is the i-th bit si of the sum. The binary number bs m is shifted one bit to the right and if bs m=0, computation is stopped, otherwise the least significant bit is the sm+1-th bit of the sum; if bs m≠0, the binary number bs m is shifted and the obtained number is the value of most significant bit of the desired sum, starting from the m+1 bit.

System and method for adaptive prioritisation of antivirus scanning objects

System for adaptive prioritisation of antivirus scanning objects includes a rule setting device which sets rules for prioritising antivirus scanning objects, a rule database for storing prioritisation rules and providing rule data to a queuing device. The system also includes an analyser which determines parameters of antivirus scanning objects required for prioritisation and sends said parameters to the queuing device. The queuing device is designed to assign priority and a scanning method with defined parameters in accordance with set rules. The queuing device also constructs a queue in accordance with the assigned priorities and sends the queue to a malicious object detecting device. The malicious object detecting device performs antivirus scanning of the scanning queue in accordance with the scanning method assigned for each object and sends the scanning results to a scanning result analyser.

Phase synchronisation method and apparatus

Phase synchronisation of a narrowband signal is based on sampling thereof on zero crossing, conversion to a binary code and comparison with one of normalised biorthogonal sequences by integration and summation, wherein the binary code undergoes Boolean transformation over Galois field GF(2n), conjugate pair Boolean transformation coefficients are multiplied, subjected to unitary Boolean transformation and, using fast Walsh transformation by Pontryagin maximum method on a threshold level, the number of one of the biorthogonal sequences which coincides with the number of a narrowband filter, independent of phase, is found. The apparatus includes an amplifier with a sampler, a random-access memory unit, a unit for Boolean transformation over Galois field GF(2n), a fast Walsh transformation unit, and additionally a unitary Boolean transformation unit, the inputs of which are connected to outputs of multipliers, and the output is connected to the input of the fast Walsh transformation unit.

Media processor for organising multimedia data

System has a control level which includes a topology generating element for generating a topology that describes a set of input multimedia streams, one or more input multimedia stream sources, a sequence of operations performed over multimedia data, and a set of output multimedia streams, and a media processor for controlling transmission of multimedia data as described in the topology, and controlling execution of the sequence of multimedia operations over the multimedia data to create a set of output multimedia streams. A nucleus level includes input multimedia streams, input multimedia stream sources, one or more converters for handling multimedia data, stream receivers and media receivers for providing a set of output multimedia streams.

Methods and systems for implementing approximate string matching within database

Method for character string matching of a candidate character string with a plurality of character string records stored within a database involves identifying a set of reference character strings in the database. The reference character strings are identified using an optimised search for a set of dissimilar character strings. An n-gram representation of each of the reference character strings in the set of reference character strings is generated and an n-gram representation of the candidate character string is also generated. Further, similarity between n-gram representations of each of the reference character strings and the candidate character string is determined. The candidate character string in the database is indexed based on the determined similarities between the n-gram representation of the candidate character string and the reference character strings in the identified set.

Homogeneous computing environment for conveyor calculations of sum of m-n-digit numbers

Homogeneous computing environment provides for parallel conveyor summation of m n-digit operands and comprises identical cells made of 2 double-input elements AND, 2 double-input elements EXCLUSIVE OR, a double-input element OR, an element NOT, 3 information triggers, at the same time the number of columns in the homogeneous computing environment is equal to p, where p=log2m, and the number of cells in the j column is equal to m/2j.

Self-checking special-purpose computer of boolean function systems

Device has memory units, adders, multiplexers, a remainder modulo calculating unit, a memory register, logic elements AND and NOR.

Method of facilitating multiplication of floating-point numbers represented in residue number system

Remainder on base pi of a multiplicant is concurrently recorded in matrix memory elements of the i-th multiplier; the number of units bi in each column of the i-th matrix is concurrently counted; the binary number b1 is shifted by one bit to the right and summed with number b2; the obtained sum bs 2 is shifted by one bit to the right and summed with number b3. Similarly, the obtained sums are shifted and summed with subsequent numbers to obtain a sum bs 2*m-1, wherein the least significant bit of the number b1 is the first multiplication bit s1, the least significant bit of each obtained sum bs i is the i-th multiplication bit. The binary number bs 2*m-1 is shifted, the least significant bit of the obtained number is the (2*m)-th bit of the determined product s2*m. If si is greater than pi, the obtained product si is corrected by successive subtraction of the base pi from si until si is less than pi, otherwise correction is not performed; powers of multipliers are simultaneously summed up and the resultant sum is the power of the determined product.

One-bit full modulo adder

Invention can be used in digital computers as well as digital signal processing devices and cryptographic applications. The device has logic elements NOT, AND, OR.

Functional structure of second least significant bit activating resultant argument (²s_min+1)f(2ⁿ) "level 2" and (¹s_min+1)f(2ⁿ) "level 1" of addder f_cd(Σ)_ru for arguments of terms ^±[^1,2n_j]f(2ⁿ) and ^±[^1,2m_j]f(2ⁿ) of "complementary code ru" format (versions of russian logic)

Invention can be used when designing arithmetic units and performing arithmetic procedures for summation of positional arguments of terms. In one version of the invention, the adder is constructed from logic elements NOT, OR, AND, NAND, NOR.

Apparatus for detecting dynamic range overflow, determining error and localisation of computation channel faults in computers operating in residue number system

Apparatus has input registers, projection generating circuits, memory units, adders, an analysis circuit, AND logic elements, a flip-flop and a projection counter.

Method to generate arguments of analog signals of partial products [n_i]&[m_j]f(h)_↓cd arguments of multiplicand ^±[m_j]f(2ⁿ) and arguments of multiplier ^±[n_i]f(2ⁿ) - "additional code" in pyramidal multiplier f_Σ(↓_cdΣ) for subsequent logical decoding f₁(cd↓) and generation of resulting sum in format ^±[s_Σ]f(2ⁿ) -"additional code" and functional structure for its realisation (versions of russian logics)

Invention may be used to build arithmetic devices for performance of arithmetic operations of multiplication of multiplicand arguments ±[mj]f(2n) and multiplier arguments ±[ni]f(2n) - "Additional code". In one of versions the structure is realised using logical elements CFU, OR-CFU.