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Optical associative search processor

IPC classes for russian patent Optical associative search processor (RU 2263946):

G06F17/30 - Information retrieval; Database structures therefor

G06E1 - Devices for processing exclusively digital data

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FIELD: computer science.

SUBSTANCE: processor has external memory control block, local memory block, micro-program control block, control memory block, processor control block, optical matrix common system bus, cash memory blocks, multi-channel optical associative correlator blocks, optical space-variable connection blocks, logical element blocks, optical block for input/output of processor signals, external main for input/output of processor signals, internal optical main for input/output of processor signals, local input/output buses, optical input/output blocks, optical input/output buses, optical blocks for decoding input/output signals, local communication buses connected to matrix optical common system bus.

EFFECT: higher efficiency, broader functional capabilities, higher resistance to interference, higher durability, higher reliability.

3 cl, 1 dwg

The invention relates to computing and information technology and can be used to create a variety of optoelectronic equipment computer and information technology, including military, space, environmental and consumer.

Known optoelectronic computing system with shared system bus [1]that contains processors, RAM and other memory, peripherals, optical bus system for exchanging information between devices in the system. The main disadvantage of this structure is not a high speed due to the relatively low speed of transmission of signals between the units of the processor.

Closest to the proposed device is the processor [2], containing the control unit external memory, the local memory unit firmware control, the control unit memory. The main disadvantage of this structure is not a high speed due to the relatively low speed of transmission of signals between the units of the processor and the lack of a hardware associative search.

The technical result is improved performance, noise immunity, reliability, processor, and expanding its functionality due to the possibility of high speed recording motion is ostego, multi-associative hardware data retrieval.

This is achieved in that in the optical associative search processor that contains the control unit, the external memory unit local memory unit firmware control, the control unit memory control unit processor entered the optical matrix common system bus, the blocks of the cache memory, the block of multi-channel optical associative correlator, optical blocks in the spatial variables of links for rearranging the words in the page information, blocks of optical logic elements for Boolean logic operations, the optical block input/output signals of the processor, the external line input/output signals of the processor, the internal optical line input/output signals of the processor local bus input/output optical input/output optical bus input/output, optical units decode the input/output signals, a local communication bus matrix with common system bus and the inputs/outputs of each block of the external memory control unit firmware management control unit CPU through the respective consistently located and connected by local bus I/o, optical block I/o, optical bus input/output, optical block decoders, input/output with whom gralow, local bus connection with the General system bus optically connected with the optical shared system bus, the inputs and outputs of each block in the local memory unit memory management unit cache memory, the block of multi-channel optical associative correlator, through the respective consistently located and connected by local bus I/o, optical block I/o, optical bus input/output, optical block decoders input/output signals, optical bus input/output, optical spatial variables of links for rearranging the words in the page information, the optical bus input/output, optical logic elements for Boolean logic operations, local bus connection with the General matrix system bus optically connected with the optical matrix of the total system bus, input/output through which consistently located and associated internal optical line input/output signal processor, the optical block I/o signals to the processor, the optical bus I/o unit optical logic elements for operations Boolean logic, optical bus input/output, optical spatial variables of links for rearranging the words in the page information is optically connected to the external line input/output signals in the processor.

is the the optical matrix common system bus includes a single optical line.

And the fact that optical shared system bus includes an optical line addresses, the optical line data, the optical line control.

This set of essential features and relationships between them allows to obtain a device having more than 1000 times more performance, noise immunity and reliability, and more functionality at the expense of direct hardware associative information retrieval

The invention consists in that on the basis of optical associative hardware search methods and signal transmission, optical total matrix of the system bus, using as a transmission medium is free space and/or an array of fibers (fiber and/or integral), the original schemes of optical input/output signals of the blocks of the processor, the original structure of the processor created the architecture of optical associative poiskah processor WEB 2 Alexander VERBOVETSKOGO, which greatly improve the performance, noise immunity, reliability of the processor and various equipment, built on its basis, as well as to extend its functionality through apparatnogo associative multi-channel high-speed information retrieval.

Thus, the proposed optical associative processor WEB 2 Alexander VERBOVETSKOGO has properties that are not inherent in prior devices. This is due to a new set of essential features and new relationships set forth above.

The comparison of the proposed device with the known evidence about compliance with a criterion of "novelty", and the lack of analogues of the distinctive features of the proposed device is based on the criterion of "inventive step".

The drawing shows a functional diagram of an optical associative search processor WEB 2 Alexander VERBOVETSKOGO.

Optical associative processor WEB 2 Alexander VERBOVETSKOGO includes: control box external memory 1 having local bus I/o 1-1, optical input/output 1-2, optical bus I/o 1-3, the optical block decoders input/output signals 1-4, the local communication bus with shared system bus 1-5; block firmware control 2, with local bus I/o 2-1, the optical input/output 2-2, optical bus I/o 2-3, optical block decoders input/output signals 2-4, the local communication bus with shared system bus matrix 2-5; block of local memory 3 having a local bus I/o 3-1, optical blocks I/o 3-2, optical is ins I/o 3-3, optical block decoders input/output signals 3-4, optical bus I/o 3-5, the optical block of the spatial variables of links for virtual rearranging the words in the information page 3-6, optical bus I/o 3-7, optical logic elements for operations Boolean logic 3-8, local bus connection with the General matrix system bus 3-9, block cache memories 4, with local bus I/o 4-1, optical blocks I/o 4-2, optical bus input/output 4-3, the optical block decoders input/output signals 4-4, optical bus input/output 4-5 optical spatial variables links for virtual rearranging the words in the information page 4-6, optical bus I/o 4-7, optical logic elements for operations Boolean logic 4-8, local bus connection with the General matrix system bus 4-9; block multichannel optical associative correlator 5, with local bus I/o 5-1, optical blocks I/o 5-2. optical bus input/output 5-3, the optical block decoders input/output signals 5-4, optical bus I/o 5-5, the optical block of the spatial variables of links for virtual rearranging the words in the information page 5-6, optical bus I/o 5-7, optical logic elements for operations bule is th logic 5-8, local communication bus with shared system bus 5-9; unit control memory 6 having a local bus I/o 6-1, optical blocks I/o 6-2, optical bus I/o 6-3, optical block decoders input/output signals 6-4, optical bus I/o 6-5, the optical block of the spatial variables of links for virtual rearranging the words in the information page, 6-6, optical bus I/o 6-7, optical logic elements for operations Boolean logic 6-8, local communication bus with shared system bus 6-9; the control unit 7 processor having local bus I/o 7-1, optical input/output 7-2, optical bus I/o 7-3, the optical block decoders input/output signals 7-4, local communication bus with shared system bus 7-5; optical matrix common system bus 8; internal optical line input/output signal processor 9; an optical unit input/output signals in the processor 10; optical bus input/output 11, the optical logic elements for operations Boolean logic 12, the optical bus I/o 13, the optical block of the spatial variables of links for virtual reflow words in page information 14, the external line input/output signals to the processor 15.

The control unit external memory 1 is designed for implementation on nomicheskogo data exchange between the processor and external to the processor memory, the unit may include memory protection keys, cache memory, memory mnogoabonentnyh access, block dynamic NAT when implementing virtual memory. The block 1 may be performed on the electronic, optoelectronic and optical components.

Local bus I/o 1-1 for transmitting electrical or optical signals may contain line address, data and control with depending on the type of transmitted signals as a conducting medium, for example, metal wires, one, several or matrix fibers (fiber and/or integral) or free space.

Optical input/output 1-2 serve to negotiate and, if necessary, convert the input/output electronic or optical signals in the optical or electrical, in accordance with the type of execution unit 1. To convert the input electronic signals in the optical, these blocks can be performed, for example, in the form of strips or matrices of laser diodes each of which emits, for example, at the wavelength λ_iwhere i=1,2,3...R, while R is the maximum number of signals for parallel code, and signal transmission is series-parallel code, serial optical signals are transmitted, for example, each is lasernet diode at different wavelengths λ _j(where j=1,2,3...s, s is the maximum number of signals transmitted by the serial code)that is different from the wavelengths of optical signals that are transmitted parallel code. If the inputs of the block 1-2 receives optical signals on their inputs can optionally be line or matrix of photodetectors.

Optical bus I/o 1-3 are used to transmit optical signals and may contain a line of the address, data and line management, having as a transmission medium, for example, one, several, or an array of fibers (fiber and/or integral) or free space.

Optical block decoders input/output signals 1-4 are used to highlight a specific group of spectral optical signals from a variety of groups of spectral optical signals propagating along the optical shared system bus 10, which correspond to the block 1. Unit 1-4 can be performed, for example, on the basis of the light guide (fiber and/or integral) optics using diffraction gratings or spectral filters, multiplexers, demultiplexes.

Local bus connection with optical shared system bus 1-5 is used for transmitting optical signals to/from the optical system bus 10 from/to the unit 1 and may consist of one line or contain line address data and control. Highways can be made in the form of one, several or matrix fibers (fiber and/or integral) or free space.

Unit firmware management 2 operates in time division mode or spectral multiplexing the operation of the processor and some procedures of channels I/o, using firmware stored in the control memory. However, he issues an order by microinstruction control signals in the corresponding blocks of the processor, generates the address of the next microcommand and processes the interrupt firmware. When you interrupt the firmware in the unit remembers the address of the next be performing microcommand. Block 2 may have an electronic, optoelectronic or optical performance.

Bus 2-1, 2-3, 2-5 have the same purpose and perform that same bus 1-1, 1-3, 1-5.

Blocks 2-2, 2-4 have the same purpose and the fulfillment of that and similar units 1-2, 1-4.

The block of local memory 3, the CPU may be used to store operands and results of operations, the value of the base address and index data block diagnostics and recovery, control word of the active subchannels. Block 3 can have, for example, an electronic, optoelectronic or optical performance.

Bus 3-1, 3-3, 3-5, 3-7, 3-9 have the same purpose and execution, Thu and similar bus 1-1, 1-3, 1-5.

Blocks 3-2, 3-4 have the same purpose and the fulfillment of that and similar units 1-2, 1-4.

The optical block of the spatial variables of links for virtual rearranging the words in the information page 3-6 is used to create a spatially-variable relations between the words of the operands, and can be performed as described in [3] or Copyright certificates No. 1531166 from 15.04.88, No. 1596340 from 15.06.88, No. 1603401 from 15.06.1988,, Patent No. 1767534 from 20.12.89,

Optical logic elements for operations Boolean logic 3-8 is used for logical processing of bits of words in the page information and can be performed as described in [3] or Copyright certificates No. 1394982, 1396827 from 29.09.86, and Patent No. 2015578, 2015579, 2015580 - all dated July 10, 1991

The block of the cache memory 4 is used for coordination capacities external to the processor memory and processor to be implemented in the processor performance equal to the performance of its operating units, and can consist of several modules cache. The block 4 may be performed on the electronic, optoelectronic and optical elements.

Bus 4-1, 4-3, 4-5, 4-7, 4-9 have the same purpose and perform that same bus 1-1, 1-3, 1-5.

Blocks 4-2, 4-4 have the same purpose and the fulfillment of that and similar units 1-2, 1-4.

Blocks 4-6, 4-8 can be performed as well as similar units 3-6, 3-8.

<> Block multichannel optical associative correlator 5 is used for multi-channel optical hardware search information, and can be run as described in [3].

Bus 5-1, 5-3, 5-5, 5-7, 5-9 have the same purpose and perform that same bus 1-1, 1-3, 1-5.

Blocks 5-2, 5-4 have the same purpose and the fulfillment of that and similar units 1-2, 1-4.

Units 5-6, 5-8 can be performed as well as similar units 3-6, 3-8.

The block of control memory 6 is used to store control information of the firmware and can be electronic, optoelectronic and optical implementation.

Bus 6-1, 6-3, 6-5, 6-7, 6-9 have the same purpose and perform that same bus 1-1, 1-3, 1-5.

Blocks 6-2, 6-4 have the same purpose and the fulfillment of that and similar units 1-2, 1-4.

Blocks 6-6, 6-8 may be made as similar blocks 3-6, 3-8.

The control block processor 7 is designed to control the operation of the processor and based on mixed hardware and firmware. The block 7 may be performed on the electronic, optoelectronic and optical elements.

Bus 7-1, 7-3, 7-5 have the same purpose and perform that same bus 1-1, 1-3, 1-5.

Blocks 7-2, 7-4 have the same purpose and the fulfillment of that and similar units 1-2, 1-4.

Optical matrix common system bus 8 is used for transmitting optical signals between the ranks of the blocks of the optical processor, and may include a single optical pathway in the form of a single optical fiber (fiber and/or integral) or free space, or can contain a line address, highway and data highway administration. Each line may have as a transmitting optical medium one, several, or an array of fibers (fiber and/or integral) or free space.

Internal optical line input/output signal processor 9 is used for transmitting optical signals from external to the processor device in the optical matrix common system bus of the processor and may contain one line or highway address, data and control, having as a transmission medium, for example, one, several, or an array of fibers (fiber and/or integral) or free space.

The optical block I/o signals to the CPU 10 serves to harmonize external to the processor signals from the optical signals transmitted via the optical system share the processor bus, and can be executed, similar to the block 1-2.

Optical bus I/o 11, 13 have the same execution as the bus 1-1, 1-3.

Optical logic elements 12 and the optical block of the spatial variables of links 14 have the same implementation as before described similar blocks.

External line input/output signals in the processor 15 is used for transmitting electrical or optical signals from external to the process, the PN device to/from the processor and may contain one line or highway address, data and control. Depending on transmitted via highways signals as a transmission medium can be either metallic conductors, or one, several, or an array of fibers (fiber and/or integral) or free space.

Optical associative search processor "WEB 2" Alexander VERBOVETSKOGO works as follows.

The input/output processor WEB 2 information and control signals in the optical or electrical form transmitted from/to the external(e) device(s) via an external line 15, the optical block of the spatial variables of links 14, the optical block of the logical links 12 and optical bus I/o 13 to/from optical(Oh) matrix(nd) total(s) system(oops) bus(s) 8 optical signals with spectral or temporary seal.

Each of transmitting information blocks 1-7 processor transmits it in the form of electronic or optical signals through the corresponding bus 1-1, 1-3, 1-5 ... 7-1, 7-3, 7-5 and blocks 1-2, 1-4 ... 7-2, 7-4 arrive in the optical matrix common system bus 8 in the form of spectral optical signals with spectral or temporary seal.

Spectral optical signals from all transmitting units 1-9 simultaneously using wavelength division multiplexing distributed under the common system bus 8 and go throu the local input optical bus 1-5 ... 7-5.

In each of the host information blocks 1-7 optical block decoders 1-4 ... 7-4 control signals are configured to allow groups of spectral optical signals transmitted from the respective transmitting information blocks with which they produce the communication session. Then allocated these blocks decode optical signals in this receiving channel is converted and delivered to the processing in the corresponding blocks 1-9.

It should be noted that the transfer of information on all bus systems may be performed by a signal as soon as the using wavelength division multiplexing, and simultaneously with spectral and temporal compaction, and communications of all units of the system can be carried out simultaneously, or in groups with a separation in time.

The use of the invention will allow to implement optical communication between blocks associative poiskah processor optical matrix a shared system bus, increasing more than 1000 times its performance, noise and reliability, as well as to extend its functionality by performing high-speed multi-channel hardware associative retrieval of information, currently unavailable on other non-optical principles. Such optical processors WEB 2 Alexander VERBOVETSKOGO can sh is widely used in various electronic equipment military, rocket-space, environmental, and domestic purposes both ground and airborne platforms.

LITERATURE

1. Patent (Russia) №2144206, MKI 06 E G 1/00, 19.02.1999.

2. Buy. Fundamentals of computer technology & personal PC. M: ALEX, 2003, s (s).

3. Buy. Optical digital associative information technology. Book 2. M: ALEX, 2003, 100 S. (p.53-87).

1. Optical associative search processor that contains the control unit, the external memory unit local memory unit microprogram control unit memory management, power management processor, wherein the processor entered the optical matrix common system bus, the blocks of the cache memory, the block of multi-channel optical associative correlator, optical blocks in the spatial variables of links for rearranging the words in the page information, blocks of optical logic elements for Boolean logic operations, the optical block input/output signals of the processor, the external line input/output signals of the processor, the internal optical line input/output signals of the processor local bus input/output optical input/output optical bus input/output, optical units decode the input/output signals, a local communication bus matrix with common system bus, and input the s/o of each block of the external memory control, unit firmware management control unit CPU through the respective consistently located and connected by local bus I/o, optical block I/o, optical bus input/output, optical block decoders input/output signals local bus connection with the General system bus optically connected with the optical shared system bus, the inputs and outputs of each block in the local memory unit memory management unit cache memory, the block of multi-channel optical associative correlator sequentially through the respective spaced and connected by local bus I/o, optical block I/o, optical bus input/o optical block decoders input/output signals, optical bus input/output, optical spatial variables of links for rearranging the words in the page information, the optical bus input/output, optical logic elements for Boolean logic operations, local bus connection with the General matrix system bus optically connected with the optical matrix of the total system bus, input/output through which consistently located and associated internal optical line input/output signal processor, the optical block I/o signals to the processor, the optical bus centuries the Yes/o optical logic elements for operations Boolean logic, optical bus input/output, optical spatial variables of links for rearranging the words in the page information is optically connected to the external line input/output signals in the processor.

2. Optical associative search processor according to claim 1, characterized in that the optical matrix common system bus includes a single optical line.

3. The optical processor according to claim 1, characterized in that the optical matrix common system bus includes an optical line addresses, the optical line data, the optical line control.