Device for finding and replacing random strings in text words

FIELD: computer science.

SUBSTANCE: device has string memory block, comparator, memory block for words and substitutes, block for analysis and forming of displacement results, block for storing string address, control block.

EFFECT: broader functional capabilities, higher reliability.

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The invention relates to means for Informatics and computer technology and can be used to solve problems by finding and replacing occurrences in the processed word. The device may find application in the creation of databases, preparation of dictionaries, reference books.

It is known Device for implementing lookup with two occurrences of" (A.S. No. 1667097, 1991, bull. No. 28), allowing to determine the occurrence presented in the word reference.

It is also known Device for sorting numbers" (A.S. No. 1277091, 1986, bull. No. 46), which allows to arrange numbers in ascending and descending order.

It is known Device for morphological analysis of the words of natural languages "business prose" (A.S. No. 1837327, 1993, bull. No. 32), which allows to conduct morphological analysis of the words of real languages, based on the logical characteristics belonging to the classes of the form.

As the prototype is set to "Device search occurrences" (patent No. 2150740, 2000), which allows you to search for occurrences presented in four types.

The task consisted of the following: 1) to extend the functionality of the search engine device; 2) to simplify the algorithm of the control unit; 3) to improve the reliability of operation of the search device random occurrences.

We offer search engine eliminate the STV will significantly expand the functionality which leads to simplification of combinational circuits, devices, and will simplify the algorithm operation.

The solution of the problem is that the device search and replace arbitrary occurrences in the words of the text, containing a block of memory words and lookup block of memory occurrences, the comparator, the storage unit address occurrences, the control unit, characterized in that it further introduced the unit of analysis and the formation of signals of the shift, and the first control input of the control unit are connected respectively with the first control the output of the memory block of occurrences, the second control output of which is connected with the second managing unit of analysis and the formation of signals of the shift and the second is the managing control unit, first to fourth information, the outputs of which are connected respectively with the first on the fourth information input block of memory occurrences, the information output of which is connected to the first information input of the comparator, the control output of which is connected to the first managing unit of analysis and shaping of the signals shift and managing third input of the control unit, from the second to the sixth control outputs which are connected respectively with the third to seventh control inputs of the unit of analysis and the formation of signals of the shift, the first and second management is managing the outputs of which are connected respectively with the fourth and fifth control inputs of the control unit, from the thirteenth to the eighteenth control outputs which are connected respectively from the thirteenth to the eighth control inputs of the unit of analysis and the formation of signals of the shift information, the output of which is connected with the information input unit of storage addresses occurrences, from first to sixth control inputs which are connected respectively with the seventh through twelfth control outputs of the control unit from the nineteenth to the twenty first control outputs which are connected respectively with the first through third control inputs of the memory block of words and lookup first to fourth information inputs which are connected respectively with the fifth-eighth informational outputs of the control unit, the sixth control input of which is connected to control the output block of memory words and substitutions, the second information, the output of which is connected with the information input control unit, a first control output of which is connected with the control input of the memory block occurrences, the first data output of the memory block of words and lookup connected with the second information input of the comparator, seventh and eighth control inputs control unit "RESET" and "START" are respectively an external input device.

BPV - block is used to store the occurrences with which the need is about to conduct a search operation.

MTBF - block is used to store words that will be used to define entry and to store the lookup, which will be replaced when a match is found.

COM - used for comparing characters processed words with the letters of the entry.

BATS - block is used for signal comparator to detect occurrences and formation signals shift, and determining the address (position) of occurrences in the processed word.

BHAVAS - block is used to store memory addresses occurrences.

BOO - block is used to control the device.

The processes of searching for occurrences of the pattern in the processed word adequately described in terms of the language of regular expressions through the use of iteration operations and conjunctive sequence (concatenation) [1].

Of particular interest is the structure of the samples, since the sequential search positions occurrence of a pattern in the processed word can be a disaster skip entry if there is a duplicate fragment at the beginning of the sample and, respectively, the n-fold repetition of the above fragment in the processed word when viewing it from left to right. In addition, the repetition of the initial fragment in the structure of the sample leads to a sharp decrease in the speed of finding the position of occurrence of a pattern in the processed word because of the need to perform m the divine indents (backtraking) in the space of processed words in his constructive linear representation.

When implementing technical solutions need to organize search positions occurrence of a pattern in order to achieve high speed search, and also to eliminate the emergency passes the desired position. To ensure the search in various operating modes. You need to determine occurrences that have the same parts and occurrences do not have common parts. The search procedure which meets the requirements will be called correct.

When performing search functions in words, occurrences can be represented by six different combinations of the letters in the word reference.

1) there is no repetition of the same letters (iteration) in the word-sample, example, "train";

2) repeat the same letters in the middle of the processed words, example - "timioara", called T{S}K;

3) iteration exists at the end of the word, example "terminii", the notation T{S};

4) iteration in the processed word exists in the beginning of a word, an example would be the occurrence of "Lemar", the symbol {S}F;

5) iteration in the processed word is present at the beginning of words and at the end, example - "themmmm", the symbol {S}D{S};

6) the processed word consists entirely of iterations, example -"www", the symbol {S}.

From the first to the third alternative representation of the processed words, when there is no iteration iteration eats is in the middle of the processed words and iteration exists at the end of words, you must search for occurrences of the word to produce the beginning of the word with the first letter. Characters processed words are also read from the beginning, i.e. with the first letter.

The fourth case representation of the processed words, when the iteration is at the beginning of the entry, search must be made with the end of a word, i.e. with the last letter. The word when it is read from the register words in reverse order - the last letter - the first, penultimate is the second and so on, the first letter is the last. The occurrences of symbols are read in exactly the same order, i.e. in reverse.

The fifth case, when the iteration and at the beginning and at the end of the processed words, the search in the present device is carried out from the beginning of the word. But preliminary analysis of the occurrences of the search block iterations of the device. The entry is divided into two parts:

1) only iteration, i.e., the part consisting of the same characters;

2) the rest of the entry, but without iterations at the beginning of the processed words.

The sixth case, the processed word consists entirely of repetitions of the same letters of iterations, then search device search universal occurrences is the beginning of the word with the first letter.

It is necessary to consider the cases when the iteration is not only one letter, but several alternate characters, such as handling emoe the word has the form: babababoo. First words recorded iteration, consisting of different letters AB and such repetitions in example - 4. Such iteration will name two. It is easy to give examples of three, four, five and n-letter iterations. At the end of the processed word ends with a final iteration, but from the same letters. At the end of words can also be mnogobukvenny iteration. To search for different types of words, consisting of various iterations obviously need to develop complex patterns of selection that determine the appearance of iterations. Then depending on the type of iteration is chosen, the algorithm performs a search operation. The aim of the invention is the creation of a search device that searches for occurrences in the processed word with any kind of iterations without complex breeding schemes, as well as functioning in two independent modes with the replace operation.

The algorithm of functioning of the device is as follows. In the case of words is processed word. In the case of occurrences recorded occurrence of the chain of characters. The task of the device is in the definition of occurrence in the processed word. If an entry is found, its address is recorded in the memory device. If an entry is not found, then in the case of processed words written a new word for undertaking the Oia search operations. The comparison in the comparator character is alphabetic. At the beginning of the operation signal of the operation mode of the control unit sets the mode of operation of the search device. To the input of the comparator receives one letter from the register of the processed words and from the register entry. If the result of the comparison is positive, then a shift to the left by one digit of information in both registers and to the input of the comparator receives the next character from the registers. Perhaps there is a situation, when a positive comparison will occur on the first letter, second, third and so on, but the letter k the result of the comparison is negative and thus the end of the word-sample will not be detected. BCD counter device counts the number of positive comparisons. Say them occurred k matches, and k+1 negative result is obtained. In this case, there is a shift to the right by k-1 bits of the register that stores the processed word. Is the "Erasure" of the first letter of the series, where there was a positive comparison. Further comparison will be made, starting with the second letter of the processed words and the first letter of the entry. The entry will be overwritten from the memory of the occurrences. Procedure shift is possible with the use of reversible registers that perform DM is IG information as to the left, and to the right. Search the device operates in two modes. The first mode of operation is to determine the occurrences that have common parts. This means that the previous entry and next have a common part, consisting of a single letter or character strings. Here is an example.

smaaaaaaaall - processed word

AA - occurrence.

After conducting a search operation in the search mode with the common parts have four occurrences of 1. The second format of the system is characterized by the definition of occurrences that do not have common parts. In this case, the address is determined only after n shifts, where n is the number of letters in the register entry. If you want to replace the found occurrences of the substitution of a letter or a word, a predetermined and recorded in the register lookup. In this case, first, the operation of the search listings without the common parts, then the operation to replace the found occurrences of the substitution. After conducting a search operation in the search mode without the common parts have two occurrences, 2.

If you want to perform a replace operation, say, for example the substitution of a shooting range, then the result is converted processed word, Fig.3.

1 shows a structural diagram of a device search and replace arbitrary occurrences in the words of the text.

On IG option presents the technical implementation of the block of memory occurrences.

Figure 3 shows a variant of the technical implementation of the block of memory words and lookup.

Figure 4 shows a functional block circuit analysis and generation of signals of the shift.

Figure 5 shows a block diagram of the storage unit address entry.

Figure 6 - conceptual GAW operation.

7 - tagged GAW operation.

The device search and replace arbitrary occurrences in the words of the text (figure 1) contains the block 1 of memory occurrences, the comparator 2, block 3 memory words and lookup block 4 analysis and generation of signals of the shift block 5 storage address listings, block 6 of the control device.

To describe the algorithm unit 6 controls the following identifiers are used.

1. PRKV - terminator occurrences. This can be a binary code is equal to 11...1.

2. PRX - a sign of the end of the word. Equal to 11...1.

3. CU - command, specifying the end of the operation.

4. SU - control signals for the shift register memory block occurrences (signals recording, receiving, issuing data).

5. SUR - control signals for the shift register RG OWN block of memory words and lookup (signals recording, receiving, issuing data).

6. SDV - team shift coming from the control unit to the input shift register of the block of memory occurrences.

7. SDS - command shift coming from backupsonline to the input of shift register RG OWN the processed words of the block of memory words and lookup.

8. SOUP - team management account, issuing, storing data in RAM memory block occurrences.

9. URR - team management account, issuing, storing data in RAM memory words of the memory block of words and lookup.

10. HELL - address data in the RAM issue and write memory block instances.

11. HELL - address data in the RAM issue and write a block of memory words and lookup.

12. DN - data recorded in RAM (the binary codes of the characters) block of memory occurrences.

13. BPS - data recorded in RAM (the binary codes of the characters) block of memory words and lookup.

14. SSR signal of the comparison received from the comparator.

15. SYN - synchronization command at the input of the binary counter SC unit of analysis and signal shift from the control unit.

16. OBN - command reset binary counter SC unit of analysis and signal offset.

17. SVA - command issuing addresses the occurrence of the unit of analysis and generating signals shift in the storage unit address entry.

18. SSS - team of the write-enable a trigger Tr unit of analysis and generation of signals of the shift output signal from the comparator.

19. NLL - command coming from the control unit, an opening or locking the electronic key AND DD22 unit of analysis and signal offset.

20. SN - command sync binary counter SC unit of analysis and fo is a strong signal of the shift.

21. WITH the command reset binary counter SC unit of analysis and signal offset.

22. PIM - rectangular pulses on information input electronic key AND DD22 unit of analysis and signal offset.

23. ADST address columns to record occurrences in the storage unit address entry.

24. Adstr address lines to record occurrences in the storage unit address entry.

25. GIVING data address entry.

26. AVH address entry.

27. VDV is the output of the block memory occurrences.

28. GVA - output data words of the block of memory words and lookup.

29. DS - data - processed words.

30. DV data entry.

31. WHEN rectangular pulses coming from the side of the control information to the input of logic element AND DD25 unit of analysis and signal offset.

32. SO - rectangular clock pulses supplied to the information input of logic element AND DD19.

33. SVP - team, determines the number of shifts to the right register RGsB DD.13 block of memory words and lookup.

34. DSE command defines the binary code 0001 (unit) output of a binary counter SC DD.20.

35. GI is the generator of impulses from the control unit to a summing input (+) of the binary counter CQ Article DD.28 block storage address entry.

36. TI - TA is preset pulses, coming from the control unit to a summing input (+) of the binary counter Midrange Page D.29 block storage address entry.

37. Reset - command reset binary counter CQ Article DD.28 block storage address entry.

38. BTS - command reset binary counter CQ P DD.29 block storage address entry.

39. SC/St command read/write operational storage device RAM of the storage unit address entry.

40. VK - command chip select operational storage device RAM of the storage unit address entry.

41. PP - command of an indication of the mode of operation of the system.

42. SRP - sign blank (no data)" operational storage device of the processed words of the block of memory words and lookup.

43. The RAF team a characteristic operation of the system in different modes.

44. PZ indication of device operation - search and replace or just to search.

45. Pus is a sign blank (no data)" operational storage device lookup block of memory words and lookup.

46. SPT - information signal consisting of signals of the STS and the SRP - indication "empty" operational storage devices RAM lookup and processed words.

47. SDS - control signal shift information to the left or right of the register RG PUFF memory block of words and lookup.

48. SDP - control signal of the shift information and the left register of the WG UNDER the block of memory words and lookup.

49. UNDER - the data lookup - output information from the memory RAM POD lookup.

50. ZAM data replacement - output information register lookup WG UNDER, the replacement is carried out in the case when the device operates in the mode of search and replace.

51. SIMS - output register buffer WG BOOTH is fed to the input register of the processed words RG OWN block of memory words and lookup.

52. Control commands control recording, issuing, storing data in RAM lookup block of memory words and lookup.

53. The BPA - address data in RAM lookup - issuing and recording information of the block of memory words and lookup.

54. Data recorded in the RAM lookup (binary codes of the characters) block of memory words and lookup.

55. SIG - control signals for the shift register of the WG UNDER the block of memory words and lookup (signals recording, receiving, issuing data).

56. SGU - control signals for the shift register RG PUFF memory block of words and lookup (signals recording, receiving, issuing data).

57. SIU - information signal consisting of control signals UPR and URR random access memory RAM POD and random access memory RAM PS.

58. ADR - information signal consisting of address signals DT and HELL random access memory RAM POD and random access memory device is STV RAM PS.

59. DSP - information signal consisting of data GIVEN and BPS operational storage devices RAM POD and PS.

60. SUPR - information signal consisting of control signals SGU, SUR and SIG (signal recording, receiving, issuing data) registers buffer WG BOOTH processed words WG FDS and lookup the WG UNDER.

The algorithm of the control device.

Meaningful GSA control is shown in Fig.6 and reflects the operation unit 6 of the control (figure 1).

The signals U" and "START" (blocks 2,4-graph-scheme of algorithm (1) is setting to zero all elements of the memory device, the command "RESET=1" (block 3).

In block 5 of the algorithm is to download words-samples for carrying out search operations. Team-PV:=SOUP supplied to the input of operational memory (RAM) PV DD8 block 1 of memory occurrences (BPV) control signals for recording information in RAM. Team-PV:=AD served the address inputs for recording data in RAM. Team-PV:=DN is fed to the inputs of RAM data write (2).

In block 6 of the algorithm loads of words for search operations. Team PS:=YPP supplied to the input of operational memory (RAM) PS DD14 block 3 memory words and lookup (MTBF) control signals for recording information in RAM. Team PS:=ADA serves the address I is dy to write data in RAM. Team PS:=BPS is fed to the inputs of RAM write data (figure 3).

In block 7 of algorithm analyzes the mode of the device - team PZ. If the device is operating in the processing mode of the character information search and replace - output YES, it means that the detection of the occurrence of the processed word is carried out on pre-recorded substitution - a string of characters. In this case, the transition is performed in block 8 of the algorithm. If the device works only in search mode, the output from the block - NO, it means that the address detected in the process of searching for occurrences will be recorded on the appropriate addresses of rows and columns in a memory device (figure 5). In this case, the transition is performed on block 9 of the algorithm.

In block 8 of the algorithm loads a lookup in memory POOL for carrying out the replacement operation of the control unit. In memory of the lookup RAM POD DD15 is recorded character information composed of a chain of letters is GIVEN. The team POD:=SIMP supplied to the input of operational memory (RAM) POD DD15 block 3 memory words and lookup (MTBF) control signals for recording information in RAM. The team POD:=DT serves the address inputs for recording data in RAM. The team POD:=DAN is fed to the inputs of RAM data write (3. On exit from the block 8 of the algorithm goes to block 13 of the algorithm.

In block 9 of the algorithm is the supply of control signals verses from the control unit to the input of the register words RGsB DD13 command RGsB:=SUR. Team Lbuf:=SSU input register buffer Lbuf DD11 served control signals SGU from the control unit to permit recording of information from memory PS and PPD respectively (figure 3).

In block 10 of the algorithm is an entry in the register of the words from the word memory word reference RGsB:=DS, in the case of occurrences written from memory of occurrences of a sequence of letters (entry) System:=DV. D - Trigger Tr DD16 unit of analysis and signal shift is set to "0" TR:=0. These commands are pre-loading device (figure 2, 3, 4).

In block 11 of algorithm command add:=0 and SDS:=0 generated shifts to the left by one digit of information held in registers respectively System DD7 and RGsB DD13 blocks 1 and 3 (figure 2, 3).

In block 12 of the algorithm is the analysis of the mode of operation of the unit of analysis and generating signals shift - command PP. If the command PP is equal to zero, it means that the search device is operating in the search mode of occurrences with the common parts (figure 1) is a transition in block 15 of the algorithm. If PP is equal to the unit, the unit is operating in the search mode of occurrence, not the actual operation of the common parts (figure 2), this will navigate to the block 13 of the algorithm.

In block 13 of the algorithm at the command of the RAF:=0 the output signal of the logic element DD26 unit of analysis and signal shift is set to the zero state. In this case, the logical elements DD25 and DD18 the specified block will be closed. The outputs of these elements will be zero status.

In block 14 of the algorithm on the team PIF:=0 input register words RGsB DD13 block 3 memory words and lookup the signal from unit 6 of the control device is equal to zero. This is a shift of the information in this register by one digit to the left.

In block 15 of the algorithm at the command of the RAF:=1 the output signal of the logic element DD26 unit of analysis and signal shift is set in one state. In this case, the logical elements DD25 and DD18 the specified block will be opened. The outputs of these elements will be the signal WITH rectangular pulses coming from the unit 6 to control the operation of the search device.

In block 16 of the algorithm on the team PIF:=SVP at the input of the register words RGsB DD13 block 3 memory words and substitutions are served rectangular pulses SVP, whose number is one less than the number of signals received at the summing input of the counter SC DD20 unit 4 analysis of the signal shift. In this case, the arrival of cadogans SVP is a shift of the information in this register to the right by one digit.

In block 17 of the algorithm is the analysis of the signal comparison SSR received from the output of the comparator COM DD2 (figure 4). If SSR=1, there is a coincidence of occurrences of letters from a word. In this case, the transition is performed in block 18 of the algorithm. If SSR=0, then a match has not occurred and the transition occurred on block 23 algorithm.

In block 18 of the algorithm on the input D-T trigger DD16 unit 4 analysis and signal shift signal SSR from the comparator COM 2 DD2 (figure 4) TR:=SSR. The trigger set to the one state. This means that the input symbols at the input of the comparator are equal.

In block 19 of the algorithm on the team SSS:=1 from the control unit is write permission on the D - trigger information from the output of the comparator. Team TR:=1 D - flip-flop unit 4 analysis and generation of signals of shift is set to one. At the summing input of a binary counter So this block receives the clock pulses SC:=TRUE. The counter counts the number of coincidence in the comparator (figure 4).

In block 20 of the algorithm is giving signals to the control SIGNAL from the control unit to the input of the register lookup Gpod DD12 command Lpod:=SIG to write characters from a register of the processed words RGsB (figure 3).

In block 21 of the algorithm is an entry in the register lookup Gpod DD12 from the register of the processed words RGsB is ingelow GVA command Lpod:=GVA (figure 3). In this case, there was a concurrence of input values to the comparator input.

In block 22 of algorithm command PIF:=0, add:=0, SDP:=0 is formed by the left shift information held in registers respectively RGsB DD13 block 3 memory words and lookup System DD7 block 1 memory usages, Gpod DD12 - register lookup block 3 memory words and substitutions. This will navigate to the block 26 of the algorithm.

In block 23 of algorithm analyzes the contents of the D - flip-flop Tr DD16 (Fig 4). If Tr=0, then this means that a match at the previous step was not, in this case, a signal of a left shift by one bit in the block 3 memory words and lookup register RGsB DD13. If TP=1 then transitions to block 36 algorithm.

In block 24 of this algorithm is the control signal SGU from the control unit to the input of the register buffer Lbuf DD11 team Lbuf:=SGU to write characters from a register of the processed words RGsB DD13 (figure 3).

In block 25 of the algorithm is formed by a team of PIF:=0 shift to the left by one digit information from the register Gssab in case Lbuf block 3 memory words and substitutions (figure 3). This Lbuf:=GVA output of the GVA of the register RGsB is overwritten in the register Rxbuf. On the vacant seat in case RGsB recorded the next symbol is processed words from unit 3 memory words and lookup RGsB:=DS.

the block 26 of the algorithm at the command of SS:=0 from the control unit is formed by the control signal, when the left-shift information in the register Lbuf DD11 on one digit to the left of the block 3 memory words and lookup for entry of the next character from register RGsB (figure 3). This will navigate to the block 36 of the algorithm.

In block 27 of the algorithm on the team Lbuf:=SGU signals control SGU from the control unit to the input of the register buffer Lbuf DD11 to write characters from a register lookup Gpod DD12. The team Lpod:=SIG is giving signals to the control SIGNAL from the control unit to the input of the register lookup Gpod DD12 for the issuance of characters from the register lookup Gpod in the register buffer Rxbuf. Team DCS:=0 from the control unit is formed by a control signal, which is the left-shift information in the register Lbuf DD11 on one digit to the left for entry of the next character from the register lookup Gpod DD12. Team SDP:=0 is formed by a left shift of information contained in the register Gpod DD12 block 3 memory words and substitutions. As a result of running these commands all information from the register lookup Gpod will be written to the register buffer Lbuf (figure 3).

In block 28 of the algorithm on the team Lbuf:=Lpod in the register buffer Lbuf characters will be transferred from the register lookup Gpod. These commands will overwrite the information from Lpod in Lbuf (figure 3).

In block 29 is analiziruetsya the state of the binary counter SC DD20 unit 4 analysing and generating signals shift. If the state counter is less than or equal to one, then transitions to the block 33 of the algorithm. If the condition is true, i.e. the value of the counter SC greater than one, then the transition occurs at block 30 of the algorithm.

In block 30 of the algorithm is formed by filing a rectangular pulse of unit 6 control - WHEN the subtractive input of a binary counter SC DD20 unit 4 analysing and generating signals shift. Team SVP:=1 in the counter is the algebraic subtraction unit until the state of this counter is not equal to a single value SC:=IF (figure 4).

In block 31 of the algorithm is formed by a shift to the right and rewriting of information from the register Rxbuf in case RGsB block 3 memory words and substitutions. Commands from the control unit SBC:=1 and SDS:=1 information from the register Lbuf shifted by one digit to the right in case RGsB. The team RGsB:=SUR is the resolution of the operations of the shift unit 3 memory words and substitutions. Information from the register Lbuf shifted into the register RGsB until the counter SC DD20 will not be equal to one (figure 4).

In block 32 algorithm on the team RGsB:=Rxbuf in the case of processed words RGsB DD13 will be transferred characters from the register buffer Lbuf DD11. These commands will overwrite the information from Rxbuf in RGsB (figure 3).

The blocks 29, 30, 31, 32 al is aritma form a cycle. The exit from the loop is the condition under which the value of the counter SC will be equal to one. On exit from the block transitions to the block 33 of the algorithm.

In block 33 of the algorithm on the input of the register entry System block 1 of memory occurrences of the control block 6 receives control signals System:=SU. As a result, in the case of occurrences of the recorded information from the memory of the occurrences of the System:=DV (figure 2).

In block 34 algorithm register listings RGsB receives information from the register Lbuf RGsB:=Lbuf (figure 3). The processed word is shifted to the right by n-1 bits, where n is the number of shifts to the left of the same word.

In block 35 of the algorithm at the command UPD:=1 is the count SC DD20 unit 4 analysing and generating signals shift. Binary counter SC DD20 take the value zero SC:=0. The output of the block is transition to a block 36 of the algorithm.

In block 36 of the algorithm is the analysis of terminator occurrences PRCV (figure 2). If PRCV=1, in case of occurrence of the detected binary code 11...1. In this case, the entry found in the word-sample and block storage address of occurrences recorded address occurrence (figure 5). If PRCV=0, it means that the comparison is on the letter, but not all occurrences of letters still viewed, this will navigate 42 block algorithm.

In block 37, the algorithm analyzes the PE the ima device - team PZ. If the device is operating in the processing mode of the character information search and replace - output YES, it means that the detection of the occurrence of the processed word is carried out in the register lookup Gpod on pre-recorded in the register of substitution - a string of characters. In this case, the transition is performed in block 38 of the algorithm. If the device works only in search mode, the output from the block - NO, it means that the address detected in the process of searching for occurrences will be recorded on the appropriate addresses of rows and columns in a memory device (figure 5). In this case, the transition is performed on the block 41 of the algorithm.

In block 38 of the algorithm at the command of Lpod:=SIG is giving signals to the control SIGNAL from the control unit to the input of the register lookup Gpod DD12 to write characters from memory lookup POD DD15. The team Lpod:=UNDER the register lookup Gpod DD12 writes letters lookup from memory lookup POD (figure 3). As a result of running these commands in the register lookup Gpod will be recorded information from the memory lookup POD.

In block 39 of the algorithm on the team Lbuf:=SGU is control signals SGU from the control unit to the input of the register buffer Lbuf DD11 to write characters from a register lookup Gpod DD12. Team SDP:=0 is formed by the left shift info is rmacie, in the case Gpod DD12 block 3 memory words and substitutions. Team DCS:=0 from the control unit is formed by a control signal, which is the left-shift information in the register Lbuf DD11 on one digit to the left for entry of the next character from the register lookup Gpod DD12.

In block 40 of the algorithm on the team Lbuf:=Lpod is write data in the register buffer Lbuf DD11 from the register lookup Gpod DD12. As a result of running these commands blocks 38, 39, 40 all information from the register lookup Gpod will be written to the register buffer Rxbuf. Thus will be realized the substitution of symbols in place of the detected occurrence of GVA (figure 3). Operation search and replace is performed only when the device is in the search mode occurrences without the common parts. The output from this block is moving to block 42 of the algorithm.

In block 41 of the algorithm is the address record in the storage unit address listings. On the control input of an electronic key CL DD24 unit 4 analysing and generating signals shift permissive signal is received from the control block 6 - CBA, CL:=CBA. Information from the output of the binary counter SC DD23 through public key CL DD24 fed to the input of operational storage device RAM DD30 (figure 4, 5). The enable signal for recording information supplied from the block 6 upravleniya/Po:=0, VK:=0. On control inputs received zero values, which corresponds to the recording mode in the RAM device input information, i.e. address entry - AVH RAM:=AVG.

In block 42 of the algorithm is the analysis of the sign of the end of a word PRX (an attribute is binary, equal to all the units 11...1). If PX=0, then the search process will continue and this will navigate to the block 17 of the algorithm. If the detected sign of the end of the word PRX=1, then it moves on to the block 43 of the algorithm.

In block 43 of the algorithm is the analysis of the sign "empty" RAM words - SRP unit 3 memory words and substitutions. If the SRP is equal to zero, then transitions to block 9 of the algorithm. In this case, the word memory block 3 memory words and lookup features (words)that will need to conduct the search and replace operation, i.e. the process will continue. If the SRP is equal to one, it means that all the words in the word memory block 3 memory words and lookup viewed. In this case, the transition is performed on the target block 44 of the algorithm. In the operation of the search device is shutdown.

The block 44 of the algorithm is the final block.

The device search random occurrences is as follows.

External control signals "START" and "RESET" enter in block 6 of the control. In operational Zap minuses device unit MTBF recorded words of arbitrary text, in which you want to detect occurrences. Under the occurrences refers to a symbol or string of symbols (including words)that you want to find in words unit MTBF. Occurrences are in operative memory unit BPV. In block comparison (comparator) sequentially comparing each letter of the occurrences of symbols processed words. In unit 4 analysing and generating signals shift is processed by the signal comparing characters received from blocks MTBF and BPV, and analyzes the signal from the control unit that sets a mode of the device - PP. If the entry found in the word, it generates the address (position) of the occurrences of the word. Detected occurrence is in the register Gpod DD12 block 3 memory words and substitutions. If the user selected mode of search and replace, in case Lpod from memory lookup replaces occurrences of the wildcard string of symbols. After a transaction lookup information from the register Gpod DD12 is overwritten in the register Lbuf DD11 block 3 memory words and substitutions. Case Gpod when this is released for further search occurrences in the processed word. If you have selected only the search, the address entry is recorded in the RAM unit 5 storage addresses. The address is stored in the storage unit 5 addresses. If the comparison n what happened, the generated signals shift SDS, SDS in the block BO received at the input blocks MTBF and BPV. If the device occurs a situation in which you received the first positive results of the comparison in the comparator, and then the negative sign of the end of entering another neobsahuje. In this case, will be found only a few characters of the entry, but not all the entry completely. With a positive result in the comparator shifts to the left by one position information register RGsB DD13, in which the word is located. The word from register RGsB DD13 by letter goes in the case Gpod DD12. A binary counter is counted positive series of comparison in the comparator. In case of negative result of the comparison is the transcribing of information from the register lookup Gpod DD12 in the register buffer Lbuf DD11. Then register Lbuf DD11 characters are overwritten in the register words RGsB DD13. The number of shifts to the right will be less by one than the number of shifts to the left. The process of search will be continued, but with the second letter of the fragment, where it was found a positive series of matches in the processed word. The first letter in this case as "deleted". The process continues until you have found all occurrences and implemented the replacement operation in the processed word.

Block 1 memory and occurrences contains random access memory (RAM) - memory occurrences DD8, reversible shift register System DD7 (register occurrences), which will be stored entry, the logical element AND DD9 to detect terminator occurrences. The control signals SOUP is the resolution of recording information on the address inputs AD recorded data DN in RAM (memory occurrences) of unit 6 controls (figure 2). Output memory occurrences information DV is fed to the input of the reversing register of occurrences of System DD7, the control signal SU from the control block 6 is write letters entry in the register of occurrences. The signal shift occurrences of add from the control block 6 is fed to the input of the reversing register occurrences (figure 2). The output of the reversible register occurrences VDV is fed to the input of the comparator COM 2 (figure 1). Reversible register System DD7 shift in any direction: left to right or Vice versa. The right shift is performed when the value of the signal SDV=1, the left shift is when add=0, i.e. the direction of the shift by one control signal [3, 4]. Element AND DD9 generates a signal terminator occurrences PRCV equal to the unit (all units at the entrance). In memory of occurrences of the signal is formed CU - end, if the RAM is empty. Before working device in the memory of the occurrences recorded all occurrences in the register of occurrences is the first occurrence, the signal characteristic is the rates of occurrences of PRCV equal to zero, the signal shift occurrences add to zero.

The comparator 2 is a device comparison for equality of input values: output occurrences airborne unit 1 BPV and output data words GVA unit 3 MTBF (figure 1). If the input signals are equal, then the output of the comparator is formed of a single signal SSR. Otherwise, the SSR will be zero. The output signal of the comparator to the input of the control block 6 and to the input unit 4 analysing and generating signals shift (figure 1).

Unit 3 memory words and lookup contains operational memory (RAM) memory words DD14, reversible shift register RGsB DD13 (register words)in which is stored the processed word, operative memory (RAM) - memory lookup DD15, reversible shift register Gpod DD12, which will be stored symbols processed words in the case of a positive comparison, the reversible shift register Lbuf DD11, the logical element AND DD10 is designed to detect signs of the end of a word PRCS. The control signals URR is the resolution of recording information on the address inputs HELL written BPS data in RAM (memory words) of unit 6 controls (figure 3). Output word memory information DS is fed to the input of the reversing register words RGsB DD13, the control signals verses from the control block 6 is SL the VA in the reversible case the words RGsB DD13. The signal shift words SDS from the control block 6 is fed to the input of the reversing register words RGsB DD13 (figure 3). The output of the reversible register words RGsB DD13 is fed to the input of logic element AND DD10, and also to the second input of the comparator COM DD2, to the information input of the register lookup Gpod, to the information input of the register buffer Rxbuf. Information to the input register of the processed words RGsB DD13 receives output information from the register buffer Lbuf DD11. Element AND DD10 generates a signal characteristic of the end of a word PRX equal to the unit (all units at the entrance). Before working device in the memory of the words of PS DD14 recorded all the words, in the case of processed words RGsB is the first word, the signal terminator words PRX equal to zero. If the output of the comparator KOM will be generated signal comparison SSR equal to one, the signal shift PIF will be zero in this case will be generated signal left shift the data by one digit. Information from the register RGsB DD13 will be shifted one character to the left. This symbol will pass on the information signals SIG in case Gpod DD12. The process left shift will continue until, until there is obtained a negative result of the comparison in the comparator COM DD2 or not detected occurrence of the word. For example, suppose you recorded 5 shifts to the left, and the ATEM received a negative signal comparison SSR, is equal to zero. In this case, all information from the register lookup Gpod will be copied into the register buffer Lbuf, under control of signals shift: SDP and SDS of zero. After that, the control unit 6 will be formed signals of a right shift of the signals of the shift SDS and SDS will be equal to one. Information from the register Lbuf DD11 will be shifted to the right by one character less than the left, in this case 4. In this case, the second letter of the word to be processed first in the register RGsB DD13, the process of the search will continue. The four letters of the register Gpod DD12 will go first in the register Lbuf DD11, and then transferred in register RGsB DD13, if the selected mode of the device search and replace. If the selected mode search with memory addresses in RAM DD30, in this case information from the case RGsB DD13 will be overwritten in the register buffer Lbuf DD11. The operating modes of the device will be formed with control signals: SUR, WHITEFISH, SGU from the control unit.

Unit 4 analysis and signal shift contains a comparator COM DD2, D - trigger Tr DD16, two-input logic element AND DD17 with an inverted input of two-input logic element AND DD19, two-input logic element AND DD22, trekhgolovy logical element AND DD18 with inverse sign, chetyrehuhogo element AND DD21 with inverted inputs, Trahunt the first element AND DD27 with inverse sign, electronic key DD24, binary counter SC DD20, binary counter SC DD23, input element OR with inverted inputs DD26, input element AND DD25. Before you begin the device binary counters DD20, DD23, and D - trigger Tr is set to the zero state. Unit 4 analysis and signal shift processes the output signal SSR from the comparator COM DD2. If the signal SSR is equal to one, it means that there was a coincidence of the binary code symbol occurrences in binary code letters of the word. In this case, D - trigger Tr DD16 upon arrival of the unit 6 control enabling signal SSS equal to one, set in one state. The logical element AND DD19, performs the function of an electronic key, unlocked, clock pulses from unit 6 control come on summing (+) input of a binary counter SC DD20. In the binary counter SC DD20 is the sum of clock pulses, whose number corresponds to the number of matches in the comparator COM. The output of the binary counter SC DD20 is formed binary code corresponding to the number of positive matches in the comparator. For each positive match in the comparator is formed of signals shift left and add SDS equal to zero, and shifted one character to the left in registers System DD7 block 1 of memory occurrences and reg is shooting RGsB DD13 block 3 memory words and substitutions. Register Lbuf DD11 block of memory words and lookup writes each character received from the register RGsB DD13, if the comparison has not occurred. In the case of terminator occurrences PRCV equal to one, the logical elements AND DD9 block 1 of memory occurrences are defined address entry and recording the corresponding address entry in the operational storage device RAM DD30 unit 5 storage addresses occurrences. If the sign of the end of a word is not found PRX=0 (zero), then the previous occurrence is restored, i.e. repopulated from the memory of the occurrences and the process of searching for occurrences of the word continues (in the case of multiple occurrences of one word). If coincidence in the comparator COM does not occur, the output signal SSR is equal to zero, it generates only the signal SDS is equal to zero, and a shift to the left by one position information held in the register words RGsB DD13 block 3 memory words and substitutions. Each left shift and the negative result of the coincidence in the comparator of the memory words of PS overwritten (appended) symbol in the memory register words RGsB DD13 block 3 memory words and substitutions. It is possible in the search operation, when it received a positive result of the comparison characters, then formed a left shift by one digit registers RGsB DD.13 and Gpod DD12. Polendvica received the second time a positive result, the third, and so on, but terminator entry yet. Suppose n step obtained a negative result of the comparison, and the occurrence is not fully discovered. In this case, D - trigger Tr DD16 was installed in the state unit, i.e. at the output of the element unit. In the next step, the signal comparison is equal to zero SSR=0. The output of the logical element AND DD17 will be formed of a single signal. The logical element AND DD18 will also be open, rectangular pulses from unit 6 management will be transmitted to the subtractive input of a binary counter SC DD20. Subtraction occurs until the output of the counter is not binary equal to one. On the positive input of the counter rectangular pulses from the control block 6 will not be received, because the logical element AND DD19, performs the function of an electronic key will be locked established in the zero state of the D trigger DD16. The logical element AND DD21 plays the role of a decoder unit. The output of this element is equal to unity in the case of obtaining the output of the counter SC DD20 binary code 0001. For all other combinations at the output of this element will be condition zero. When the unit output of this element logical element AND DD18 locked, because the unit is supplied to an inverse input. Rectangular pulses to the subtractive input of the counter SC DD20't do that. Counter SC DD20 is set to zero coma the DOI OBN, coming from the control block 6. The logical element AND DD27 performs the role of a "valve"that form the number of shifts to the right register RGsB DD13. Every time there is a subtraction unit from the contents of the counter SC DD20, is moving to the right information from the register Lbuf DD11 in case RGsB DD13. The number of shifts to the right will be one less than the number of shifts to the left. In our example, n-1. The second letter from the received series of positive changes will be first in the register RGsB DD13. The entry will be rewritten from memory occurrences in the register of occurrences of System DD7. The search process will continue. The logical element OR DD26 performs the detection operation mode. As you know the system works in two independent modes: definitions of occurrences with the common parts and identify occurrences and without (intersections) of the common parts. In the first case, the characteristic mode of the RR will be zero. In the second case, the sign of PP equal to one. The logical element AND DD25 performs the function of an electronic key. In the case when the characteristic operation of the system PP is equal to zero, the output element OR DD26 will always be one. Electronic key DD25 will be opened. The rectangular pulses from unit 6 of the control unit via the public key received at the third input of logic element AND DD18. This mode is characterized by what relocation information from the register Lbuf DD11 in case RGsB DD13 on n-1 bits, i.e. generate a return of information, where n is the number of positive shifts, whenever it is discovered occurrence in processed word in this terminator occurrences PRCV will be equal to one. If the system mode will be set as the search without the common parts, in this case, RR is equal to one. In case of detection of occurrence, while the sign of occurrences PRCV equal as one. The output of logic element OR DD26 set to zero. Electronic key AND DD25 will be locked. The rectangular pulses from unit 6 of the control unit will not be sent to the input element AND DD18 (figure 4). Information from the register Lbuf DD11 not to move in case RGsB DD13. In this case, is formed by the left shift of characters from the register RGsB DD13 in case Gpod DD12, i.e. return information will not (figure 3).

Terminator device SRP equal to one, can be formed when all occurrences viewed, in memory of occurrences of no information and memory of the words of PS is also empty. If the SRP is equal to zero, the register of the word RGsB DD13 block 3 memory words and lookup MTBF receives new information (new word) of memory words (figure 3).

Unit 5 storage addresses occurrences BHAVAS contains operational storage device RAM DD30 binary counter that generates addresses of columns of RAM - MF article D28, a binary counter that generates addresses of the rows of RAM - MF p DD29. Binary counters at the beginning of the operation of the device reset control signal reset, the line coming from the control block 6. The inputs of the counters arrive rectangular pulses KI-TI from the control block 6. Counters form the addresses of rows and columns, which will be written to address occurrences at the input of operational storage device RAM DD30, if the selected device mode only search listings. The control signals operative storage device RAM DD30 read/write and chip select, respectively, when recording take values MF/St=0, VK=0 (figure 5).

The control block 6 is synthesized on the basis of GSA control algorithm (6) in a known manner [3, 5]. Tagged GSA unit 6 of the control shown in Fig.7, where indicated:

The logical conditions are true:
X1: "the DOE"X6: "TR"
X2:START"X7: "SC>"
X3: "PZ"X8: "PRCV"
X4: "RR"X9: "PX"
X5: "SSR"X10: "SRP"

Operators:
N1: RESET:=1"U: ”SC=TAK”
the 2: "RO:=SOUP" U: "Lpod=SIG"
U3: "PV:=ADU: "Lpod:=GVA"
A4: "PV-LTOs"U: "SDP:=0"
W: PS:=URR"U: "Lbuf:=Gpod"
W: PS:=ADE"U: "Lbuf:=GVA"
W: PS:=BPS"U: "RGsB:=DS"
U: "POD:=SIMP"U: "SDS:=0"
U: "POD:=DT"U: "SVP:=1"
U: "POD:=DAN"U33: "SC:="
U: "RGsB:=SURU: "SDS:=1"
U: "Lbuf:=SGU"U: "SDS:=1"
U: "RGsB:=DS"U: "RGsB:=Rxbuf"
U: "System=DV"U: "System:=SU
- Y15: "TR:=0"U: "System=DV"
U: "add=0"U: UPD:=1"
U: "SDS:=0"U: "SC:=0"
U: "RAF:=0"U: "Lpod:=UNDER
U: "RAF:=1"U: "CL:=CBA"
U: "SDS:=SVP"U: "MF/Po:=0"
U: "TR-SSR"W: VK:=0"

U: "SSS:=1"U: RAM:=AVH"
U:"TR:=1" 

SOURCES of INFORMATION

1. Kudryavtsev V.B. have been, Podkolzin A.S., accomlish W. Introduction to theory is Yu abstract machines. M.: Moscow University press, 1985. 174 C.

2. Markov, A.A., Nagorno NM Theory algorithm. - Moscow: Science 318 S. Main edition of physico-mathematical literature. 1984

3. POM A., Agrawal O. high-speed memory systems. - M.: Mir, 1987. - 264 FF., Il.

4. Alexenko A.G., Sagarin I.I. Microcircuitry: Textbook. manual for schools. - 2nd ed., revised and enlarged extra - M.: Radio and communication, 1990. - 496 S.: ill.

5. Baranov, S. Synthesis of microprogrammed machines. Energy, Leningrad branch. 1974 - 184 C.

6. Digital and analog integrated circuits: Handbook edited Svechenovskoj. - M.: Radio and communication, 1990. - 496 S.: ill.

7. Patent No. 2150740 (prototype).

8. AS the USSR № 1837327 (similar).

9. AS the USSR № 1667097 (similar).

10. AS the USSR № 1277091 (similar).

The device search and replace arbitrary occurrences in the words of the text, containing a block of memory words and lookup block of memory occurrences, the comparator, the storage unit address occurrences, the control unit, characterized in that it further introduced the unit of analysis and signal shift, and the first control input of the control unit is connected respectively with the first control the output of the memory block of occurrences, the second control output of which is connected with the second managing unit of analysis and waveform generation shift and the second is the managing control unit, from the first to the fourth the fifth the information outputs of which are connected respectively with the first to fourth information inputs memory block occurrences, the information output of which is connected to the first information input of the comparator, the control output of which is connected to the first managing unit of analysis and generating signals shift and managing third input of the control unit, from the second to the sixth control outputs which are connected respectively from the third to the seventh control inputs of the unit of analysis and waveform generation shift, the first and second control outputs of which are connected respectively with the fourth and fifth control inputs of the control unit, from the thirteenth to the eighteenth control outputs which are connected respectively from the thirteenth to the eighth control inputs of the unit of analysis and signal shift information output of which is connected with the information input block storage address of occurrences, from the first to the sixth control inputs which are connected respectively with the seventh through twelfth control outputs of the control unit from the nineteenth to the twenty first control outputs which are connected to first to third control inputs of the memory block of words and lookup first to fourth information inputs which are connected respectively with the fifth to eighth informational outputs of the control unit, the sixth control input of which is connected with the charge of the current output block of memory words and lookup the second information output of which is connected with the information input control unit, a first control output of which is connected with the control input of the memory block occurrences, the first data output of the memory block of words and lookup connected with the second information input of the comparator, seventh and eighth control inputs control unit “RESET” and “START” are respectively an external input device.



 

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