Parallel search and replace system

FIELD: computers.

SUBSTANCE: system has entries memory block, words memory block, control block, substitutions block, n blocks for searching and replacing.

EFFECT: broader functional capabilities.

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The invention relates to means for Informatics and computer technology and can be used to solve problems by finding and replacing occurrences in the processed word. The device may find application in the creation of databases, preparation of dictionaries, reference books.

It is known Device for implementing lookup with two occurrences of" (A.S. N 1667097, 1991, bull. N 28), allowing to determine the occurrence in the presented word.

It is known Device for morphological analysis of the words of natural languages "business prose (A.S. N 1837327, 1993, bull. N 32), which allows to conduct morphological analysis of the words of real languages based on logical signs of belonging to the classes of forms.

You know the "Device search" (patent N 2150740, 2000), which allows you to search for occurrences presented in four types.

As the prototype is set to "Parallel information retrieval system" (patent No. 2195015, 2002), seeking random occurrences in the words of the text.

The task consisted of the following:

1) to extend the functionality of the search engine,

2) to simplify the algorithm of the control unit,

3) to increase the reliability of the search engine.

We offer search system will significantly expand the functions the optional features, which leads to simplification of combinational circuits, systems, and will simplify the algorithm of the parallel system.

The solution is the fact that a parallel system of search and replace, containing a block of memory occurrences, a block of memory words, the control unit, characterized in that additionally introduced: block lookup n blocks search and replace, and first to third information output control unit are connected respectively with the first through third information input of the memory block occurrences, managing the output of which is connected to the first Manager of the input control unit, the second control input of which is connected to control the output unit substitutions, from the fourth to the sixth information outputs of the control unit are connected respectively with the first through third information input unit lookup the third control input of the control unit connected to control the output of the memory block of words from the first to the third information input of which is connected respectively with the seventh to ninth informational outputs of the control unit, the fourth control input of which is connected to control the output of the first block search and replace, the control input of which is connected to first control the output control unit, the fifth control input of which is connected with the control output of the m second unit search and replace, the control input of which is connected with the second control the output control unit, the sixth control input of which is connected to control the output of the n-th block search and replace, a control input connected to the third control the output control unit, the information output memory block occurrences connected with the second information inputs of all n blocks search and replace, the information output unit lookup connected with the first information inputs of all n blocks search and replace, the information output memory block of words connected with the third information inputs of all n blocks search and replace, seventh and eighth control inputs control unit "RESET" and "START are external inputs to the system.

BPV - block is used to store entries that will need to conduct search operations. BPS - block is used to store words that will be determined occurrence. BPSP - blocks are used to search for occurrences of arbitrary patterns in the processed words in different modes, and perform the replacement operation. Bio - block is used to store lookup, which will replace the found occurrences in a random text. BOO - block is used to control the device.

The processes of searching for occurrences of the pattern in the processed word adequately described in terms Jaz is ka regular expressions through the use of iteration operations and conjunctive sequence (concatenation) [1].

Of particular interest is the structure of the samples, since the sequential search positions occurrence of a pattern in the processed word can be a disaster skip entry if there is a duplicate fragment at the beginning of the sample and, respectively, the n-fold repetition of the above fragment in the processed word when viewing it from left to right. In addition, the repetition of the initial fragment in the structure of the sample leads to a sharp decrease in the speed of finding the position of occurrence of a pattern in the processed word because of the need to perform multiple indents (backtraking) in the space of processed words in his constructive linear representation.

When implementing technical solutions need to organize search positions occurrence of a pattern in order to achieve high speed search, and also to eliminate the emergency passes the desired position. To ensure the search in various operating modes. You need to determine occurrences that have the same parts and occurrences do not have common parts. When performing search functions in words, occurrences can be represented by six different combinations of letters in a word processed.

1) there is no repetition of the same letters (iteration) in the word, example "train";

2) repeat the same letters in the middle of the workpiece is th word, example - "timioara", called V{C}M;

3) iteration exists at the end of the word, example "terminii", the designation V{C};

4) iteration in the processed word exists in the beginning of a word, an example would be the occurrence of "Lemar", the notation {C}Z;

5) iteration in the processed word is present at the beginning of words and at the end, example - "themmmm", the notation {C}W{C}.

6) the processed word consists entirely of iterations, example - "www", the symbol {}.

From the first to the third option of presenting the word of the master, when there is no iteration, the iteration is in the middle of a word and iteration exists at the end of a word, you must search for occurrences of the word to produce the beginning of the word with the first letter. Characters processed words are also read from the beginning, i.e. with the first letter.

The fourth case representation of the processed words, when the iteration is at the beginning of the entry, search must be made with the end of a word, i.e. with the last letter. The word when it is read from the register words in reverse order - the last letter - the first, penultimate is the second and so on, the first letter is the last. The occurrences of symbols are read in exactly the same order, i.e. in reverse.

The fifth case, when the iteration and at the beginning and at the end of the processed words, the search in the present device is carried out from the beginning of the word. But before artelino carried out an analysis of the occurrences of the search block iterations of the device. The entry is divided into two parts:

1) only iteration, i.e., the part consisting of the same characters;

2) the rest of the entry, but without iterations at the beginning of the processed words.

The sixth case, the processed word consists entirely of repetitions of the same letters of iterations, then search device search universal occurrences is the beginning of the word with the first letter.

It is necessary to consider the cases when the iteration is not only one letter, but several alternate characters, such as the processed word is: abababababab. At the beginning of the words of the iteration, consisting of different letters AB, and such repetitions in example - 5. Such iteration will name two. It is easy to give examples of three, four, five and n-letter iterations. At the end of the processed word ends with a final iteration, but from the same letters. At the end of words can also be mnogobukvenny iteration. To search for different types of words, consisting of various iterations necessary, obviously, to develop complex patterns of selection that determine the appearance of iterations. Then depending on the type of iteration is chosen, the algorithm performs a search operation. The aim of the invention is the creation of a search device that searches for occurrences in the processed text is ve with any kind of iterations without complex breeding schemes, as well as functioning in two independent modes with the replace operation.

The algorithm of functioning of the device is as follows. In the case of words is processed word. In the case of occurrences recorded occurrence of the chain of characters. The task of the system is the definition of occurrence in the processed word. If an entry is found, its address is recorded in the memory unit search and replace. If an entry is not found, then in the case of processed words written a new word for search operations. The comparison in the comparator character is letter by letter. At the beginning of the operation signal of the operation mode from the power control unit sets the mode of operation of the search device. To the input of the comparator receives one letter from the register of the processed words and from the register entry. If the result of the comparison is positive, then a shift to the left by one digit of information in both registers and to the input of the comparator receives the next character from the registers. Perhaps there is a situation, when a positive comparison will occur on the first letter, second, third and so on, but the letter k the result of the comparison is negative and thus the end of the word-sample will not be detected. BCD counter device counts the number of floors is positive comparisons. For example, occurred k matches, and k+1 negative result is obtained. In this case, there is a shift to the right by k-1 bits of the register that stores the processed word. Is the "Erasure" of the first letter of the series, where there was a positive comparison. Further comparison will be made, starting with the second letter of the processed words and the first letter of the entry. The entry will be overwritten from the memory of the occurrences. Procedure shift possible with the use of reversible registers that perform shift information as to the left and to the right. The search system works in two modes. The first mode of operation is to determine the occurrences that have common parts. This means that the previous occurrence and subsequent have a common part, consisting of a single letter or character strings. Here is an example.

To The M And P I I I I I p R O s T - handled word

And - entering.

After conducting a search operation in the search mode with the common parts, have four occurrences of 1.

The second format of the system is characterized by the definition of occurrences that do not have common parts. In this case, the address is determined only after n shifts, where n is the number of letters in the register entry. If you want to replace the found occurrences of the substitution of a letter or word, pre-determine lannou and recorded in the register lookup. In this case, first the operation of the search listings without the common parts, then the operation to replace the found occurrences of the substitution.

After conducting a search operation in the search mode without the common parts have two occurrences, 2.

If you want to perform a replace operation, say, for example, the substitution of M And R, then the result is converted processed word, Fig.3.

Parallel search and replace (1) contains the block 1 of memory occurrences, block 2 lookup, block 3 memory words, n - blocks search and replace, block 7 device management.

Figure 1 shows a block diagram of a parallel system of search and replace.

Figure 2 presents different technical implementations of the memory block occurrences, a block of memory words, block lookup.

Figure 3 shows a block diagram of the block search and replace.

Figure 4 shows a variant of the technical implementation unit of the register of occurrences and Comparer.

Figure 5 shows a variant of the technical implementation unit of the register words and lookup.

Figure 6 shows a variant of the technical implementation unit of the register buffer.

7 shows a functional block circuit analysis and generation of signals of the shift.

On Fig depicts a block diagram of the storage unit address entry.

Figure 9 shows a variant t the political implementation of block register processed the words.

Figure 10 shows a variant of the technical implementation unit of the register lookup.

Figure 11 - conceptual GSA unit control block search and replace parallel system.

On Fig - tagged GSA unit control block search and replace parallel system.

On Fig - content GAW operation of the control unit parallel system.

On Fig - tagged GAW operation of the control unit parallel system.

To describe the algorithm of the control block 16 block search and replace and block 7 of the management of a parallel system of search and replace the following identifiers are used.

1. PRKV - terminator occurrences. This can be a binary code is equal to 11...1.

2. PRX - a sign of the end of the word, equal to 11...1.

3. CU - command, specifying the end of the operation.

4. SU - control signals for the shift register memory block occurrences (signals recording, receiving, issuing data).

5. SUR - control signals for the shift register word WG FDS block register processed words (set to "0", reception, synchronization).

6. SDV - team shift coming from the control unit to the input shift register of the block of memory occurrences.

7. SDS - command shift coming from the control unit to the input of shift register word WG FDS block register processed the words.

8. SOUP - team management account, issuing, storing data in RAM memory block occurrences.

9. URR - team management account, issuing, storing data in RAM memory words of the memory block of words.

10. HELL - address data in the RAM issue and write memory block instances.

11. HELL - address data in the RAM issue and write a block of memory words.

12. DN - data recorded in RAM (the binary codes of the characters) block of memory occurrences.

13. BPS - data recorded in RAM (the binary codes of the characters) block of memory words.

14. SSR signal of the comparison received from the comparator.

15. SYN - synchronization command at the input of the binary counter SC unit of analysis and signal shift from the power control block.

16. OBN - command reset binary counter SC unit of analysis and signal offset.

17. SVA - command issuing addresses the occurrence of the unit of analysis and generating signals shift in the storage unit address entry.

18. SSS - team of the write-enable a trigger Tr unit of analysis and generation of signals of the shift output signal from the comparator.

19. NLL - command coming from the control unit by unit, an opening or locking the electronic key AND DD25 unit of analysis and signal offset.

20. SN - command sync binary counter SC unit of analysis and signal shift.

21. WITH the command reset binary counter SC unit of analysis and signal offset.

22. PIM - rectangular pulses on information input electronic key AND DD25 unit of analysis and signal offset.

23. ADST address columns to record occurrences in the storage unit address entry.

24. Adstr address lines to record occurrences in the storage unit address entry.

25. GIVING data address entry.

26. AVH address entry.

27. VDV is the output of the block memory occurrences.

28. GVA - output data words of the block of memory words and lookup.

29. DS - data - processed words.

30. DV data entry.

31. WHEN rectangular pulses coming from the side of the unit control information to the input of logic element AND DD25 unit of analysis and signal offset.

32. SO - rectangular clock pulses supplied to the information input of logic element AND DD29.

33. SVP - team, determines the number of shifts to the right of the register word RGsB DD41 unit register of the processed words.

34. DSE command defines the binary code 0001 (unit) output of a binary counter SC DD30.

35. GI is the generator of impulses coming from the block management unit for summing input (+) of the binary counter SCST DD37 block storage address at which ojdani.

36. T - clock pulses from the control unit by a unit at the summing input (+) of the binary counter Schstr DD38 block storage address entry.

37. Reset - command reset binary counter SCST DD37 block storage address entry.

38. BTS - command reset binary counter Schstr DD38 block storage address entry.

39. SC/St command read/write random access memory RAM of the storage unit address entry.

40. VK - command chip select random access memory RAM of the storage unit address entry.

41. PP - command of an indication of the mode of operation of the system.

42. SRP - sign blank (no data)" random access memory device of the processed words of the block of memory words.

43. The RAF team a characteristic operation of the system in different modes.

44. PZ indication of device operation - search and replace or just to search.

45. Pus is a sign blank (no data)" random access memory lookup unit lookup.

46. SPT - information signal consisting of signals of the STS and the SRP - indication "empty" RAM RAM lookup and processed words.

47. SDS - control signal shift information to the left or right of the register buffer Lbuf block register buffer.

48. SDP - control signal change is and information to the left of the register lookup Lpod block register lookup.

49. UNDER - the data lookup - output information from the RAM lookup.

50. ZAM data replacement - output information register lookup Gpod, replacement is performed in the case when the device operates in the mode of search and replace.

51. SIMS - output register buffer Lbuf, is fed to the input of the register word RGsB block register processed the words.

52. Control commands control recording, issuing, storing data in RAM lookup block lookup.

53. The BPA - address data in RAM lookup - issuing and recording information block lookup.

54. Data recorded in the RAM lookup (binary codes letters) block lookup.

55. SIG - control signals for the shift register Lpod block register lookup (set to "0", reception, synchronization).

56. SGU - control signals for the shift register Lbuf block buffer register (set to "0", reception, synchronization).

57. Vigin - output information output from the electronic key RWE block register processed the words.

58. Up - control signal of an electronic key CL block register buffer.

59. UR a control signal of an electronic key RWE block register processed the words.

60. P - control signal of an electronic key CLC block register lookup.

61. KP - team start-up operation of the search block and the replacement of the s parallel system.

62. Control commands control recording, issuing, storing data in RAM block lookup.

63. BPA addresses of rows and columns for which the data is written in RAM block lookup.

64. Data recorded in RAM (binary codes letters) block lookup.

65. When - output information output from the electronic key CL block register buffer.

66. Behinf - output information output from the electronic key CLC block register lookup.

67. MOUTH "0", the control signal installation at zero buffer register block register buffer.

68. SINGH - managing the synchronization signal of the register buffer unit register of the buffer.

69. NOTE - the control signal receive data register buffer unit register of the buffer.

70. USN "0", the control signal inserted in the zero case of a word block register processed the words.

71. CNH - managing the synchronization signal of the register word block register processed the words.

72. NRB - control signal reception information of the register word block register processed the words.

73. The CONDITION "0", the control signal inserted in the zero register lookup block register lookup.

74. SHIN - control signal synchronizing the operation of the register lookup block register lookup.

75. RBT - control signal reception information register lookup block re the Istra lookup.

Description of the algorithm of the control unit search and replace (BPG).

Meaningful GSA control is shown in figures 9 and reflects the work of the unit search and replace (BPG) (figure 3).

The signal "CP" block 2 graph-scheme of algorithm is filing enabling signal from the control unit for operation of the next block search and replace.

In block 3 on the command "CP:=1" block search and replace receives the enable signal from the control unit parallel system.

In unit 4 of the algorithm is analyzed the mode of the device - team PZ. If the device is operating in the processing mode of the character information search and replace - out YES, then transitions to block 9 of the algorithm. If the device works only in search mode, the output of the block is NO, then transitions to block 5 of the algorithm.

In block 5 of the algorithm is the supply of control signals verses from the control block 16 to the input of the register word RGsB DD41 command RGsB:=SUR. Team Lbuf:=SSU input register buffer Lbuf DD24 served control signals SGU from the control block 16. This is the resolution for recording information from the memory of the words of PS DD10 in the case of the word RGsB, as well as to transmit information from the register of the word RGsB in the register buffer Lbuf (2, 6, 9).

In block 6 of the algorithm about what comes from the entry in the register of the word from memory the words of the processed words RGsB:=DS, in the case of occurrences written from memory of occurrences of a sequence of letters (entry) System:=.D Trigger Tr DD26 unit of analysis and signal shift is set to "0" TR:=0. These commands are pre-loading device (figure 4, 7, 9).

In block 7 of algorithm command add:=0 and SDS:=0 generated shifts to the left by one digit of information contained in the register System DD17 and register the word RGsB DD41 blocks 11 BRUCH (figure 4) and 22 Blab (Fig.9).

In block 8 of the algorithm is the analysis of the mode of operation of the unit of analysis and generating signals shift - command PP. If the command PP is equal to zero, it means that the search device is operating in the search mode of occurrences with the common parts (Fig.1) In this case, the transition is performed on the block 11 of the algorithm. If PP is equal to the unit, the unit is operating in the search mode of occurrences that do not have common parts (Fig.2), this will navigate to the block 9 of the algorithm.

In block 9 of the algorithm at the command of the RAF:=0 the output signal of the logic element DD35 unit of analysis and signal shift is set to the zero state. In this case, the logical elements DD28 and DD32 the specified block will be closed. The outputs of these elements will be zero status.

In block 10 of the algorithm on the team PIF:=0 input register word RGsB DD41 unit 22 register of the processed word is udaetsya signal from unit 16 to control the operation of the memory block and replace is equal to zero. This is a shift of the information in this register by one digit to the left.

In block 11 of the algorithm at the command of the RAF:=1 the output signal of the logic element DD36 unit of analysis and signal shift is set in one state. In this case, the logical elements DD35 and DD28 the specified block will be opened. The outputs of these elements will be the signal WITH rectangular pulses coming from the unit 16 to control the operation of the memory block and replace.

In block 12 of the algorithm on the team PIF:=SVP at the input of the register word RGsB DD41 unit 22 register of the processed words served rectangular pulses SVP, whose number is one less than the number of signals received at the summing input of the counter SC DD30 unit 14 analyzes the signals of the shift. Upon the arrival of each pulse SVP is a shift of the information in this register to the right by one digit.

In block 13 of the algorithm is the analysis of the signal comparison SSR received from the output of the comparator COM DD12 (figure 4). If SSR=1, there is a coincidence of occurrences of letters with the letter of the processed words. In this case, the transition is performed in block 14 of the algorithm. If SSR=0, then a match has not occurred and the transition occurred on the block 19 of the algorithm.

In block 14 of the algorithm on the input D - T trigger DD26 unit 14 analysis and formation is of Ignatov shift signal SSR from the comparator COM DD12 (figure 4) TR:=SSR. The trigger set to the one state. This means that the input symbols at the input of the comparator are equal.

In block 15 of the algorithm on the team SSS:=1 from the control block 16 is write permission on the D-trigger information from the output of the comparator. Team TR:=1 D-trigger unit 14 analysis and signal shift is set to one. At the summing input of a binary counter SC DD30 this block receives the clock pulses SC:=TRUE. The counter counts the number of coincidence in the comparator (Fig.7).

In block 16 of the algorithm is giving signals to the control SIGNAL from the control block 16 to the input of the register lookup Gpod DD43 command Lpod:=SIG to write characters from a register of the processing word RGsB (Fig.9, 10).

In block 17 of the algorithm is an entry in the register lookup Gpod DD43 from the register of processed words RGsB characters GVA command Lpod:=GVA (Fig.9, 10). In this case, there was a concurrence of input values to the comparator input.

In block 18 of algorithm command PIF:=0, add:=0, SDP:=0 is formed by the left shift information held in registers respectively RGsB DD41 unit 22 register of the processed words, System DD17 unit 11 of the register of occurrences, Gpod DD43 - register lookup unit 20 register lookup. This will navigate to the block 32 algorithm.

In b the Oka 19 algorithm analyzes the contents of the D-flip-flop Tr DD26 (Fig 7). If Tr=0, then this means that a match at the previous step was not, in this case, a signal of a left shift by one digit in the register of the word RGsB DD41 unit 22 register of the processed words. If TP=1 then transitions to block 23 of the algorithm.

In block 20 of this algorithm is the control signal SGU from the control block 16 to the input of the buffer register Lbuf DD24 team Lbuf:=SGU to write characters from the register of the word RGsB DD41 (Fig.9).

In block 21 of the algorithm is formed by a team of PIF:=0 shift to the left by one digit information from the register of the word RGsB in case Lbuf block 21 block register buffer Bigbuf (6). This Lbuf:=GVA output GVA from the register of the word RGsB is overwritten in the register Lbuf through public key CL DD23. The vacant place in the case of the word RGsB recorded the next symbol is processed words from unit 3 memory words RGsB:=DS (2, 5, 9).

In block 22 of the algorithm at the command of SS:=0 from the control block 16 is formed a control signal, which is the left-shift information in the register Lbuf DD24 on one digit to the left of block 21 of the register buffer to write the next character from the register of the word RGsB DD41 (5, 9). This will navigate to the block 36 of the algorithm.

In block 23 of the algorithm on the team Lbuf:=SGU signals control SGU from the block 16 management in the ar register buffer Lbuf DD24 to write characters from a register lookup Gpod DD43. The team Lpod:=SIG is giving signals to the control SIGNAL from the control block 16 to the input of the register lookup Gpod DD43 for the issuance of characters from the register lookup Gpod in the register buffer Rxbuf. Team DCS:=0 from the control block 16 is formed a control signal, which is the left-shift information in the register Lbuf DD24 on one digit to the left for entry of the next character from the register lookup Gpod DD43. Team SDP:=0 is formed by a left shift of information contained in the register Gpod DD43 unit 20 substitutions. As a result of running these commands all information from the register lookup Gpod will be written to the register buffer Lbuf (figure 5, 6, 10).

In block 24 of the algorithm on the team Lbuf:=Lpod in the register buffer Lbuf DD24 unit 21 of the register buffer characters will be transferred from the register lookup Gpod DD43. These commands will overwrite the information from Lpod in Lbuf (figure 5, 6, 10).

Unit 25 analyzes the state of the binary counter SC DD30 unit 14 analysis and signal shift. If the state counter is less than or equal to one, then transitions to block 29 of the algorithm. If the condition is true, i.e. the value of the counter SC greater than one, then the transition occurs at block 26 of the algorithm.

In block 26 of the algorithm is formed by filing a rectangular pulse of unit 16 of the control is to be placed - In the subtractive input of a binary counter SC DD30 unit 14 analysis and signal shift. Team SVP:=1 in the counter is the algebraic subtraction unit until such time as the state of this counter is not equal to a single value SC:=IF (Fig.7).

In block 27 of the algorithm is formed by a shift to the right and rewriting of information from the register buffer Lbuf DD 24 in the case of the word RGsB DD41 unit 22 register of the processed words. Commands from the control block 16 SDS:=1 and SDS:=1 information from the register buffer Lbuf shifted by one digit to the right in the case of the word RGsB. The team RGsB:=SUR is the resolution of the operations of the shift register block 22 of the processed words. Information from the register buffer Rxbuf is shifted in the register of the word RGsB up until the counter SC DD30 will not be equal to one (figure 4, 5, 6, 7, 9).

In block 28 of the algorithm at the command of Lsob:=Rxbuf in the case of the word RGsB DD41 will be transferred characters from the register buffer Lbuf DD24. These commands will overwrite the information from Rxbuf in RGsB (figure 5, 6, 9).

The blocks 25, 26, 27, 28 algorithm form a cycle. The exit from the loop is the condition under which the value of the counter SC will be equal to one. On exit from the block transitions to the block 29 of the algorithm.

In block 29 of the algorithm on the input of the register entry System DD17 unit 11 d is Istra occurrences of the control block 16 receives control signals System:=SU. As a result, in the case of occurrences of the recorded information from the memory of the occurrences of the System:=DV (figure 4).

In block 30 of the algorithm register word RGsB receives information from the register buffer Lbuf RGsB:=Lbuf (figure 5, 6, 9). The processed word is shifted to the right by n-1 bits, where n is the number of shifts to the left of the same word.

In block 31 of the algorithm at the command UPD:=1 is the count SC DD30 unit 14 analysis and signal shift. Binary counter SC DD30 take the value zero SC:=0. The output of the block is transition to a block 32 algorithm.

In block 32 of the algorithm is the analysis of terminator occurrences PRCV (figure 4). If PRCV=1, then the register entry System detected binary code 11...1. In this case, the occurrence is detected in the processed word in the block storage address of occurrences recorded address entry (Fig) If PRCV=0, it means that the comparison process is letter by letter, but not all occurrences of letters still viewed, this will navigate 38 block algorithm.

In block 33 of the algorithm is analyzed mode device operation commands PZ. If the device is operating in the processing mode of the character information search and replace - output YES, it means that the detection of the occurrence of the processed word is carried out in the register lookup Gpod on pre-recorded the th in the case of the substitution - the string of symbols. In this case, the transition is performed in block 34 of the algorithm. If the device works only in search mode, the output from the block - NO, it means that the address detected in the process of searching for occurrences will be recorded on the appropriate addresses of rows and columns in a memory device (Fig). In this case, the transition is performed at block 37 algorithm.

In block 34 of the algorithm at the command of Lpod:=SIG is giving signals to the control SIGNAL from the control block 16 to the input of the register lookup Gpod DD43 to write characters from a memory block lookup bio - RAM lookup UNDER DD9. The team Lpod:=in the case of lookup Gpod DD43 written letters lookup from memory lookup UNDER 2, 5, 10). As a result of running these commands in the register lookup Gpod will be recorded information from the block of RPU memory lookup.

In block 35 of the algorithm on the team Lbuf:=SGU signals control SGU from the control block 16 to the input of the buffer register Lbuf DD24 to write characters from a register lookup Gpod DD43. Team SDP:=0 is formed by a left shift of the information contained in the register lookup Gpod DD43 unit 20 register lookup. Team DCS:=0 from the control block 16 is formed a control signal which is the left-shift information in the register buffer Lbuf DD24 is but one digit to the left for entry of the next character from the register lookup Gpod DD43.

In block 36 of the algorithm on the team Lbuf:=Lpod is write data in the register buffer Lbuf DD24 from the register lookup Gpod DD43. As a result of running these commands blocks 34, 35, 36 all information from the register lookup Gpod will be written to the register buffer Rxbuf. Thus will be realized the substitution of symbols in place of the detected occurrence of GVA (figure 5, 6, 10). Operation search and replace is performed only when the device is in the search mode occurrences without the common parts. The output from this block is transition to a block 38 of the algorithm.

In block 37 of the algorithm is the address record in the storage unit address listings. On the control input of an electronic key CL DD34 unit 14 analysis and signal shift permissive signal is received from the control block 16 - IAS, CL:=CBA. Information from the output of the binary counter SC DD33 through public key CL DD34 fed to the input of operational storage device RAM DD39 (Fig.7, 8). The enable signal for recording information supplied from the control block 16 MF/Po:=0, VK:=0. On control inputs received zero values, which corresponds to the recording mode in the RAM device input information i.e. address entry - AVH RAM:=AVG.

In block 38 of the algorithm is the analysis of the sign of the end of a word PRX (an attribute is binary, equal to all units who am 11...1). If PX=0, then the search process will continue and this will navigate to the block 13 of the algorithm. If the detected sign of the end of the word PRX=1, then transitions to block 39 of the algorithm.

In block 39 of the algorithm is the analysis of the sign "empty" RAM words - SRP unit 3 memory the processed words. If the SRP is equal to zero, then transitions to block 5 of the algorithm. In this case, the word memory block 3 memory words available information (words)that will need to conduct the search and replace operation, i.e. the process will continue. If the SRP is equal to one, it means that all the words in the word memory unit 3 to the memory of the processed words viewed (figure 2). In this case, the transition is performed on the target block 40 of the algorithm. In the operation of the search device is shutdown.

Unit 40 of the algorithm is the final block.

Description of the algorithm of the control unit parallel system of search and replace.

Meaningful GSA management see figure 11 and reflects the operation of the control unit (figure 1).

The signals U" and "START" (blocks 2,4-graph-scheme of algorithm (1) is setting to zero all memory elements of a parallel system, the command "RESET=1" (block 3).

In block 5 of the algorithm loads of occurrences of the block of memory occurrences (figure 2) for search operations is th. Team-PV:=SOUP supplied to the input of random access memory (RAM) PV DD.8 memory block occurrences (BPV) control signals for writing and reading information in RAM. Team-PV:=AD served the address inputs of rows and columns for recording and reading data in RAM. Team-PV:=DN is fed to the inputs of RAM data (occurrences) to record in random access memory (figure 2).

In block 6 of the algorithm is loading information into the memory block of words for search operations. Team PS:=YPP supplied to the input of random access memory (RAM) PS DD.10 block of memory words (BPS) control signals for recording information in RAM. Team PS:=ADA serves the address inputs of rows and columns for recording data in RAM. Team PS:=BPS is fed to the inputs of RAM write data into the random access memory (figure 2).

In block 7 of the algorithm is loading information in the block lookup for surgery replacement. On command:=SIMP supplied to the input of random access memory (RAM) UNDER DD.9 block substitutions (BPO) control signals for recording information in RAM. On command:=DT serves the address inputs of rows and columns for recording data in RAM. On command:=DAN is fed to the inputs of RAM data to write to the operator the main storage device (figure 2).

In block 8 block counter search and replace - i is set to one state by the command i:=1.

In block 9 of the algorithm analyzes the current value of the counter units i. If i<=N, where N is the total number of blocks search and replace in a retrieval system, then the boot process block for character processing continues. In this case, the transition occurs at block 10 of the algorithm. If the condition in block 9 of the algorithm is performed, i.e. all blocks are loaded, then it moves on to the block 12 of the algorithm.

In block 10 of the algorithm on the team Bps:=MSE units search and replace parallel system serves a start command - KP, for the start of the system.

In block 11 of the algorithm by command i:=i+1 is the change in the value of the counter blocks (BPG) on the unit. This will navigate on block 9 of the algorithm.

In blocks 9, 10, 11 formed cycle of loading and operation for all blocks search and replace parallel systems, starting with the first and N-th.

In block 12 block counter search and replace - i is set to one state by the command i:=1.

In block 13 of algorithm analyzes the current value of the counter units i. If i<=N, where N is the total number of blocks search and replace in a retrieval system, then the operation blocks search and replace parallel systems is still ongoing. In this case, the transition occurs at block 14 of the algorithm. If the condition in the Loka 13 algorithm fails, i.e. all the blocks of the system is stopped, it moves on to the block 16 of the algorithm.

In block 14 of the algorithm at the command BU:=PRCV of the blocks search and replace parallel system receives signals terminator occurrences - PRVC, which means the end of the next block. In this block of the algorithm is to count the number of blocks performed the task on symbolic information processing, and therefore generated the signal shutdown.

In block 15 of the algorithm by command i:=i+1 is the change in the value of the counter blocks (BPG) on the unit. This will navigate to the block 13 of the algorithm.

In blocks 13, 14, 15 formed cycle counting all the blocks in the search and replace parallel systems, in which the work was completed, starting with the first and n-th.

Job search random occurrences is as follows:

External control signals "START" and "RESET" are received in block 7 of the control.

In a parallel system search and replace is a process with multiple words and multiple instances in parallel form, and if necessary, the operation of replacing occurrences of the substitution. To implement parallel processing in the system, there are n blocks search and replace BPSP. In each block BPSP system loaded words and occurrences. Work the try blocks are independent of each other mode. All these blocks have the same structural and circuit diagrams, consisting of similar digital items. The units work on the same algorithm. The replacement operation is carried out only in the mode of the search engine listings do not have common parts.

In the random access memory unit 3 BPS recorded, processed words in which it is necessary to detect occurrence. Under the occurrences refers to a symbol or string of symbols (including words)that you want to find in words unit BPS. Occurrences are recorded in the memory device unit 1 BPV. In block 2 lookup BPO records lookup. This individual characters, the string of symbols or words on which you want to replace the found occurrences in the processed text. The team is START from RAM memory blocks of occurrences of words in search boxes and replacement of the system are recorded respectively occurrences of a word.

In each block a search and replace operation comparison to the comparator sequentially, each letter of the entry is compared with the characters of the processed words. In block 14 analysis and signal shift is processed by the signal comparing characters received from the comparator COM DD12. The processed word from the RAM block 3 memory words is recorded in the register of processed words RGS Is B DD41 block search and replace. The occurrence is recorded in the register of occurrences of System DD7. In each block a search and replace analyzes the signal from the block control unit that sets a mode of the device - PP. If the entry found in the word, it generates the address (position) of the occurrences of the word. The detected entry is in the registry lookup Gpod DD43 unit 20 register lookup. If the user selected mode of search and replace in the registry lookup Lpod from memory lookup replaces occurrences of the substitution chain of characters. After a transaction lookup information from the register lookup Gpod DD43 is overwritten in the register buffer Lbuf DD24 unit 21 of the register buffer. Case Gpod when this is released for further search occurrences in the processed word. If you have selected only the search, the address entry is recorded in the RAM unit 15 storage addresses. The address is stored in the storage unit 15 addresses. If the comparison is not completed, the formed signals shift SDS, SDS in block 16 of the control unit, supplied to the input blocks BRSP. If the device occurs a situation in which you received the first positive results of the comparison in the comparator, and then negative, but the terminator occurrences not yet discovered. In this case, will be found only a few characters joining the Oia, but not all occurrences completely. With a positive result in the comparator shifts to the left by one position information of the register word RGsB DD41, in which the word is located. The word from the register of the word RGsB DD41 letter goes into the register lookup Gpod DD43. A binary counter is counted positive series of comparison in the comparator. In case of negative result of the comparison is the transcribing of information from the register lookup Gpod DD43 in the register buffer Lbuf DD24. Then from the register buffer Lbuf DD24 characters are overwritten in the register of the word RGsB DD41. The number of shifts to the right will be less by one than the number of shifts to the left. The process of search will be continued, but with the second letter of the fragment, which was found positive series of matches in the processed word. The first letter in this case as "deleted". The process continues until you have found all occurrences and implemented the replacement operation in the processed word.

Block 1 of memory occurrences contains random access memory (RAM) - memory occurrences of RO DD8, which will be recorded occurrences.

Unit 2 lookup contains random access memory (RAM) - memory lookup UNDER DD9, which will be stored lookup.

Unit 3 memory words contains an operational saponin the abuser device (RAM) - the memory of the words of PS DD10, which will be recorded, processed the words.

Unit 7 generates control information and control signals received at the input units of the system.

Unit 4 search and replace BPG contains: block register entry - BRUH DD11, comparator - COM DD12, block register words and lookup - BRSP DD13, the unit of analysis and signal - BATS DD14, the storage unit address occurrences - BHAVAS DD15.

Block 11 of the register of occurrences - BRUH contains a reversible shift register System DD17 (register occurrences), which will be stored entry, the logical element AND DD18 to detect terminator occurrences. The control signals SOUP is the resolution of recording information on the address inputs AD recorded data DN in RAM (memory occurrences) of unit 7 controls (figure 1, 2, 4). Output memory occurrences information DV is fed to the input of the reversing register of occurrences of System DD17, the control signal SU from the block 16 of the control unit, write the letters of the entry in the register of occurrences. The signal shift occurrences of add from the block 16 of the control unit is fed to the input of the reversing register listings - System (figure 4). The output of the reversible register occurrences VDV is fed to the input of the comparator COM 12 (3, 4). Reversible register System DD17 shift in any direction: left to right or Vice versa. Shift to the right in is performed when the value of the signal SDV=1, left shift - if add=0, i.e. the direction of the shift by one control signal [3, 4]. Element AND DD18 generates a signal terminator occurrences PRCV equal to the unit (all units at the entrance). In memory of occurrences of the signal is formed CU - end, if the RAM is empty. Before working device in the memory of the occurrences recorded all occurrences in the register of occurrences is the first occurrence, the signal terminator occurrences PRCV equal to zero, the signal shift occurrences add to zero.

The comparator COM DD12 is a device comparison for equality of input values: output occurrences airborne unit 11 BRUCH and output data words GVA unit 13 BRSP (figure 4, 5). If the input signals are equal, then the output of the comparator is formed of a single signal SSR. Otherwise, the SSR will be zero. The output signal of the comparator is fed to the input unit 16 of the control unit and the input unit 14 analysis and signal shift (figure 4, 7).

Unit 13 registers the words and lookup contains: block register lookup Blpod DD20, block register buffer Bigbuf DD21, the unit register of the processed word - Blab DD22, the logical element AND DD19 is designed to detect signs of the end of a word PRCS.

Block register lookup Blpod DD20 contains: reversible shift register Gpod DD43 (case sensitive lookup), in which x is anicca characters processed words in the case of a positive comparison in compartor and electronic key CLC DD42. Block register buffer Bigbuf DD21 contains: reversible case shift buffer Lbuf DD24 for intermediate storing information and an electronic key CL DD23. The unit register of the processing word Blab DD22 contains: reversible shift register RGsB DD41 (register words)in which is stored the processed word, and electronic key RWE DD40.

The control signals URR is the resolution of recording information on the address inputs HELL written BPS data in RAM (memory words) from the block 16 of the control unit (figure 2). Output word memory information DS is supplied to the inputs of blocks search and replace BPG parallel systems. In each block a search and replace input information DS is recorded in the reversible case the word RGsB DD41, the control signals verses from the unit 16 of the control unit (Fig.9). The signal shift words SDS from the block 16 of the control unit to the input of the unit register of the processing word Blab DD22, in which the input of the reversing register words RGsB DD41 (5, 9). The output of the reversible register word RGsB DD41 - GVA is fed to the input of logic element AND DD19, and also to the second input of the comparator COM DD12, the information input electronic key CLC DD 40, then to the input of the register lookup Gpod, to the information input of the register buffer Lbuf through electronic key CL DD23 (figure 5, 6, 9, 10). On the WMO information the register of the word RGsB DD41 receives output information from the register buffer Lbuf DD24. Element AND DD19 generates a signal characteristic of the end of a word PRX equal to the unit (all units at the entrance). Before working device in the memory of the words of PS RAM DD10 recorded all the words, in the case of the word RGsB is the first word, the signal terminator words PRX equal to zero. If the output of the comparator KOM will be generated signal comparison SSR equal to one, the signal shift PIF will be zero in this case will be generated signal left shift the data by one digit. Information from the register of the word RGsB DD41 will move one character to the left. This symbol will pass on the information signals WHITEFISH in the register lookup Gpod DD43. The process left shift will continue until, until there is obtained a negative result of the comparison in the comparator COM DD12 or not detected occurrence of the word. For example, suppose you recorded 5 shifts to the left, and then received a negative signal comparison SSR, zero. In this case, all information from the register lookup Gpod will be copied into the register buffer Lbuf, under control of signals shift: SDP and SDS of zero. After that, the control unit 16 unit will be generated signals right-shift the signals shift SDS and SDS will be equal to one. Information from the register buffer Lbuf DD24 will be shifted to the right by one character less than the left, in this case 4. E is th case of the second letter of the word will be first in the register of the word RGsB DD41, the process of search will be continued. Four letters from the register lookup Gpod DD43 go first in the register buffer Lbuf DD24, and then transferred to the register of the word RGsB DD41, if the selected mode of the device search and replace. If the selected mode of operation only search listings with saving the addresses in RAM DD39, in this case, information from the register of the word RGsB DD41 will correspond directly to the register buffer Lbuf DD24. The operating modes of the device will be formed with control signals: SUR, WHITEFISH, SGU from unit 16 unit control.

Unit 14 analysis and signal shift contains: D - trigger Tr DD26, two-input logic element AND DD27 with an inverted input of two-input logic element AND DD29, two-input logic element AND DD25, trekhgolovy logical element AND DD28 with inverse sign, chetyrehuhogo element AND DD31 with inverted inputs, trekhgolovy element AND DD32 with inverse sign, electronic key DD34, binary counter SC DD30, binary counter SC DD33, input element OR with inverted inputs DD36, input element AND DD35. Before you begin the device binary counters DD30, DD33, and D-trigger Tr is set to the zero state. Unit 14 analysis and signal shift processes the output signal SSR from the comparator COM DD12. If the signal SSR is equal to one, it means that produced Oslo coincidence of the binary code symbol occurrences in binary code letters of the word. In this case, D-trigger Tr DD26 upon arrival of the unit 16 control enabling signal SSS equal to one, set in one state. The logical element AND DD29, performs the function of an electronic key, unlocked, clock pulses from the control block 16 are received at summing (+) input of a binary counter SC DD30. In the binary counter SC DD30 is the sum of clock pulses, whose number corresponds to the number of matches in the comparator COM. The output of the binary counter SC DD30 is formed binary code corresponding to the number of positive matches in the comparator. For each positive match in the comparator is formed of signals shift left and add SDS equal to zero, and shifted one character to the left in registers System DD17 block 1 of memory occurrences and register the word RGsB DD41 unit 22 register of the processed words. Register Lbuf DD24 unit 21 of the register buffer writes each character received from the register of the word RGsB DD41, if the comparison has not occurred. In the case of terminator occurrences PRCV equal to the unit logic elements AND DD18 unit 11 of the register of occurrences is determining the address for the entry and recording the corresponding address entry in the random access memory RAM DD39 unit 15 storage addresses occurrences. Eclipsing the end of a word is not found PRCV=0 (zero), the previous occurrence is restored, i.e. repopulated from the memory of the occurrences and the process of searching for occurrences of the word continues (in the case of multiple occurrences of one word). If coincidence in the comparator COM does not occur, the output signal SSR is equal to zero, it generates only the signal SDS is equal to zero and a shift to the left by one position information held in the register word RGsB DD41 unit 22 register of the processed words. Each left shift and the negative result of the coincidence in the comparator of the memory words of PS overwritten (appended) character in the register of the word RGsB DD41 unit 22 register of the processed words. It is possible in the search operation, when it received a positive result of the comparison characters, then formed a left shift by one digit registers RGsB DD41 and Gpod DD43. After shifting the received second time a positive result, the third and so on, but terminator entry yet. For example, for n step obtained a negative result of the comparison, and the occurrence is not fully discovered. In this case, D-trigger Tr DD26 was installed in the state unit, i.e. at the output of the element unit. In the next step, the signal comparison is equal to zero SSR=0. The output of the logical element AND DD27 be formed of a single signal. The logical element AND DD28 will also be open, etc is mogilnie pulses from unit 16 of the control unit WHEN will be transmitted to the subtractive input of a binary counter SC DD30. Subtraction occurs up until the output of the counter is not binary equal to one. On the positive input of the counter rectangular pulses from unit 16 unit control will not be received, because the logical element AND DD29, performs the function of an electronic key will be locked established in the zero state of the D trigger DD26. The logical element AND DD31 performs the function of the decoder unit. The output of this element is equal to unity in the case of obtaining the output of the counter SC DD30 binary code 0001. For all other combinations at the output of this element will be condition zero. When the unit output of this element logical element AND DD28 locked, because the unit is supplied to an inverse input. Rectangular pulses to the subtractive input of the counter SC DD30't do that. Counter SC DD30 reset command OBN coming from unit 16 of the control unit. The logical element AND DD32 performs the role of a "valve"that form the number of shifts to the right of the register word RGsB DD41. Every time when the subtraction unit from the contents of the counter SC DD30, is moving to the right information from the register Lbuf DD24 in the case of the word RGsB DD41. The number of shifts to the right will be one less than the number of shifts to the left. In our example, n-1. The second letter from the received series of positive changes will be first in the register of the word RGsB DD41. The entry will be rewritten from memory occurrences in the register of occurrences of System DD17. The search process will continue. The logical element OR DD36 performs the detection operation mode. As is known, the system operates in two independent modes: definitions of occurrences with the common parts and identify occurrences and without (intersections) of the common parts. In the first case, the characteristic mode of the RR will be zero. In the second case, the sign of PP equal to one. The logical element AND DD35 performs the function of an electronic key. In the case when the characteristic operation of the system PP is equal to zero, the output element OR DD36 will always be one. Electronic key DD35 will be opened. The rectangular pulses from unit 16 of the control unit via the public key received at the third input of logic element AND DD28. This mode is characterized by movement of information from the register Lbuf DD24 in the case of the word RGsB DD41 on n-1 bits, i.e. generate a return of information, where n is the number of positive shifts, whenever it is discovered occurrence in the processed word, and the terminator occurrences PRCV will be equal to one. If the system mode will be set as the search without the common parts, in this case, RR is equal to one. In case of detection of occurrence, while the sign of occurrences PRCV also equal to one. The output log is ical element OR DD36 set to zero. Electronic key AND DD35 will be locked. The rectangular pulses from unit 16 unit control will not be sent to the input element AND the DD28 (Fig.7). Information from the register Lbuf DD24 will not move in the case of the word RGsB DD41. In this case, is formed by the left shift of characters from the register of the word RGsB DD41 in case Gpod DD43, i.e. return information will not be (5, 9, 10).

Terminator device SRP equal to one, can be formed when all occurrences viewed, in memory of occurrences of no information and memory of the words of PS is also empty. If the SRP is equal to zero, the register of the word RGsB DD41 unit 22 register of the processing word Blab receives new information (new word) of memory words (2, 5, 9).

Block 15 storage addresses occurrences BHAVAS contains random access memory RAM DD39, the binary counter generates the addresses of the columns of RAM - MF Article DD37, the binary counter generates the addresses of the rows of RAM - MF P DD38. Binary counters at the beginning of the operation of the device reset control signal reset, the line coming from the block 16 of the control unit. The inputs of the counters arrive rectangular pulses KI TI of block 16 of the control unit. Counters form the addresses of rows and columns on which is recorded the address of the occurrences at the input of random access memory RAM DD39, if the selected device in the e mode only search listings. The control signals random access memory RAM DD39 read/write and chip select, respectively, when recording take values MF/St=0, VK=0 (Fig).

Unit 16 unit control BPG is synthesized on the basis of GSA control algorithm (11) by a known method [3,5]. Tagged GSA unit 16 of the control unit shown in Fig where indicated:

The logical conditions are true:
X1: "KP"X6: "SC>1"
X2: "PZ"X7: "PRCV"
X3: "RR"X8: "PX"
X4: "SSR"X9: "SRP"
X5: "TR"
Operators:
N1: KP:=1"U: "Lbuf:=Gpod"
U2: "RGsB:=SURU: "Lbuf:=GVA"
U3: "Lbuf:=SGU"U: "RGsB:=DS"
A4: "RGsB:=DS"U: "SDS:=0"
U: "System:=DV"U: "SVP:=1"
U: "TR:=0"U: "SC:="
U: "add:=0"U: "SDS:=1"
U: "SDS:=0"U: "SDS:=1"
U: "RAF:=0"U: "RGsB:=Rxbuf"
U: "RAF:=1"U: "System:=SU
U: "SDS:=SVP" U: "System:=DV"
U: "TR:=SSR"U: UPD:=1"
U: "SSS:=1"U: "SC:=0"
U: "TR:=1"U: "Lpod:=UNDER
- Y15: "SO:=SOU33: "CL:=CBA"
U: "Lpod:=SIG"U: "MF/Po:=0"
U: "Lpod:=GVA"W: VK:=0"
U: "SDP:=0"U: RAM:=AVH"

Unit 7 control system is synthesized on the basis of GSA control algorithm parallel system (Fig) in a known manner [3, 5]. Tagged GSA unit 7 controls the parallel system is shown in Fig where indicated

The logical conditions are true:
X1: "the DOE"X3: "i<=N
X2: START"
Operators:
N1: RESET:=1"U::=SIMP"
U2: "PV:=SOUP"U: UNDER:=DT"
U3: "PV:=ADU::=DAN"
A4: "PV:=DN"U: "i:=1"
W: PS:=URR"U: "Bps=KPI"
W: PS:=ADE"13: "i:=i+1"
W: PS:=BPS"U: "BU:=PRCV"

SOURCES of INFORMATION

1. Kudryavtsev V.B. have been, Podkolzin A.S., Osculi the W. Weenie in theory of abstract machines. M.: Moscow University press, 1985. 174 C.

2. Markov, A.A., Nagorno NM Theory algorithm. - Moscow.: Science 318 S. Main edition of physico-mathematical literature. 1984

3. Uspensky V.A., Semenov A.L. Theory algorithm: main discoveries and applications. - Moscow.: The science. The main edition of physico-mathematical literature. 1987 - 210 C.

4. Alexenko A.G., Sagarin I.I. Microcircuitry: Textbook. manual for schools. - 2nd ed., revised and enlarged extra - M.: Radio and communication, 1990. - 496 S.: ill.

5. Baranov, S. Synthesis of microprogrammed machines. - Energy. Leningrad branch. 1974 - 184 C.

6. Digital and tax integrated circuits: Handbook edited Svechenovskoj. - M.: Radio and communication, 1990. - 496 S.: ill.

7. Patent No. 2195015 (prototype).

8. Patent N 2150740 (similar).

9. A.S. USSR N 1837327 (similar).

10. A.S. USSR N 1667097 (similar).

Parallel search and replace, containing a block of memory occurrences, a block of memory words, the control unit, characterized in that additionally introduced block lookup n blocks search and replace, and first to third information output control unit are connected respectively with the first through third information input of the memory block occurrences, managing the output of which is connected to the first Manager of the input control unit, the second control input of which connection is replaced with a control unit output lookup from the fourth to the sixth information outputs of the control unit are connected respectively with the first through third information input unit substitutions, the third control input of the control unit connected to control the output of the memory block of words from the first to the third information input of which is connected respectively with the seventh to ninth informational outputs of the control unit, the fourth control input of which is connected to control the output of the first block search and replace, the control input of which is connected to first control the output control unit, the fifth control input of which is connected to control the output of the second unit search and replace, a control input connected with the second control the output control unit, the sixth control input of which is connected to control the output of the n-th block search and replace, a control input connected to the third control the output control unit, the information output memory block occurrences connected with the second information inputs of all n blocks search and replace, the information output unit lookup connected with the first information inputs of all n blocks search and replace, the information output memory block of words connected with the third information inputs of all n blocks search and replace, seventh and eighth control I the water control unit "RESET" and "START" are external inputs to the system.



 

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