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Target fluctuating signal generator

Target fluctuating signal generator
IPC classes for russian patent Target fluctuating signal generator (RU 2253129):
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FIELD: check-up of functioning of the devices for processing of radar information, as well as instruction and training of operators of these means in the conditions of a great number of targets moving in complex trajectories.

SUBSTANCE: the device having a control panel, storage unit, synchrosignal generator, first, second and third on-line memories, unit for formation of target relative coordinates, unit for formation of the maximum target signal intensity, first, second, third and fourth synchronizers, unit for formation of the current intensity of the target signal, digital-to-analog converter, noise generator, adder uses also a correlator, first and second detectors, first and second multiplier units, first and second random number generators, which provides for formation of amicably fluctuating and quickly fluctuating bursts of pulses reflected from the radar targets, internal noise of the receiver and synchronizing signals at the output of the radar receiver in the rate of radar functioning and with due account made for motion of the ship-carrier.

EFFECT: simulation on the screen of the radar station of the target situation corresponding to the real conditions of receiving of the bursts of radar signals reflected from the moving targets with slow and quick fluctuation of the amplitude.

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The invention relates to the field of radar, namely, devices that form simulating the synchronization signals and the signals at the receiver input surveillance radar station (radar)containing the signals from moving targets, taking into account the fluctuations of their effective reflecting surfaces (EOP), and the noise of the receiver of the simulated radar, and is intended to verify the operation of the devices, radar data processing, as well as education and training of the operators of these funds in terms of a large number of moving along complex trajectories purposes.

Widely known device that generates trajectories of moving objects at a known initial coordinates, time of beginning and the parameters of the maneuver, as well as devices forming the current polar coordinates of targets relative to radar systems [1]. Also known device, forming a stack of the reflected signals from the target, given its average value EOP, target range and its angular position relative to the search radar and beam forming simulated radar [2].

From the known signal generators targets used to test devices, radar data processing, closest to the claimed most essential features and achieved technical effect is the generator of signals from targets containing the th remote control, memory block, the block forming the relative coordinates of the target (FOCC), block the formation of the maximum signal intensity of the target (FMISC), first, second and third operative memory (RAM), block the formation of the current signal intensity of the target (FTIC), the generator of signals, the first, second, third and fourth blocks synchronization digital to analogue Converter, the noise generator and the adder [3]. Generator, selected as a prototype, provides for the formation of pulses of the objectives fixed by the average value of the image intensifier, and verification of algorithms of functioning of the apparatus for the detection and tracking of targets, the possibility of the formation of the signal applied to the indicator devices of the radar data processing, but does not ensure the formation of packs together fluctuosa and quickly fluctuosa pulses caused by the change in the instantaneous value EOP target due to its movement relative to the center of mass and vibration applied to the indicator devices of the radar data processing for checking algorithms of functioning of these devices, as well as for training operators of these funds in conditions as close to real.

Object of the invention is to enhance the functionality of the generator signal is s goals that improves the quality of diagnosis of radar devices and validation of algorithms for processing radar data from the moment of detection packs reflected on the purpose of the pulses prior to the issuance of the current coordinates of the targets consumers, as well as the effectiveness of the education and training of radar operators, taking into account changes in instantaneous image intensifier moving targets in the process of their movement in space relative to a search radar.

The technical result consists in the simulation on the screen of the radar target environment corresponding to the actual conditions of reception packs reflected from the moving target radar signals with slow and rapid fluctuation of the amplitude.

This object is achieved by the introduction of the scheme of the prototype blocks and their relationships, which provide for a given number of targets forming together fluctuosa (slow fluctuation) and quickly fluctuosa packs of reflected pulses, depending on the type and angle of goals, as well as from the correlation interval fluctuations.

The ability to achieve a technical result due to the fact that on the basis of theoretical assumptions [4] random changes in the amplitude of the pulses together fluctuating tutu occur in accordance with the exponential law of distribution density verojatno and (1) simultaneously for all pulses within the batch, and random changes in the amplitude of the pulses rapidly fluctuating packs are also in accordance with the exponential distribution the probability density, but independently for all pulses within the stack.

where- the power of the Central pulse of the stack corresponding to the average value of effective area of the radar cross section (RCS) of the target.

Figure 1 shows the structural electrical diagram of the inventive device.

Figure 2-8 shows the timing chart explaining the operation of GFSC.

Generator fluctuosa of signals from targets (GFSC) contains (1) 1 remote control (PU), a memory unit 2, unit 3 forming the relative coordinates of the target (FOCC), the correlator 4, block 5 the formation of the maximum signal intensity of the target (FMIC), the first detector 6, the first unit 7 multiplication, the first generator 8 random numbers, the first operational storage device 9 (the first RAM), generator, signals 10, the first block 11 synchronization, the second block 12 sync generator 13 of noise, the second memory device 14 (the second RAM) unit 15 of the formation of current signal intensity of the target (block FTIC), the second detector 16, the second block 17 multiplication, the second generator 18 random number, the third operational storage device 19 (third RAM), the amount of the EO 20, d / a Converter 21 (DAC), the third block 22 synchronization, the fourth block 23 synchronization. Out of the 1 remote control connected to the data bus with the input of the generator 10 signals and to the first input of the memory unit 2, the first output of which is connected to the data bus to the first input unit 5 FMIC and with the input of block 3 FACTS, and a second output connected to the data bus with the input of the correlator 4, the output of which is connected to data bus with the third input of the first RAM 8 and the input of the first detector 6, the output of which is connected to the input of the first generator 8 random numbers, the output of which is connected to data bus with a second input of the first unit 7 multiplication, the output of which is connected to data bus with the first the input of the first RAM 9, a first input connected data bus to the output unit 5 FMISC. The output of block 3 FACTS connected to the data bus with a second input unit 5 FMIC and with the second input of the first RAM 9. The first output of the first block 11 synchronization is connected to the address bus with the second input of the memory unit 2 and the fifth input of the first RAM 9, and the second output is connected by bus synchronization with the third input of the memory unit 2 and to the fourth input of the first RAM 9, a third output connected to the first input of the second unit 12 synchronization, the first output of which is connected to the address bus with the sixth input Pervov the RAM 9 and the third input of the second RAM 14, the second output is connected by bus synchronization with the seventh input of the first RAM 9 and the second input of the second RAM 14. The output of the first RAM 9 is connected to the information bus to a first input of the second RAM 14, the first output of which is connected to the data bus to the first input unit 15 FTESTS, a third output connected to the address bus with the second input of the third RAM 19, and a second output connected to the data bus with the input of the second detector 16, the output of which is connected to the input of the second random number generator 18, the output of which is connected to the data bus to the first input of the second unit 17 multiplication, the output of which is connected to the data bus to the first input of the third RAM 19, and the first input connected data bus to the output unit 15 FTESTS. The first output of the generator 10 signals connected to the second input of the second block 12 and synchronization with the input of the fourth block 23 synchronization and is the third output, the third output of the generator 10 signals connected to the data bus with a second input unit FTIC and is the first output and the second output connected to the input of the third block 22 synchronization, the first output of which is connected to the address bus with the fourth input of the second RAM 14, and the second output is connected by bus synchronization with the fifth input of the second RAM 14 and to the second input of the third RAM 19, the fourth WMO is which is connected to the address bus to the first output of the fourth block 23 synchronization and the output is connected to data bus with the input of the DAC 21, the output of which is connected with the second input of the adder 20, the first input of which is connected to the output of the noise generator 13 whose output is the second output device.

The whole device can be implemented by using computer technology, together with the analog circuits on the basis of the well-known radioactive elements. Remote control 1, the memory unit 2, unit 3 FACTS, block 5 FMISC, the generator 10 signals, the first block 11 synchronization, the second synchronization block 12, block 14 FTESTS, the third RAM 19, a noise generator 13, the adder 20, the DAC 21, the third block 22 synchronization, the fourth block 23 synchronization, similar to the blocks of the prototype. The first RAM 9 and the second RAM 14 differ from the prototype recording capability index value, and further reading.

The introduction of GFSC correlator, the first and second detector, the first and second random number generator, the first and second multiplier provides the possibility of the formation at the output of the radar receiver together fluctuosa and quickly fluctuosa packs reflected on the purpose of the pulses in the rate of operation of the station.

The device operates as follows. Preparations GFSC is that with the remote 1 control, which can be implemented using the control panel obsorn is on radar and computer keyboards, are set for each target number, target type, the initial coordinates of the points of beginning and settings maneuvers, as well as the initial coordinates of the points of beginning and settings maneuvers of the carrier vessel of the simulated radar. This information is entered from the keyboard of the computer both before and during work GFSC. Also in the process of working with the control panel radar enter information about operation modes of the simulated radar and about changing the operation mode. All of this information comes from the data bus in the memory unit 2 in the form of binary code. Address record this information for each goal is a number. In the memory unit 2, which represents the long-term storage device, other than that specified in the prototype stores data on the intervals of the correlation for each type of simulated targets depending on their angles. It can be implemented, for example, on the basis of the computer hard drive and memory registers.

Time diagrams of GFSC presented in figure 2.

The generator 10 produces signals at the first output (figa) pulse forward stroke of the sweep (INP), on the second output (figb) pulses reverse sweep (INAH), and the third output codes of the current bearing and elevation of MDA radar station. The repetition period INP and ENOCH (Tand), their temporal placement (tp is the time for forward travel and toxthe time-reverse), and the sequence of change codes bearing and elevation angle of maximum radiation pattern antenna (MDNA) is determined by the mode of operation of the simulated radar station (radar), as set with the remote control 1 control. For the implementation of the block 10, in part, on modeling codes, bearing and elevation angle of the antenna (high beam)can be used separate devices corresponding antenna post. As a generator INP and INK can be used blocks synchronizers radar or circuits and operating on similar principles and their parameters corresponding to the simulated radar.

The first block 11 synchronization, regardless of the generator 10 signals, generates over time tCZon the address bus (first exit) and bus synchronization (second exit) command sequence cycle of calculate and record the information in the first RAM 9 (pigv), which ends with the formation of the third output pulse of the end of the record in the first RAM 9 (high)supplied to the first input of the second unit 11 synchronization. The timing diagram cycle of calculate and record the information in the first RAM 9 is shown in figure 3. The repetition period of this cycle is the period of calculation of Tpis determined by the travel time of the goal, dizusas the maximum velocity V maxon the value of the resolution of the simulated radar range Δ d in accordance with the expression (2):

Cycle time calculation and recording information in the first RAM 9 is determined by the ratio:

The second block 12 synchronization on the first INP (second entrance) after the arrival of the pulse of the end of the record in the first RAM 9 (first entry) forms within time tCZon the address bus (first exit) and bus synchronization (second exit) command sequence cycle to overwrite data from the first RAM 9 in the second RAM 14 (figd). The timing diagram of this cycle is shown in figure 4. The duration of tCZis determined by the ratio:

The third block 22 synchronization on each coming at its input INP forms for time tuson the address bus (first exit) and bus synchronization (second exit) command sequence cycle to overwrite data from the second RAM 14 in the third RAM 19 (fige). The timing diagram of this cycle is shown in Fig.6. The duration of tCZis determined by the ratio:

The fourth block 23 synchronization on each coming at its input INP forms for time tCCon the address bus (the first exit) the bus synchronization (second exit) command sequence cycle of reading data from the third RAM 19 (figs). The timing diagram of this cycle is shown in figure 5. The duration of tCCis determined by the ratio:

Unit 11 first synchronization unit is a conventional oscillator, which can be implemented on the well-known schemes. Blocks 12, 22 and 23, respectively second, third and fourth synchronization blocks are simply waiting for the blocking generators, which can also be implemented on the well-known schema.

Use the device three of RAM due to the need to synchronize two independent and different durations of processes: calculation of the relative coordinates of the goals and values of the maximum intensity fluctuosa reflected signals from these goals, the receiver output in the rate of operation of the simulated radar vessel. After calculating the data they are immediately written into the first RAM 9, and the data calculation and recording in RAM may take several cycles of the forward stroke of the sweep. The second RAM 14 solves the problem of storing data in the period between calculations and ensuring data block 15 FTIC and block 16 of the second detector, and update information in the second RAM 14 occurs only during the forward stroke of the sweep, when the simulation reflected from the objectives of the signals at the output of the radar receiver vessel carried aetsa according to the third RAM 19. The third RAM 19 solves the problem of modeling the reflected signals from the goals in the rate of operation of the radar of the carrier vessel, and update information in the third RAM 19 occurs during the reverse sweep, when modeling reflected on the purpose of the signals is not performed.

The cycle of calculate and record the information in the first RAM 9 (see chart 3) consists of intervals of the calculation in block 3 FACTS relative coordinate, perform a comparison operation in the correlator 4, block 5 FMISC maximum signal intensity, the operation of the first detector 6 lined index for synchronization of the first generator 8 random numbers, perform in the first unit 7 multiplication the multiplication of the parameter output unit 5 FMIC and the coefficient on the output of the first generator 8 random numbers, for each of the N simulated signals from targets, recording the received values and index values in the first RAM 9. In the correlator 4 is a comparison operation from the memory block, the values of the correlation interval (τ0for the irradiated target depending on its angle with the value of the pulse repetition period (Tand), the irradiation time of the target (τregionand the review period RLS (T0). After comparing the output of the correlator 4 issued a decision to set the input variable to an int τregion0<T0or τ0Tandas an index, allowing the detectors (blocks 6 and 16) to operate on installed them in the threshold value of the index. The correlator 4 may be implemented, for example, on the chip type SP and schema matching (scheme I).

Unit 3 FACTS produces real-time calculation of the current coordinates of the targets in respect of the carrier vessel surveillance radar, which we model. At the stage of preparation of the memory unit 2 is written in the RAM block 3 FACTS initial target coordinates (bearing, distance, elevation) and its motion elements (heading, speed), and the parameters of carrier movement is simulated radar (course and speed), which if necessary can be changed directly during operation. Function block 3 FACTS can perform a special processor or computer. Address of the source data from the memory unit 2 for calculating and recording in the first RAM 9 calculated values of the relative coordinates, the maximum signal intensity and the correlation interval is the number of simulated targets.

The relative coordinates of goals - range, bearing, elevation, calculated in block 3 FACTS based on the received at its input on the data bus from the memory unit 2 data on the initial coordinates, time of beginning and characteristics of man is the enemy targets and media maneuver modulated radar station and proceed to the second input of the first RAM 9. Moreover, if the current time is less than the start time of the maneuver, the calculations used the initial or input from the remote control 1 control course and speed of the target, and if the current time is the time of the maneuver purpose, or media, to calculate the next location, use the course and speed of maneuver. The maximum intensity of the target signal corresponding to the amplitude of the video signal of the Central pulse bundles reflected from this target signal is calculated in block 5 FMIC on the basis of the entrant, on his first entrance on the data bus from the memory unit 2 data on the technical characteristics of the simulated radar (mode and transmitter power) and target type, and arriving at its second input on the data bus from the block 3 FACTS calculated values of the distance to the target and radio horizon DWGdefined by the formula:

where nand- the height of the antenna simulated radar on the vessel carrier;

HC- altitude air targets or height add-on surface targets.

The calculated value output 5 FMIC on the data bus is supplied to the first input of the first unit 7 multiplication, which is the operation of multiplication by the factor received at its second input from the output of the first generator 8 random numbers, the value of which is about in the case of the established correlation of the index with the index at the input of the first detector 6, varies from zero to one according to exponential law probability distribution (1). This allows you to change the maximum intensity of purpose in the interests of further forming together fluctuosa bundles reflected from targets pulses. In case of discrepancy between the established correlation of the index with the index value at the input of the first detector 6, the coefficient on the output of the first random number generator 8 will be constantly equal to the unit that allows you not to interfere in the formation quickly fluctuosa bundles reflected from the objectives of the signals. The value obtained from the output of the first unit 7 multiplication on the data bus is supplied to the first input of the first RAM 9. The first unit 7 multiplication in the same way as the second block 16 multiplication can be implemented on the basis of chip CTA.

The calculated values of range, bearing, elevation angle, and the maximum signal intensity, as well as the values of the correlation interval goals are written in the first RAM 9 with the arrival of the first synchronization unit 11 of the synchronization signal at the fourth input, the address corresponding to the number of goals and coming to the fifth input of the first RAM 9. After recording the calculated data on the last of N simulated the purposes of the first block 11 synchronization generates a third output pulse of the end of the record in the first RAM 9, is which is fed to the first input of the second block 12 synchronization and puts it in standby mode for team building cycle to overwrite data from the first RAM 9 in the second RAM 14.

Rewriting cycle information from the first RAM 9 in the second RAM 14 begins with the arrival to the second input of the second unit 12, the synchronization of the first INP, after bringing the unit in the readiness of a triggering pulse from the third output of the first block 11 synchronization, and consists of intervals (see chart 4) reading data from the first RAM 9 and the record information into the second RAM 14 for each of the N simulated signals from targets. The read address and the write information of the first RAM 9 and the second RAM 14 is the number of simulated targets.

Rewriting cycle information from the second RAM 14 in the third RAM 19 begins with the arrival at the input of the third block 22 synchronization of each INK and consists of intervals (see chart 6) of the computing unit 15 FTESTS for each of the N simulated signals the objectives of the current intensity, the operation of the second detector 16 with the set value of the index correlation correlator 4 to synchronize the operation of the second generator 18 random numbers, and perform a multiplication operation in the second block 17 multiplying the volume obtained from the output of block 15 FTESTS, the coefficient generated by the second generator 18 random numbers and write the calculated values in the third RAM 19. Blocks 9, 14 and 19, respectively, the first RAM, the second RAM and the third RAM can be implemented on the well-known static RAM bol is high capacity and performance, for example, CRU. The peculiarity of these RAM is that the same pins in different modes perform different functions, for example, in the recording mode information are input and read output.

The current intensity of the target signal corresponding to the amplitude of the video signal of the next pulse bundles reflected from the target signal, is calculated in block 15 FTESTS on the basis of incoming information bus, on its first input from the second RAM 14 codes bearing, elevation angle, and the maximum signal intensity of the target, and to the second input of the generator 10 of the code signals bearing and elevation of MDNA. Thus in block 15 FTEST is modulated bundles reflected from the target signals, the shape of the beam, taking into account the coefficients of attenuation introduced by the deviation of the target location of the maximum of the main lobe of the BOTTOM. In the second block 17 multiplication when triggered, the second detector 16 on the set value of the index of correlation is the modulation of each pulse bundles reflected from the target pulse coefficients calculated by the second generator 18 random numbers from the exponential distribution law of probability (1)that allows you to quickly simulate fluctuosa bundle reflected from the target signals. The second detector 16 as the first detector 6 may be implemented on the basis of well-known schemes of limiting amplifiers, constructed, for example, on the chip type CRUD and analog-to-digital Converter. In case of discrepancy between the index at the input of the detector 16 with the set value to the second input of the second block 16 multiplication from the second generator 18 random number is supplied the value of the coefficient of one, which does not affect the formation together fluctuosa bundles reflected from the target signal.

The first generator 8 random numbers and the second generator 18 random numbers can be constructed, for example, on the basis of the generator of normally distributed random numbers and analog-to-digital Converter.

Address selection from the second RAM 14 source data for the calculation is the number of simulated targets. The address of the entry in the third RAM 19 of the calculated value of the current signal intensity of the target range is to this purpose that is read from the third output of the second RAM 14 and received by the address bus to the second input of the third RAM 19.

The cycle of reading the information of the third RAM 19 begins with the arrival at the input of the fourth block 23 synchronization of each INP and consists of intervals (see chart 5) reading information from the third RAM 19 and zeroing the corresponding cell of the third RAM 19 for each discrete range. The size of each incremental step distance equal to the resolution of the simulated radar is about the distance. The read address and the zero cells of the third RAM 19 is the number value of the range selected sequentially from the interval from 1 to m, where m is the total number of samples range defined by the equation:

where Dmax- the maximum size of the field of view of the radar range;

tpH- time of the forward stroke of the sweep;

C is the speed of propagation of electromagnetic waves in the air.

When reading information about the amplitude of the video signal with a delay relative to INP, the corresponding number of selected readings range is supplied with an output of the third RAM 19 to the data bus to the input of the DAC 21, where it is converted to an analog signal. The zero cells of the third RAM 19 is carried out to prepare it for the next cycle to overwrite data from the second RAM 14.

Clearly the formation of packs together fluctuosa and quickly fluctuosa pulses when reading and writing the third RAM 19 is presented on Fig.7 and 8, respectively.

The device enables the formation of a number of signals from targets defined by the ratio of the performance of his blocks and time tpH, toxTandTpthat modern surveillance radar stations, computer equipment and radioactive elements ranges from tens to a few hundred microseconds.

With nchronization process of calculating the relative coordinates of a large number of purposes, the maximum intensity of signals from targets with the process of forming reflected from the objectives of the signals at the output of the receiver is simulated radar is achieved by the presence in the composition GFSC the first block 11 synchronization, the second unit 12 synchronization, the first RAM 9 and the second RAM 14.

The possibility of the formation of fluctuosa signals reflected from targets in the rate of operation of the simulated radar stations, including the targets in the same direction is provided by the presence in the composition GFSC third block 22 synchronization, the fourth block 23 synchronization and third RAM 19, and that the information read from the second RAM 14 is made to an address corresponding to a number of purpose, and writing information to third RAM 19 is at the address corresponding to the target range. DAC 21 when the input of some digital sequence, for example: 039, converts it into an analog signal with a certain duration and amplitude, which will correspond to the number.

The analog signal from the DAC output 21 corresponding to the video signals reflected from targets of pulses received and processed by the receiver path of the simulated radar station, is supplied to the second input of the adder 18, where it is summed with the signal generator 13 of the noise received at the first input of the adder. Generator W the mA generates a video signal, similar to the noise of the receiver of the simulated radar.

In the result of the addition output of the adder 20, which is the second output GFSC, the result is a signal similar to the signal of the simulated radar detection of targets in the zone of visibility. The first output GFSC receives signals of the angular position of MDNA, and a third output - INP. Feeding signals from outputs GFSC to the inputs of the processing unit of the radar information is provided complete simulation of the functioning of surveillance radar station that allows you to verify these devices and algorithms for their work, as well as providing training and training of operators operating these radar means.

Sources of information

1. Kuzmin SZ fundamentals of digital processing systems. - M.: Radio and communication, 1986, s-136.

2. Patent No. 5870055 U.S. CL G 01 S 7/40, 1999, Tracking radar signal generator.

3. Evidence of the Russian Federation for useful model No. 11348, IPC 6 G 01 S 7/40, 1999. The signal generator purposes (prototype).

4. Wetwetwet. Theoretical bases of radar. Moscow: “Soviet radio”, 1978

Generator fluctuosa signals containing the control panel, the block memory generator signals, the set of relative coordinates of the target (block FOCC), block the formation of the maximum signal intensity of the target (block FMISC) the first synchronization unit, the second synchronization unit, the first memory device (first RAM), the second random access memory (second RAM), block the formation of the current signal intensity of the target (block FTIC), the third synchronization unit, a fourth synchronization unit, the third storage device operatively (third RAM), digital to analog Converter (DAC), a noise generator, an adder, characterized in that it introduced the correlator, the first detector, the first random number generator, the first block multiplication, the second detector, the second random number generator, the second block multiplication, and the remote control is connected to data bus with the generator input signals and to the first input of the memory block, the first output of which is connected to data bus with the input of block FACTS and to the first input unit FMIC, and a second output connected to the data bus with the input of the correlator, the output of which is connected to data bus with the third input of the first RAM and the input of the first detector, the output of which is connected to the input of the first random number generator whose output is connected to data bus with a second input of the first block multiplication, the first input of which is connected to data bus to the output of the block FMISC, and the output connected to the data bus to the first input of the first RAM, the output of block FACTS connected and the formation of the bus with the second input unit FISTS and with the second input of the first RAM, the first output of the first synchronization unit connected to the address bus with the second input of the memory block and the fifth input of the first RAM, a second output connected to the bus synchronization with the third input of the memory block and the fourth input of the first RAM, and a third output connected to the first input of the second synchronization unit, the first output of which is connected to the address bus with the sixth input of the first RAM and the third input of the second RAM, the second output is connected by bus synchronization with the seventh input of the first RAM and the second input of the second RAM, the output of the first RAM connected to the data bus to the first input of the second RAM, the first output of which is connected to data bus with the first input unit FTESTS, the output of which is connected to data bus with the first input of the second block multiplication, the third output of the second RAM is connected to the address bus with the second input of the third RAM, and a second output connected to the data bus with the input of the second detector, the output of which is connected to the input of the second random number generator whose output is connected to data bus with a second input of the second block multiplication, the output of which is connected to the data bus to the first input of the third RAM, the first generator output signals connected to the second input of the second synchronization unit and to the input of the fourth synchronization unit and the third output condition the device, the third generator output signals connected to the data bus with a second input unit FTIC and is the first output and the second output connected to the input of the third synchronization unit, the first output of which is connected to the address bus with the fourth input of the second RAM, the second output is connected by bus synchronization with the fifth input of the second RAM and the third input of the third RAM, the output of which is connected to data bus with the input of the DAC, the output of which is connected with the second input of the adder, the first output of the fourth synchronization unit connected to the address bus with the fourth input of the third RAM, and the second output is connected by bus synchronization with the fifth input of the third RAM the output of the noise generator connected to the first input of adder whose output is the second output device.

 

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