# Random series generator

FIELD: computer science.

SUBSTANCE: device has random numbers source, N-digit selector-multiplexer, RAM, ranges control block, generations number control block, J-input OR element, AND elements block. Because series of given values of data set is broken in ranges and frequency of their appearance is set within certain limits, random series is generated with distribution law, presented in form of ranges.

EFFECT: broader functional capabilities.

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The invention relates to computing and is intended to generate a random sequence of values of the data set with the specified distribution.

A device for obtaining random numbers with a given distribution law (see Ed. St. USSR №478298, CL G 06 F 1/02, 1973), comprising a generator of uniformly distributed random numbers, multistage decoder, composition field, block elements OR output device, which includes a block of elements AND IS NOT, a counter and a decoder.

The disadvantage of the generator is that its functionality is limited, because it is not possible to generate with a given distribution law character and string constants.

Known generator of sequences of random numbers (see Ed. St. USSR №447706, CL G 06 F 1/02, 1974), containing the sensor uniformly distributed numbers, the switch, the first and second clocks, the counter, registers, valves, delay element, a transducer, a pulse shaper collection and key.

The disadvantage of the generator is limited functionality, because it is not possible to obtain sequence values of the data set.

The well-known random number generator (see Ed. St. USSR №771654, CL G 06 F G 1/02 07 15/00, 1978), contains a source ravnomerno the distributed random signals, two of the memory block, the adder, the switch and the multiplier.

Known generator allows you to generate a random number with a given accuracy of approximation as continuous distributions and distributions with singularities of the first kind. The disadvantage of the generator is its limited functionality associated with the inability to ensure the formation of a random finite sequence of values of the data set with the specified distribution.

Known the closest analogue (prototype) for their technical nature of the claimed device is a random number generator given values of the data set (see Ed. Saint of the Russian Federation No. 2138074, CL G 06 F 1/02, 1999), consisting of a source of random numbers, the first and second memory devices (designed in the form of a set of 16-and RAM each), the N-bit selector-multiplexer (made in the form of a set of 3 selectrow-multiplexers), multi-input element OR (in the form of a set of 5 items OR) and block elements And. M-bit output of block elements And where M≥ 2 - bit width of the generated numbers, is the M-bit output of the generator. The bits of the N-bit output of a source of random numbers, where N≥ 2 - number of bits sufficient for addressing the of ways a given set of data, connected to the corresponding inputs of the second group of information inputs N-bit selector-multiplexer, the N outputs of which are connected to corresponding address inputs of the first and second random access memory device. N inputs of the first group of information inputs N-bit selector-multiplexer are the corresponding bits of the N-bit address input generator. Each of the M information inputs of the first memory device is connected with the corresponding information input of the second memory device and an appropriate category of M-bit information input device. M outputs of the first memory device connected to the corresponding inputs of the multi-input OR element, and M outputs of the second memory device connected to the corresponding bits of M-bit input block elements And. Each random access memory device is equipped with inverted inputs chip select and read/write, which are the corresponding inputs the chip Select 1", "Choice crystal 2, Read/write 1, Read/write 2" of the generator. The output multi-input element OR is connected to the second control input of the block I. the control input of the source of random numbers is connected with the progress of the N-bit selector-multiplexer, with the control input of the block elements And at the same time is a control input device. Inverted enable input N-bit selector-multiplexer is the first permissive generator input.

Known generator provides a random finite sequence of values of the data set with the specified distribution.

However, the device prototype has the disadvantage of limited functionality due to the following reasons.

1. The determination of the relative occurrence of the given values of the data set, which is a consequence of prototechno job distribution.

2. The inability to generate a random sequence with the distribution presented in widely used in practice, the interval (a polygon of frequencies) without intentionally making a determination, due to the subjective nature of the job to particular values.

The aim of the invention is to increase the capacity of the generator by providing the possibility of forming a finite sequence of values of the set of data at a predetermined interval in the form of the distribution law with a random chastoty occurrence of values within the interval.

The goal stated in the random generator is posledovatelnosti is achieved by in the well-known random sequence of values of the data set containing the source of random numbers, the N-bit selector-multiplexer, random access memory, multiple-input item OR block of items And M-bit output of which, where M≥ 2 - bit width of the generated numbers is M-bit output "Result" of the generator, the bits of the N-bit output "Random values" address of the source of random numbers, where N≥ 2 - number of bits sufficient for addressing elements of a given set of data, connected to the corresponding inputs the second group of information inputs N-bit selector-multiplexer, the N outputs of which are connected to corresponding address inputs of RAM, M information inputs which are the corresponding bits of M-bit information input device, and M outputs random access memory device connected to the corresponding bits of M-bit input Random number block elements And the second enable input of which is connected to the output multi-input element OR the control input of the source of random numbers, the input N-bit selector-multiplexer control input of block elements And are combined and managing generator input, the N entrance is in the first group of information inputs N-bit selector-multiplexer are N-bit address input of the generator, inverted enable input N-bit selector-multiplexer is the first permissive generator input and inverted inputs chip select and read/write random access memory device are respectively inputs the chip Select and Read/write generator, inputs of the control unit intervals, the control unit number of generations. Multiple-input element OR performed with J inputs, where J≥ 2 - the width of the number of generations. To M-bit input value control unit intervals, where≥ 2 - the number of intervals on which split the given data set are To the N-bit input values of the spacing device. To J-bit inputs "Number of generations" control unit number of generations are To J-bit inputs "Number of generations" generator. Enter "Setup" block control the number of generations is the entrance of the Installation of the generator, and M outputs random access memory device connected to the corresponding bits of M-bit input "Random number" control unit intervals. L-bit output "Number of intervals", where L=- the number of bits sufficient to encode numbers, intervals, control unit intervals is connected to an L-bit input "interval Number" block to the control of the number of generations, the bits of the J-bit output Current value of the number of generations which is connected to the corresponding inputs of J-Vodolaga OR. The output of the J-Vodolaga element OR is connected to the second allows the input of the control unit number of generations.

The control unit interval consists of the Comparators To the input elements OR NOT, priority encoder, L inverters. The output of the l-rd, where l=1,2,... ,L, the inverter is the l-th category of L-bit output "Number of interval control unit intervals, and the input l-th inverter is connected to the l-inverted output of the priority encoder, k, where k=1,2,... K, the inverse input connected to the inverse output of the k-th input of the element OR NOT. The first and second inputs of the k-th input element OR IS NOT connected respectively to the outputs of "Equality" and "Inequality" of the k-th comparator, m-e, where m=1,2,... ,M, the inputs of the first group of information inputs of the Comparators are interconnected and are m-th category of the M-bit input "Random number" control unit intervals, and the m-th entry of the second group of information inputs of the k-th comparator is the m-th digit of the k-th M-bit input values of the intervals of the block.

Control unit number of generations consists of a decoder low level, inverter, input elements OR NOT, TO a reversible counter, J selectors-multiplexers, each of the C which is equipped with L inputs of the choice of data and information inputs. Each of the L inputs of the decoder low level is connected to the corresponding inputs of the data selection J selectors-multiplexers and is the corresponding digit of the input Number of interval control unit number of generations. The first input of the k-th input element OR IS NOT connected to k-inverted output of the decoder low level. Second input To two-input elements OR are NOT interconnected and connected to the inverter output. The input of the inverter is the second permissive input control unit number of generations. Inverted output of the k-th input element OR IS NOT connected to the counting input of the k-th reversible counter. J information inputs of the k-th reversible counter are the corresponding bits of the k-th J-bit input "Number of generations" control unit number of generations. Inverse inputs of the Gating appointment of each reversible counter connected with each other and the entrance of the Installation control unit number of generations. In this case, the j-th output where j=1,2,... ,J, k-reversible counter is connected to the k-information input of the j-th selector is a multiplexer. Outputs J selectors-multiplexers are the corresponding bits of the J-bit output Current value of the number of generations" block.

This goal is achieved by introducing a control unit in which Ermolov, control unit number of generations, providing sets the number of intervals, their boundaries, the definition of the set of generated numbers to one of the specified intervals and the reduction specified for each interval the number of generations.

Conducted by the applicant's analysis of the level of technology has allowed to establish that the analogs are characterized by the sets of characteristics is identical for all features of the claimed technical solution, no. Therefore, the claimed invention meets the condition of patentability "Novelty".

Search results known solutions in this and related areas of technology in order to identify characteristics that match the distinctive features of the prototype of the characteristics of the claimed invention have shown that they do not follow explicitly from the prior art. Of certain of applicant's prior art there have been no known impact provided the essential features of the claimed invention transformations on the achievement of the technical result. Therefore, the claimed invention meets the condition of patentability "Inventive step".

The claimed device illustrated by the drawings, in which

figure 1 - random sequence;

figure 2 - control unit intervals;

figure 3 - control unit quantities of the generations;

figure 4 - block elements And;

figure 5 - table of operating modes of the generator;

figure 6 - graphical representation of the operation of the generator;

figure 7 - illustration of the differences cycles generating device of the prototype and the proposed device.

The random sequence (see figure 1) consists of a source of random numbers 1, N-bit selector-multiplexer 2, RAM 3, the control unit interval 4, the control unit number of generations 5, J-Vodolaga element OR 6, block elements And 7.

The control input 10 of the source of random numbers 1 is a control input of the generator and is connected to the selection input SE of the N-bit selector-multiplexer 2 and control input of the block elements And 7. The first group of N information inputs A_{1}-A_{N}N-bit selector-multiplexer 2 is an N-bit address input generator. The inputs of the second group of N information inputs B_{1}-B_{N}N-bit selector-multiplexer 2 is connected to the corresponding bits of the N-bit output of the Random value of the address" 12 source of random numbers 1. Inverted enable inputN-bit selector-multiplexer 2 is the first permissive input 8 of the generator. N outputs Q_{1}-Q_{N}N-bit selector-multiplex the ora 2 connected to the corresponding address inputs A_{
1}-A_{N}random access memory 3, M information inputs D_{1}-D_{M}which are the corresponding bits of M-bit information input device 11. Random access memory device equipped with 3 negative input select crystaland negative input read/writethat are respectively input "Choice crystal" 14 and the input of the Read/write generator 15. M outputs_{1}-C_{M}random access memory connected to the corresponding bits of M-bit input "Random number" 16 control unit intervals 4 and block elements And 7. To M-bit input value 17_{1}-17_{K}control unit intervals of 4, are To the M-bit input value generator, the L-bit output "interval Number" 18 control unit intervals 4 is connected to an L-bit input "Number of interval control unit number of generations 5. To J-bit inputs "Number of generations" 19_{1}-19_{K}control unit number of generations 5 are To J-bit inputs "Number of generations" generator. Enter "Setup" 20 control unit number of generations 5 is the entrance of the Installation of the generator. The bits of the J-bit output Current value of the number of generations" 21 block counter is La number of generations 5 connected to the corresponding inputs of the J-Vodolaga element OR 6.
The output 22 of the J-Vodolaga element OR 6 is connected to the second allows the input of the control unit number of generations 5 and the second allows the input of block elements And 7, the M-bit output "Result" which is the M-bit output Result 23 of the generator.

Source of random numbers 1, designed to generate N-bit random address known and shown, for example, in the book Mpobile "Generating random signals" (M.: Energy, 1971, s, Fig.6-13).

J-shadowy element OR 6 is intended for comparison with the zero current value of the number of generations. The scheme of realization of such element OR known. See, for example, in the book: Bvitamin, Sviatoslavsky, Nasardinov and other "Handbook of integrated circuits". - 2nd ed., Rev. and supplementary): Energy, 1981, pp.109.

N-bit selector-multiplexer 2 is designed for switching on its N-bit output signals of one of the two groups of N information inputs. The scheme of realization of the N-bit selector-multiplexer known. See, for example, in the book: "the Logical IP CR, CR" (Handbook Ies and others In two parts. Part 1. - M.: Binom, 1993, s).

Random access memory device 3 is intended to store values of a given data set. The scheme of realization of the random access memory is known. See, for example, in the book: Wllile "warnie digital circuits", M.: Radio and communication, 1987, 164-166.

Block elements And is intended for filing with randomly selected values of the data set in the output if there are two control signals at its respective inputs. Block elements And can be implemented in various ways. In particular, the option of building block elements And are presented in figure 4. Block elements And consists of M trehshipovyh elements And. the Second inputs of all trehshipovyh elements And included in parallel and are managing input 10 of block elements And. Third control inputs of all trehshipovyh elements And included in parallel and are the second permissive input 22 of the block elements And. Each category of M-bit input "Random number" 16 block elements And connected to the first input of the corresponding element I. the Outputs of all elements And 7.1_{1}-7.1_{M}are the appropriate category of the M-bit output "Result" block elements I.

Trekhgolovy element And is designed for switching its output signal on one of its inputs in the presence of permissive signals high logic level to the other two inputs. Scheme implementation trehshipovyh elements And known. See, for example, in the book: "the Logical IP CR, CR" (Handbook Ies and others In two parts. Part 2. - M.: Binom, 1993, s-259).

The monitoring unit interval is designed to set the lower bounds of the intervals,
determine the number of interval belongs to the generated value, and transfer it in binary code at its output. The control unit intervals may be implemented in various ways. In particular his scheme, shown in figure 2, contains To Comparators 4.1_{1}- 4.1_{K}To input elements OR NOT 4.2_{1}-4.2_{K}, encoder priorities 4.3, L inverters 4.4_{1}-4.4_{L}. The elements are interconnected as follows. The output of the l-rd, where l=1,2,... L, the inverter is the l-th category of L-bit output "interval Number" 18 control unit intervals. The input l-th inverter is connected to the l-inverted output of the priority encoder 4.3, k, where k=1,2,... K, the inverse input connected to the inverse output of the k-th input of the element OR NOT. The first and second inputs of the k-th input element OR IS NOT connected respectively to the outputs of "Equality" and "Inequality" (which in figure 2 are indicated by the symbols "=" and ">", respectively) of the k-th comparator, m-e, where m=1,2,... ,M, the inputs of the first group of information inputs A_{1}-A_{M}Comparators are interconnected and are m-m discharge Bitwise login "Random number" 16 control unit intervals. Thus the m-th entry of the second group of information inputs B_{1}In_{m}the k-th comparator is the m-th digit of the k-th M-bit input value unit stake is the control interval.

Comparators 4.1_{1}-4.1_{K}designed to compare two M-bit numbers and the formation of the comparison. Job description and diagram of the comparator is shown, for example, in the book: Wllile "Popular digital circuits", M.: Radio and communication, 1987, .183-184.

Items OR NOT 4.2_{1}-4.2_{K}- are used to form at its output low-level signal in case of occurrence of signal on any one of the output "a=b" or ">" relevant Comparators. The implementation of the elements OR IS NOT known. See, for example, in the book: "the Logical IP CR, CR" (Handbook Ies and others In two parts. Part 1. - M.: Binom, 1993, s-247).

Encoder priorities 4.3 is designed to convert low-level signal on one of its inputs in binary code at its output, and the conversion is carried out taking into account the priorities of the signals corresponding to the numbers of inputs. The implementation of the priority encoder is known. See, for example, in the book: Law, Nsize and others, Handbook of Digital integrated circuits", - M.: Radio and communication, 1994, p.40-41.

Inverters 4.4_{1}-4.4_{to}designed to invert signals with inverted outputs of the priority encoder. The implementation of the inverter is known. See, for example, in the book: "the Logical IP CR, CR" (Handbook Ies and others In two parts. Part 2. M.: Binom,
1993, s-472).

Control unit number of generations is intended to specify the number of generations for each of the intervals, forming at its output current value of the number of generations when submitting his entry number of the selected interval in the binary code and reduce the per unit current value of the number of generations for the corresponding interval. Control unit number of generations can be implemented in various ways. In particular his scheme, shown in figure 3, contains the decoder low level 5.1, 5.2 inverter, input elements OR NOT 5.3_{1}-5.3_{K}To the reversible counters 5.4_{1}-5.4_{K}, J selectors multiplexers 5.5_{1}-5.5_{J}, each of which is equipped with L inputs of the data selection S_{1}-S_{L}and To the information inputs of the I_{1}-I_{K}. Each of the L inputs of the decoder low level 5.1 is connected to the corresponding inputs of the data selection for each of the J selectors multiplexers 5.5_{1}-5.5_{J}and is the corresponding discharge input "interval Number" 18 control unit number of generations. The first input of the k-th (k=1,2,... K) input of the element OR NOT connected to k-inverted output of the decoder low level, and the second input To two-input elements OR are interconnected and connected to the output of the inverter 5.2, the entrance of which is the second authorize the named input unit 22.
Inverted output of the k-th input element OR IS NOT connected to the counting input "-1" k-reversible counter. J information inputs D_{1}-D_{J}the k-th reversible counter are the corresponding bits of the k-th J-bit input "Number of generations" 19_{1}-19_{K}block. Inverse inputs of the Gating appointmenteach reversible counter 5.4_{1}-5.4_{K}interconnected and enter "Setup" 20 control unit number of generations. When this j-th output (j=1,2,... ,J) of k-reversible counter is connected to the k-information input of the j-th selector is a multiplexer. Outputs J selectors multiplexers 5.5_{1}-5.5_{J}are the relevant bits of the J-bit output Current value of the number of generations" 21 block.

The decoder low level 5.1 is designed to convert binary code at its input in a low-level signal on one of its outputs, and output number corresponds to the number in binary code, the input decoder. The implementation of the decoder of the low level is known. See, for example, in the book: Law, Nsize and others, Handbook of Digital integrated circuits", - M.: Radio and communication, 1994,pp.42-43.

Items OR NOT 5.3_{1}-5.3_{K}are used to form at its output a high signal in the case of simultaneous occurrence of low level signals at the inputs.
The implementation of the elements OR IS NOT known. See, for example, in the book: "the Logical IP CR, CR" (Handbook Ies and others In two parts. Part 1. - M.: Binom, 1993, s-247).

The inverter 5.2 is designed to invert the signal received at the input Resolution 22 of the control unit number of generations. The implementation of the inverter is known. See, for example, in the book: "the Logical IP CR, CR" (Handbook Ies and others In two parts. Part 2. - M.: Binom, 1993, s-472).

Reversible counters 5.4_{1}-5.4_{K}designed to store the current value of the number of generations for each of them To intervals and reduce the value specified on the unit when it arrives at their counter input signal of high level. The scheme of realization of the reversible counter are known. See, for example, in the book: "the Logical IP CR, CR" (Handbook Ies and others In two parts. Part 1. - M.: Binom, 1993. p.71).

Selectors-multiplexers 5.5_{1}-5.5_{J}designed for switching signal on one of the information inputs to the output, while the input number is determined by the binary code, submitted to the selection input data selectors-multiplexers. The implementation of the selector-multiplexer known. See, for example, in the book: "the Logical IP CR, CR" (Handbook Ies and others In two parts. Part 1. - M.: Binom, 1993, p.194).

The claimed device is STV works as follows.

In the initial position on the first permissive input 8 input "Choice crystal" 14, the entrance of the Installation device 20 is set to the high logic level, and the control input 10 - low logic level.

The device operates in two modes, the first mode ready the device for generation; the second generation mode. In this mode of the device is determined by the combination of signals on the first permissive input 8 and the control input 10 of the device (see figure 5).

In the training mode of the generator for operation following steps.

The first step is adding the set A={_{0}, a_{1}, a_{2}... and_{R}} the values of the elements of a given data set (see Fig.6) in random access memory, while

0≤ and_{r}≤_{}2^{m}-1 is an element of a given set of data, where r=0,1,... ,R;

M≥ 2 - number of bits sufficient to represent the values of a given set of data;

1≤ R≤ 2^{N}-1 is the number of elements of a given set of data;

N≥ 2 - the number of binary digits, sufficient for addressing elements of a given set of data.

The second step is to install the set In={b_{1}b_{2}b_{3},... , b_{K}} the values of the lower bounds of the intervals are divided into a specified data set (see Fig.6), while

0≤ b_{k}≤_{}2^{M}-1 - the value is their lower boundary of a k-interval,
where k=1,2,... ,K and 0≤ b_{1}≤_{}b_{2}≤_{}... ≤_{}b_{To};

1≤... 2^{L}-1 - the number of intervals;

L=- the number of bits sufficient to encode the sequence number interval.

Thus, a given data set is divided into the following intervals:

1st interval [b_{1}; b_{2}];

2nd interval [b_{2}; b_{2}];

K-th interval [b_{K}; (2^{m}-1)].

The third step is to install the set D={d_{1}d_{2}d_{3},... , d_{K}} the number of generations for each interval (see Fig.6), while

1≤ d_{K}≤_{}2^{J}-1-the number of generations for the k-th interval, k=1,2,... ,K

J≥ 2 - number of bits sufficient to represent the values of the number of generations.

The first step in preparing the device for operation includes the following steps. N-bit address input device 9 to the first group of information inputs A_{1}-A_{N}selector multiplexer 2 is supplied N-bit address, which must be recorded the value of the first element and_{0}. On the first permissive input 8 devices establish a low logic level, which is fed to the enable input E of the selector-multiplexer 2 that the presence of a low logic level on upravlajushemu 10 device causes the switching addresses,
installed on the inputs A_{1}-A_{N}selector-multiplexer, the N-bit output Address 13, by which it is fed to the address inputs A_{1}-A_{N}random access memory device 3. By M-bit information input device 11 to the information inputs of the D_{1}-D_{M}RAM serves the value of the first element and_{0}a given set of data, which are recorded in the random access memory when receiving on its inputsandlow level signals at the inputs of the "Choice crystal" 14 and "Read/write" 15 respectively. Then N-bit address input device 9 to the first group of information inputs A_{1}-A_{N}selector multiplexer 2 is supplied N-bit address, which must be recorded the value of the second element of a_{1}and on the M-bit information input device 11 to the information inputs of the D_{1}-D_{M}RAM serves the value of the element a_{1}and, by setting the low level signals at the inputs of the "chip Select" 14 and "Read/write" 15, write the value of a_{1}in random access memory. Similarly, in the random access memory device is updated with any R elements values satanophobia data.
Then on the first permissive input 8 devices set a high logic level.

The second step in preparing the device for operation as follows. On the M-bit input value 17_{1}-17_{K}device set the lower bounds of the intervals. When the input 17_{1}set the value of b_{1}coming to the second group of inputs B_{1}In_{M}comparator 4.1_{1}at the entrance 17_{2}the value of b_{2}coming to the second group of inputs B_{1}In_{m}comparator 4.1_{2}at the entrance 17_{K}the value of b_{to}coming to the second group of inputs B_{1}In_{m}comparator 4.1_{K}.

The third step of preparing the device for operation includes the following steps. On J-bit inputs "Number of generations" 19_{1}-19_{K}device set the number of generations. When the input 19_{1}set the value of d_{1}coming to the information inputs of the D_{1}-D_{J}reversible counter 5.4_{1}at the entrance 19_{2}the value of d_{2}coming to the information inputs of the D_{1}-D_{J}reversible counter 5.4_{2}at the entrance 19_{K}the value of d_{K}coming to the information inputs of the D_{1}-D_{J}reversible counter 5.4_{K}. Then input "Setting" 0 establish a logic low
which is fed to the input Gating appointmentall reversible counter, which provides the initial installation of the reversible counters in accordance with the inputs 19_{1}-19 to values.

After the above steps, the unit is ready for operation.

In the generation mode operation of the device is as follows. On the first enable input 8 device serves low logic level, which is fed to the input resolutionselector-multiplexer 2, the control input 10 serves a high logical level, which is fed to the input selection SE selector-multiplexer 2, which provides switching addresses coming from the output of a source of random numbers 1, for N-bit output Address 12, by which it is fed to the address inputs A_{1}-A_{N}random access memory 3.

Source of random numbers 1 in the presence of the control input device signal of high voltage level to generate N-bit addresses, which through the selector-multiplexer 2 are received at address inputs A_{1}-A_{N}random access memory device 3. Input "Choice crystal" 14 inputRAM serves low level signal, and input "H is tell/write 15 on the entrance
RAM serves the high level signal, which corresponds to the read data. Thus, in accordance with a random addresses generated by the source of the random numbers is reading the values of elements A={_{0}and_{1}and_{2},... , a_{R}} given a set of data from random access memory, which M-bit output "Random number" is coming to the inputs of the control unit intervals 4 and block elements And 7.

Read from the random access memory is a_{r}by M-bit input "Random number" 16 is supplied simultaneously to the first group of information inputs A_{1}-A_{m}all Comparators 4.1_{1}-4.1_{M}control unit intervals 4, where the comparison values and the values of the lower bounds given intervals In={b_{1}b_{2}b_{3},... ,b_{to}}. If the received value and_{r}belongs to the k-interval, i.e. the condition b_{k}≥_{}and_{r}<b_{k+1}at the appropriate outputs ">" or "=" Comparators 4.1_{1}-4.1_{k}signals are formed of a high logic level, the output "A>" and "a=b" Comparators 4.1_{k+1}-4.1_{K}will be a signal of low logic level. The signals from the output "A>" and "a=b" each comparator is combined and inverted input elements OR NOT 4.2_{
1}-4.2_{K}and then proceed to the corresponding inverted inputsencoder priorities 4.3 (inputthe priority encoder is not used, because the numbering of intervals begins with unit). Thus, if the condition b_{k}(a_{r}b_{k+1}on inputsencoder priorities 4.3 will be installed signals at a lower logical level, and inputssignals high logic level. In this case, the L-bit outputencoder priorities 4.3 will be generated binary code in inverse representation corresponding to the maximum number of input number of inputsinstalled low logic levels, i.e. code that corresponds to the number k - number interval, the value belongs to and_{r}. The resulting code after inverting elements 4.4_{1}- 4.4_{L}arrives at the L-bit output "interval Number" 18 and further to the input of the control unit number of generations 5.

In the control unit of the number of generations 5 code corresponding to the number of the interval, the value belongs to and_{r}comes simultaneously to the inputs of Y_{1}-Y_{L}decoder low level 5.1 and the inputs of the data selection S_{1
-SLall selectors-multiplexers 5.51-5.5J. At the k-th output of the decoder low level 5.1 signal is formed of a low logic level, and outputs the Y selectors-multiplexers 5.51-5.5Jswitched by signals from outputs Q1-QJthe k-th reversible counter. Thus, the number of generations dkcorresponding to the number of the interval, the value belongs to andrcomes to J-bit output Current value of the number of generations" 21 and then to the J-shadowy element OR, the output of which in the case of inequality values for the number of generations to zero (dk≠0) is formed by a high signal level on the second allows the input 22 is fed simultaneously into the block elements And 7 and the control unit number of generations 5.}

The high signal received on the second allows the entrance 22 to the control unit number of generations 5, is inverted and, together with the signal of the low logic level is generated at the k-th output of the decoder low level 5.1 produces a signal of high logical level at the output of the k-th element OR NOT. This decreases the value set in the k-th reversible counter unit, which corresponds to a decrease in per unit values of d_{k}- the number of generators is the second to k-th interval,
i.e. the interval, the value belongs to and_{r}.

Receipt of a high signal on the second allows the entrance 22 to the block elements And 7 in the presence of a high signal at the control input 10 provides a flow values and_{r}output from the memory device to the output Result 23 of the generator.

The device stops working when all the elements of the set D={d_{1}d_{2}d_{3},... , d_{K}}, set in the reversible counters 5.4_{1}-5.4_{K}become equal to zero.

The device prototype (see figa, 7b) for each element a_{r}a given data set, A={_{0}, a_{1}and_{2}... , and_{R}} hard coded number (castest)his appearances on the output device that you are performing repeated cycles of generation, performed with the same initial data leads to the determination of the frequency of occurrence of values of the data set within each cycle.

Unlike the device of the prototype, the proposed device (see figv, 7 g) the specified dataset A={a_{0}, a_{1}, a_{2}... , and_{R}} is divided into K intervals and for each interval specifies the number dk of occurrences of the values found within it. At the same time. as for the first cycle generation, and all subsequent, ka is the of values and_{
r}where r=0,1,... ,R, of a given set of data appears at the output of a random number of times. The sum of the random values of the number of occurrences of elements of a given set of data belonging to the k-interval in the first and subsequent cycles of generation is equal to d_{k}(see Fig 7b, 7G).

THE SOURCES OF INFORMATION.

1. The copyright certificate of the Russian Federation No. 2138074, CL G 06 F 1/02 (prototype).

2. USSR author's certificate No. 771654, CL G 06 F 1/02, G 07 15/00, 1978.

3. USSR author's certificate No. 478298, CL G 06 F 1/02, 1973.

4. USSR author's certificate No. 447706, CL G 06 F 1/02, 1974.

5. Mponi. Generating random signals. - Moscow: Energiya, 1971, - 240 C.

6. Bvitamin, Sviatoslavsky, Nasardinov and other "Handbook of integrated circuits". - 2nd ed., Rev. and supplementary): Energy, 1981, 816 S.

7. Wllile "Popular digital circuits", M.: Radio and communication, 1987, - 352 S.

8. Law, Nsize and others, Handbook of Digital integrated circuits", - M.: Radio and communication, 1994.

9. Reference IAS and other "Logical IP CR, CR". In two parts. Part 1. - M.: Binom, 1993, - 256 S.

10. Reference IAS and other "Logical IP CR, CR". In two parts. Part 2. - M.: Binom, 1993, - 244 C.

1. Generator random sequence containing a source of random numbers, the N-bit selector-multiplexer, operative the second storage device,
multiple-input item OR block of items And M-bit output of which, where M≥2 - bit width of the generated numbers is M-bit output “Result” of the generator, the bits of the N-bit output “Random values” address of the source of random numbers, where N≥2 - number of bits sufficient for addressing elements of a given set of data, connected to the corresponding inputs of the second group of information inputs N-bit selector-multiplexer, the N outputs of which are connected to corresponding address inputs of RAM, M information inputs which are the corresponding bits of M-bit information generator input and M outputs random access memory device connected to the corresponding bits of M-bit input Random number block elements And the second enable input of which is connected to the output multi-input element OR the control input of the source of random numbers, the input N-bit selector-multiplexer control input of block elements And are combined and managing generator input, the N inputs of the first group of information inputs N-bit selector-multiplexer are N-bit address generator input inverted enable input N-bit selector-multiplexer are the two what is the first permissive input of the generator,
and inverted inputs chip select and read/write random access memory device are respectively inputs the chip Select and Read/write generator, characterized in that it further introduced the control unit intervals and the control unit number of generations, and the item OR performed with the J-inputs, where J≥2 - the width of the number of generations, To the M-bit input value control unit intervals, where≥2 - the number of intervals into which is divided the specified data set are To the M-bit input values intervals of the generator, To the J-bit inputs “Number of generations” control unit number of generations are To J-bit inputs “Number of generations” generator input “Setting to” block control the number of generations is the entrance of the Installation of the generator, and M outputs random access memory device connected to the corresponding bits of M-bit input “Random number” control unit intervals, the L-bit output “Number of intervals”, where L=[log_{2}K]+1 - the number of bits sufficient to encode numbers, intervals, control unit intervals is connected to an L-bit input “Number of interval control unit number of generations, the bits of the J-bit output Current value of the number of generations to the showing connected to the corresponding inputs of the J-Vodolaga element OR
the output of which is connected to the second allows the input of the control unit number of generations.

2. The device according to claim 1, characterized in that the control unit interval consists of the Comparators To the input elements OR NOT, priority encoder, L inverters, the output of the l-rd, where l=1, 2,..., L, the inverter is the l-th category of L-bit output “Number of interval control unit intervals, and the input l-th inverter is connected to the l-th inverted output of the priority encoder, k, where k=1, 2,..., K, the inverse input connected to the inverse the output of the k-th input of the element OR NOT, the first and second inputs of the k-th input element OR IS NOT connected respectively to the outputs of “Equality” and “Inequality” of the k-th comparator, m-e, where m=1, 2,..., M, the inputs of the first group of information inputs of the Comparators are interconnected and are m-th category of the M-bit input “Random number” control unit intervals, and the m-th entry of the second group of information inputs of the k-th comparator is the m-th category of k-th M-bit input values of the intervals of the block.

3. The device according to claim 1, characterized in that the control unit number of generations consists of a decoder low level, inverter, input elements OR NOT, TO a reversible counter, J selectors-multiplexers, each of which is equipped with L inputs of the data selection and To information and inputs, each of the L inputs of the decoder low level is connected to the corresponding inputs of the data selection J selectors-multiplexers and is the corresponding digit of the input Number of interval control unit number of generations, the first input of the k-th input element OR IS NOT connected to the k-th inverse of the output of the decoder, the low level and the second input To two-input elements OR are NOT interconnected and connected to the inverter output, the input of which is the second permissive input control unit number of generations, the inverted output of the k-th input element OR IS NOT connected to the counting input of the k-th reversible counter J information inputs of the k-th reversible counter are the corresponding bits of the k-th L-bit input “Number of generations” control unit number of generations, the inverse inputs of the Gating appointment of each reversible counter connected with each other and the entrance of the Installation control unit number of generations, the j-th output, where j=1, 2,..., J, k-reversible counter is connected to the k-th information input of the j-th selector-multiplexer, the outputs J selectors-multiplexers are the corresponding bits of the J-bit output Current value the number of generations” control unit number of generations.

**Same patents:**

**FIELD: pulse engineering.**

**SUBSTANCE: proposed flip-flop device has RS flip-flops 3, 16, EXCLUSIVE OR gates 1, 2, NAND gates 5, 6, NOR gates 10, 11, resistors 4, 7, 12, 13, capacitors 14, 15, memory items 8, 9 built around magnetic core with rectangular hysteresis loop and single center-tapped coil, input bus 21, and common bus 22. Combining read and write coils of memory items 8, 9 makes it possible to increase turn number in read and write coils by 1.5 times, in each of half-coils of memory items 8 and 9, which reduces magnetizing current through cores of memory items 8 and 9 approximately by 1.5 times due to enhancing ratings of limiting resistors 4 and 7.**

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**FIELD: pulse engineering.**

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**EFFECT: reduced input current from power supply.**

**1 cl, 1 dwg**

**FIELD: pulse engineering.**

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**EFFECT: reduced input current from power supply.**

**1 cl, 1 dwg**

**FIELD: pulse engineering.**

**SUBSTANCE: proposed flip-flop device has RS flip-flop 1, EXCLUSIVE OR gates 2,3, NOR gates 4, 5, inverters 6, 7, 8, diodes 15, 16, resistors 9 through 12, capacitors 13, 14, memory items 17, 18 built around magnetic cores with rectangular hysteresis loop and single coil, input bus 19, and common bus 20. Combining write and read coils of memory items 17 and 18 makes it possible to increase coil number of write and read coils by 1.5 times, in each of half-coils of memory items 17 and 18, which reduces magnetizing current through cores of memory items 17 and 18 by approximately 1.5 times due to enhancing ratings of limiting resistors 11 and 12.**

**EFFECT: reduced input current from power supply.**

**1 cl, 1 dwg**

**FIELD: pulse engineering, computer engineering, and control systems.**

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**1 cl, 1 dwg**

**FIELD: digital pulse engineering.**

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**1 cl, 1 dwg**

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SUBSTANCE: method includes generating random numbers with use of displacement register with check connection, elementary digit of which is a q-based symbol (q=2^{l}, l - binary symbol length) at length of q-based digits register, in check connection networks nonlinear two-parameter operations on q-based symbols F (u_{b}, u_{d}) are used, on basis of random replacement tables, for generating next random number values z_{1}=F(u_{i}, u_{j}), z_{2}=F(u_{t}, u_{m}), z_{g}=F(z_{1}, z_{2}) are calculated, where u_{i}, u_{j}, u_{t}, u_{m} - values of filling of respective register digits, value of result in check connection networks z_{g} is recorded to g digit of displacement register and is a next result of random numbers generation, after which displacement of register contents for one q-based digit is performed.

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3 cl

FIELD: cryptography.

SUBSTANCE: method includes generating random numbers with use of displacement register with check connection, elementary digit of which is a q-based symbol (q=2^{l}, l - binary symbol length) at length of q-based digits register, in check connection networks nonlinear two-parameter operations on q-based symbols F (u_{b}, u_{d}) are used, on basis of random replacement tables, for generating next random number values z_{1}=F(u_{i}, u_{j}), z_{2}=F(u_{t}, u_{m}), z_{g}=F(z_{1}, z_{2}) are calculated, where u_{i}, u_{j}, u_{t}, u_{m} - values of filling of respective register digits, value of result in check connection networks z_{g} is recorded to g digit of displacement register and is a next result of random numbers generation, after which displacement of register contents for one q-based digit is performed.

EFFECT: higher speed and efficiency.

3 cl