Device for controlling knowledge quality estimation process in remote education system

FIELD: computers.

SUBSTANCE: device has registers, comparators, signs input block, counters, adder, decoder, memory block, means for determining support test address, triggers, AND elements, groups of AND elements, OR elements, delay elements.

EFFECT: higher precision.

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The invention relates to computing, and in particular to devices for controlling the receipt of assessing the quality of knowledge in distance learning system, and can be used to control students ' knowledge.

The known device that could be used to solve the task [1, 2].

The first known device contains a computer unit connected to the input of the functional characteristics and logical processing, the outputs of which are connected to the memory unit, the display unit connected to the computing unit and to the unit of decision making [1].

A significant disadvantage of this device is its limited functionality due to the fact that the description of input situations for training and quality control knowledge is possible only in space for a limited number of signs, which leads to low efficiency of its use.

Known and other device containing memory blocks, Comparators, counters, registers, triggers, groups of items AND, OR, elements of the delay [2].

The last of the above technical solutions most closely described.

Its disadvantage is the low accuracy due to the lack of control of knowledge on multi-criteria parameters used in the description of input situations in the space of the functional characteristics.

The purpose of the invention is improving the accuracy of the device by the use of multi-criteria parameters for detecting and correcting errors.

This objective is achieved in that the device containing the first register,

information the input of which is the first information input device, and the clock input of the first synchronizing input of the second register, an information input connected to the output of the memory block, which is the first information output device, the third register, the information input of which is the second information input of the clock input is the second clock input devices, and output connected to one input of the first comparator, another input connected to the output of the second register, and outputs connected to one inputs of the first and second elements, And accordingly, the second comparator, one input of which is connected to the output of the first counter, and the outputs are connected to one inputs of the third and fourth elements, And accordingly, the first element OR, one input of which is connected to the output of the third element, And the output of the first element OR is connected to the input of the first delay element, the output of which is connected to the input of the second delay element, the output of which is connected to the input of the read memory block and the input of the third delay element, the pulse from the third element And is supplied to the counting input of the first counter, the clock pulse from the fourth element And is supplied on the installation input of the first counter, the clock pulse delayed by the fourth delay element for recording time code in the third the register, with the output of the fifth delay element is fed to the first and second elements And the first trigger, a single entry which is the first Manager of the input device, the second element OR,

one input of which is the second managing input devices, and output connected to the set input of the first flip-flop, the fourth delay element, the input of which is connected to the second clock input devices, and output connected to the clock input of the first comparator, while the clock pulse, delayed by the fourth delay element for recording time code in the third case comes from the output of the fifth delay element to the first and second elements And a second trigger unit whose input is connected to the output of the second element And connected to the counting input of the second counter, the first group of items, one input of which is connected with the output of the fourth element And the second element group, And some inputs are connected to the outputs of the second register, the third element OR, one input of which is connected to the output of the first element And the fifth and sixth elements, one input of which is connected with a unit output of the first trigger, the seventh element And one input connected to an inverted output of the first trigger clock pulse from the fourth element And is supplied to the clock output as a signal about the end of the presentation of tests, with an output of the third delay elements receives the clock pulse to the input of the fourth element And the input of the second register on the first signal output a signal “True” from the fifth element And code the correct answer from the second group of elements And is issued on the display screen, with the sixth element And receives a pulse on the second signal output device in signal quality Error,

the clock pulse from the fourth element And is supplied on the installation input of the second counter and the second element OR entered the keys to the reference address of the test, an information input connected to the output of the first register, a clock input connected to the first clock input the device information output connected to another input of the second comparator, and a clock output connected to another input of the first element OR adder, one data input of which is connected to the information output of the determinant of the reference address of the test, another information input is connected to the output of the first counter, the clock input connected to the output of the first delay element setting input connected to the output of the fourth element, And the output of the adder is connected to the address output of the memory block, the decoder, the input connected to the output of the second counter, and outputs connected to the other input elements And the first group, while the other input of the fifth element And is connected to the output of the first element And the other input of the sixth element And is connected to the output of the second element And the other input elements And the second group are connected to individual outputs of the first and second triggers, the other input of the seventh element And is connected to the output of the second element, And a seventh output element And is connected to another input of the third element OR the output of which is connected to another input of the third element And output element And the first group signal is given a “score” on the second information output device.,

The invention is illustrated by drawings, where figure 1 shows the block diagram of the device, figure 2 shows an example of a specific structural embodiment of the determinant of the reference address of the test, figure 3 shows the structure of the presentation code of the message identifier of the reference address of the test, and figure 4 presents the structure of the code messages stored in the memory unit of the device.

The device (1) contains the first 1, second 2 and third 3 registers, the first 4 and second 5 Comparators, the first 6 and second 7 meters, the adder 8, a decoder 9, block 10 memory keys 11 of the reference address of the test, the first 12 and second 13 triggers, the first 14, 15 second, third 16, 17 fourth, fifth, 18, 19 sixth and seventh 20 elements, And the first 21-23 24 and the second group of elements, And the first 25 and second 26 and third 27 elements OR, the first 28 and second 29, the third 30, 31 fourth and fifth 32 delay elements.

Figure 1 also shows the first 33 and second 34 information input device, the first 35 and second 36 clock inputs of the device, the first 37 and second 38 control inputs of the device and the first 39 and second 40, 41 third information output device, the first 42 and second 43 and output signals and synchronizing 44 exit.

The keys 11 of the reference address of the test (Fig. 2) contains a decoder 45, a memory unit 46, made in the form of a persistent storage device, the register 47, the elements 48 to 50 And the elements 51 and 52 of the delay. The drawing also shows the clock input keys 33, the information input 53, the information output 54 and the clock output 55.

All nodes and elements of the device are made on the standard of potentially switching elements.

The basis of the device to obtain the knowledge assessment is based on assignments for self-control and control implemented in these two different modes of operation. The methodology of the tests (i.e. a series of test tasks for self-control and control of knowledge of students in any subject area in General are similar. However, there are differences. Thus, the direct and sole purpose test is a test of knowledge on a particular discipline, while the tasks for self-control include elements of training, because in this case, while testing reported correct answers [3].

On this basis, the requirements for the correctness of the compilation of the test more stringent, because the analyzed level of knowledge should be adequately reflected some of the quantitative indicators. To the prepared tests really made it possible to assess the degree of learning, they must be prepared in accordance with the specific requirements of the classical theory of testing [4].

The device operates as follows.

Client workstation control knowledge consists of a terminal having a screen for playback tests, examples of which are shown in the above-mentioned source [3], and the keyboard of the personal computer. The management control of knowledge in the system of remote training from a server (not shown).

Before beginning the next cycle of operation of the server in the register 1 is written to the ID numbers of the test tasks which must be presented for knowledge control. For this purpose, the input 33 of the server issues a code number of the test that the synchronization server at the input 35 is in register 1.

In addition, the server sets one of the two working modes: control mode or the mode of self-control, implemented using a trigger 12, controlled with inputs 35 and 36. If the trigger 12 is in the initial (zero) state, then it implements the control mode, in which it blocks the chain issue “tips” through the elements 18, 19 and 24 I. If the trigger 12 will be transferred in one state, it would mean the device is in a mode of self-control. High potential with a single trigger output elements 18, 19 and 24 And will be open to issue prompts on the display screen.

Code test number from the output of the register 1 is transferred to the input 53 of the guide 11 of the reference address of the test, where it is input to the decoder 45 (see figure 2), which decrypts the code, and on one of its outputs is formed a high potential, opening one of the corresponding items 48-50 I.

In parallel, the clock signal server input 35 is delayed by element 51 delay (response time decoder 45 and setup code address inputs a persistent storage device 46) and the output element 51 delay, having an open second input of one of the elements 48 and 50 And is fed to the input of the read fixed memory permanent storage device 46.

In the fixed cell of the memory block is stored a code message, whose structure is presented in figure 3, where the first K1-bits is stored start address of the first test, and secondly K2-bits is stored the total number of jobs in this test.

The contents of the fixed cells of the ROM 46 is read at the input of the register 47, where it is recorded synchronizing pulse received from the output of the delay element 52 to the clock input of the register 47. The contents of the first K1-bits from the output register 47 through the output 54 of the guide 11 is supplied to one input of the adder 8, and the contents of the second K2 bits to one input of the comparator 5.

The clock pulse from the output of the delay element 52 after entering code in the register 47 through the output 55 of the determinant 11 passes through the element 25 OR the input element 28 delay, where is delayed by the time delay of the register 47 and setup code at the input of the adder 8. Given that at this point, the counter 6, the output of which is connected to another input of the adder 8 is in the original “zero” state, one input of the adder will be the contents of the K1-bits, and the second input code corresponding to the zero value.

Synchronizing pulse received at the clock input of the adder 8 from the output of the delay element 28, the output of the adder 8 is fixed initial address of the first test, which must be issued on the display screen. The same pulse delayed by the delay element 29 at the time of transient processes in the adder 8, is fed to the input of the read unit 10 to the memory and reads the contents of the start address of the output unit 10.

The structure of the read coded messages presented in figure 4, where the first K3-bits allotted for the test task, and the second K4-bits contain the code of the correct answer.

After reading the first K3-discharge in the form of tests are given on the display screen through the output device 39, and the latter K4-bits, containing the code of the correct answer, go to the information input of the register 2, where and are recorded synchronizing pulse from the output of delay element 30 (check received at its input pulse to the time code read from the memory block and install it to the input register 2).

According to the classical theory of testing [4] on the optimal number (4-6) of the answer choices must be only one correct answer and this answer will be in register 2.

The learner of the proposed answers chooses the one that he prefers, and types on the keyboard corresponding character or symbol. Response code is supplied to the information input 34 case 3, where and recorded clock pulse input 36.

Simultaneously, the same clock pulse input 36 is delayed by the delay element 31 on the recording time code in register 3 and then supplied to the clock input of the comparator 4, the information inputs which are served codes registers 2 and 3. If the codes registers match, the direct output of the comparator 4 is a high potential, which will be open element 14 And the other input of which receives the clock pulse from the output of the delay element 32, arrested on the response time of the comparator.

The pulse from the output element 32 of the delay element 14 passes And then goes, firstly, to the input element 18 And open at the second input of the trigger 12 in the mode of self-control. As a result, the signal output device 42, a signal will appear “True”.

Secondly, the pulse from the output of element 14 And through the element 27 OR receives on one input element 16 And whose state is determined by the potential with the inverted output of the comparator 5. Given the fact that one input of the comparator is the code, fixing the number of tasks in the test, and the other code counter 6 at the moment corresponding to the zero value, to direct the output of the comparator 5 is low potential and the inverted - high supporting element 16 And in the open state.

As a result, the pulse from the output element 27 OR passes through the element 16 And then goes on counting input of the counter 6, increasing his testimony on the unit and through the element 25 OR element 28 delay to the sync input of the adder 8, fixing the fact of increasing code the address inputs of the memory block unit.

Next is read in the manner described above the following tests and corresponding code of the correct answer in the register 2.

If in the process of choice for the next test assignment in the register 3 is incorrect response, this fact will be recorded by the comparator 4, the issuance of a high potential at its inverted output. As a result, the element 14 will be closed, and the element 15 And is open. The pulse from the output element 32 delay will pass through the element 15 And will, firstly, on a single input trigger 13, the locking fact errors and an opening on one input elements 24 I. the return of the trigger 13 to its original state is performed by the signal initial setup of the remote control device (not shown) before dialing the correct answer.

Secondly, it will pass through the element 19 And outdoor high potential trigger 12 in the mode of self-control, exit 43 in the signal quality Error. Given that the mode of self-control trigger 12 opens and the elements 24 And the second input, the output of the register 2, the code of the correct answer through the elements 20 And will be issued on the display screen in the form of information “ the Right answer”.

Thirdly, the pulse from the output element 15 And is supplied to the counting input of the counter 7, count the number of errors. The counter 7 is fed to the input of the decoder 9, which, depending on the counter opens one of the elements 21-23 I. the Outputs of the respective elements 21-23 And set in accordance with a possible assessment of knowledge, which are issued to the outputs 40.

Fourth, this same pulse is supplied to one input element 20 And whose state is determined by the potential with the inverted output of the trigger 12. If at the moment the trigger 12 is in the mode of self-control, low potential with the inverted output of the trigger 12, the element 20 will be closed and the cycle continued the presentation of the next test assignment is possible only after re-entering the now prompted correct response in the register 3.

In this case, the comparator 4 will record the fact of comparing codes of registers 2 and 3 and high potential will open element 14 And through which the clock pulse from the output element 32 delay passes through element 27 OR the element 16 And as to the counting input of the counter 6, and through the element 25 OR delay element 28 to the clock input of the adder 8. Next is read in the manner described above the following tests and corresponding code of the correct answer in the register 2.

If the trigger 12 were in the initial state, which corresponds to the mode of the device in a control mode, a high potential with inverted output will be open element 20 And the pulse from the output element 15 And passes through the element 20 And the element 27 OR the element 16 And further to the counting input of the counter 6 and through the element 25 OR element 28 delay to the sync input of the adder 8.

The described process will continue until such time as the comparator commits equality codes in register 47 of the guide 11 and the counter 6. As soon as the comparator 5 will record the equality codes of the counter 6 and the register 47, to direct the output of the comparator will appear high potential, which one input is opened, the element 17 And on the other input of which receives the clock pulse from the output of the delay element 30. The clock pulse passes the element 17 And and comes first, as to the output 44 as a signal to the server about the end of the presentation of tests and installation inputs of the counter 6 and the adder 8, returning to their original state.

Secondly, this same pulse is fed to the inputs of the elements 21 and 23 And passes to the output from them which will open the corresponding output of the decoder 9, which determines the type of assessment, which earned it the test the learner on the results.

Third, this same pulse is supplied on the installation of the meter inlet 7 and through the element 26 OR on the installation log trigger 12, setting it in its original state, which corresponds to the control mode of knowledge.

Thus, the introduction of new nodes and constructive relations will significantly improve the accuracy of assessing the students ' knowledge in all areas of the studied subject areas.

Sources of information

1. Published Japan's bid No. 60-19540, CL G 06 F 15/16, 1985.

2. The description of the author's certificate No. 1550528, CL G 06 F 15/20, 15/40, 1990 (prototype).

3. Romanov A.N. and other distance learning technologies in distance education in Economics. - M.: UNITY-DANA, 2000.

4. Kline P. reference guide for designing tests. Kiev: PAN-LTD, 1994.

Device to control the receipt of assessing the quality of knowledge in distance learning system, containing the first register, the information input of which is the first information input device, and the clock input of the first synchronizing input of the second register, an information input connected to the output of the memory block, which is the first information output device, the third register, the information input of which is the second information input of the clock input is the second clock input devices, and output connected to one input of the first comparator, another input connected to the output of the second register, and outputs connected to one inputs of the first and second elements And accordingly, the second comparator, one input of which is connected to the output of the first counter and outputs connected to one input of the third and fourth elements, And accordingly, the first element OR, one input of which is connected to the output of the third element, And the output of the first element OR is connected to the input of the first delay element, the output of which is connected to the input of the second delay element, the output of which is connected to the input of the read memory block and the input of the third delay element, the pulse from the third element And is supplied to the counting input of the first counter, the clock pulse from the fourth element And is supplied to an installation log the first counter, the first trigger, a single entry which is the first Manager of the input device, the second element OR, one input of which is the second managing input devices,

and the output connected to the set input of the first flip-flop, the fourth delay element, the input of which is connected to the second clock input devices, and output connected to the clock input of the first comparator, while the clock pulse, delayed by the fourth delay element for recording time code in the third case comes from the output of the fifth delay element to the first and second elements And a second trigger unit whose input is connected to the output of the second element And connected to the counting input of the second counter, the first group of items, one input of which is connected to the output of the fourth element And the second element group, And some inputs are connected to the outputs of the second register, the third element OR, one input of which is connected to the output of the first element And the fifth and sixth elements, one input of which is connected with a unit output of the first trigger, the seventh element And one input connected to an inverted output of the first trigger clock pulse from the fourth element And is supplied to the clock output as a signal about the end of the presentation of tests, with an output of the third delay elements receives the clock pulse to the input of the fourth element And the input of the second register, the first signal output a signal “That's right” from the fifth element And code the correct answer from the second group of elements And is issued on the display screen, with the sixth element And receives a pulse on the second signal output device in signal quality Error,

the clock pulse from the fourth element And is supplied on the installation input of the second counter and the second element OR, characterized in that it contains the identifier of the reference address of the test, an information input connected to the output of the first register, a clock input connected to the first clock input the device information output connected to another input of the second comparator, and a clock output connected to another input of the first element OR adder, one data input of which is connected to the information output of the determinant of the reference address of the test, another information input is connected to the output of the first counter, the clock input connected to the output of the first delay elements, installation the input is connected to the output of the fourth element, And the output of the adder is connected to the address output of the memory block, the decoder, the input connected to the output of the second counter, and outputs connected to the other input elements And the first group, while the other input of the fifth element And is connected to the output of the first element And the other input of the sixth element And is connected to the output of the second element And the other input elements And the second group are connected to individual outputs of the first and second triggers, the other input of the seventh element And is connected to the output of the second element, And the output of the seventh element And connected with the other the entrance to the third element OR the output of which is connected to another input of the third element And output element And the first group signal is given a “score” on the second information output device.,