Apparatus for quantitative estimation of quality indicator

FIELD: physics.

SUBSTANCE: apparatus for quantitative estimation of a quality indicator comprises an array of m*n first 1_ij and second registers 6_ij (i=1, …, m, j=1, …, n), n third registers 2_j (j=1, …, n), n first multiplier units 5_j, n second multiplier units 9_j (j=1, …, n), first 10, second 11 and third 12 adders, fourth 15 and fifth 16 register, a clock-pulse generator 17, a third multiplier unit 14, a divider unit 13, first 22, second 23, third 24 and fourth 25 delay elements, first and second array of m*n first 3_ij and second 7_ij AND elements (i=1, …, m, j=1, …, n), n first 4_j and n second 8_j OR elements (j=1, …, n), a third AND element 18, a counter 19, a comparator circuit 20, a decoder 21.

EFFECT: high reliability of the device owing to considerable reduction of hardware costs.

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The invention relates to computing and can be used to quantify the qualitative index that consists of individual components (factors)in different areas of science, technology and public life.

The technical result is to increase the reliability of the device due to a significant reduction in hardware costs.

This is achieved in that the device comprises a group of input registers, input registers, groups, blocks the multiplication group of the cumulative adders, groups of blocks dividing the cumulative adders, units of the division, the adder, a shift register, an output register, a display unit, a generator of clock pulses and the pulse distributor [1].

Determination of quantitative values of quality will help to get an objective assessment of the issues of science, technology and Economics. Such determination can be carried out as follows.

The quantitative importance of the influence of each component (factor) quality of d_ijis determined by an expert. Is defined as the maximum value of one of the components (factor) per unit, as numeric values in each case (for orientation to the expert) are encouraged to use the verbal - numerical scale Harrington [2].

Verbal - numerical scale is Arrington

Quantitative assessment of the value of quality indicator seems to be considering the expert's competence. While a quantitative assessment of the quality index factor (fraction) d_ijspecified as a range of values of the scale Harrington (minimum-maximum).

The expertise of each expert is established a priori (before the survey). Expert evaluations are independent random variables, which can be folded into account the correction factors B_j.

Average rating Pd_iall experts on the i-th factor is determined by the formula

Pd_i=(∑Pd_ij*B_j)/n i=1, ..., m; j=1, ..., n,

where P_dji- evaluation of the j-th expert's probability of influence of the i-th factor (fraction) quality;

B_j- coefficient taking into account the qualification (competence) of the j-th expert.

Average rating PD₀all factors will be equal to

Pd₀=(∑Pd_i)/m, i=1, ..., m.

You must determine the maximum and minimum points, and then find the average of.

The maximum average score$$P{d}_0^{\max }$$all factors calculated by the following formula:

$$P{d}_0^{\max }=\left(\sum \sum P{d}_{ij}^{\max }*Bj\right)/\left(m*n\right)\left(\text{1}\right)$$

where$$P{d}_{ij}^{\max }$$- the maximum score for the j-th expert's probability of influence of the i-th factor (fraction) quality.

Minimum average score$$P{d}_{}^{}$$i j min all experts on all the factors is determined by the following formula:

$$P{d}_0^{\min }=\left(\sum \sum P{d}_{ij}^{\min }*Bj\right)/\left(m*n\right)\left(\text{2}\right)$$

where$$P{d}_{ij}^{\min }$$- the minimum score of the j-th expert's probability of influence of the i-th factor (fraction) quality.

Final score Pd₀the value of the quality indicator is determined as an average value of$$P{d}_0^{\max }$$and$$P{d}_{ij}^{\min }$$:

$$P{d}_0=(P{d}_0^{\max }+P{d}_{ij}^{\min })/2\left(\text{3}\right)$$

The technical result is achieved in that the device for the quantitative evaluation of the quality indicator includes first and second groups of input registers, each of which consists of k×n elements, the third group of input registers, consisting of n elements, the first and second input registers, the first and second groups of multiplier units, each of which consists of k×n elements, the first and second groups of the cumulative adders, each of which consists of n elements, the first and second groups of blocks dividing, each of which consists of n elements, the first and second cumulative adders, the first and second units of the division, the adder, a shift register, an output register, a display unit, a generator of clock pulses and the pulse distributor (RI), a clock input connected to the output of the generator of clock pulses, a first output RI - I write the first, second and third groups of input registers, the first and second input registers, the second output from the reading of the first, second and third groups of input registers, the third and fourth outputs - inputs are read, respectively, the first and second input case is, the fifth and sixth outputs - inputs respectively write and read the output register, the information inputs of the first and second groups of input registers are used as inputs to set the source of the information on the received values, respectively$$P{d}_{ij}^{\max }$$and$$P{d}_{ij}^{\min }$$characterizing respectively the maximum and minimum estimates of the j-th expert on the i-th factor (fraction), the information inputs of the third group of input registers are set reference input source information, which enter the value of b_jcharacterizing factors of qualification (competence) of the j-th expert, informational inputs of the first and second input registers are used as inputs to set the source of information, which are received, respectively, the value of k, which characterizes the number of experts, and the value of n, which characterizes the number of factors (interest) as a quality indicator, the outputs of the first and second groups of input registers connected to the first inputs of the respective elements, respectively, the first and second groups of multiplier units, each second column which, from first to k-th, clucene to the outputs of the respective elements, from the first to the k-th, the third group of input registers, the outputs of each row, the first through n-th, first and second groups of blocks of the multiplication connected with the first through k-th inputs of the first through n-th elements of, respectively, the first and second groups of the cumulative adders, the outputs of each of which are connected to the inputs of the dividend corresponding elements, respectively, the first and second groups of blocks dividing the inputs of the divider which is connected to the output of the first input register, and outputs first to n-th inputs respectively of the first and second cumulative adders, outputs are connected to the inputs dividend, respectively, the first and second units of the division, the inputs of the divider which is connected to the output of the second input register, and the outputs respectively from the first and second inputs of the adder, the output of which through the shift register is connected to the information input of the output register, the output of which is connected to the input of the display unit.

Device for the quantitative assessment of qualitative indicators (see figure 1) contains a group of m∗n registers 1_ij(i=1, ..., m, j=1, ..., n), the group of n registers 2_j(j=1, ..., n), the group of items 3_ij(i=1, ..., m, j=1, ..., n), the group of n elements, OR 4_j(j=1, ..., n), the group of n blocks of multiplication 5_j(j=1, ..., n), the group of m∗n registers 6_ij(i=1, ..., m, j=1, ..., n), the group of items 7_ij(i=1, ..., m, j1, ..., n), the group of n elements, OR 8_j(j=1, ..., n), the group of n blocks of multiplication 9_j(j=1, ..., n), the adders 10, 11 and 12, unit 13, block multiplication 14, registers 15 and 16, the generator of clock pulses (GTI) 17, the And gate 18, the counter 19, the comparison circuit 20, a decoder 21, the delay elements 22, 23, 24 and 25, the outputs 26 and 27, the input device 28.

In the initial state, all the adders 10, 11 and 12 are in the zero state, the register 15, the recorded code number m (the number of factors)on the register on 16 recorded code number n (number of experts). The registers 1_ijstored value codes$$P_{ij}^{\max }$$on the registers 6_ijstored value codes$$P_{ij}^{\min }$$on the registers 2_jstored value codes b_j(i=1, ..., m, j=1, ..., n) (Installation inputs on the drawing because of its bulkiness not shown). As a result, the output of block multiplication 14 will be the code value (2∗m∗n) - this can be implemented in a known block multiplication by removing the result from the output unit 14 is shifted by one digit in the direction of the senior ranks.

Device for the quantitative assessment qualitative indicator operates as follows (see Fig.1). Input 28 in which trojstva receives the start signal, served on the control input element And 18, after which the counting pulses from the output of the generator 17 through the open item And 18 arrive at the counting input of counter 19. The contents of the counter 19 is then fed to the input of the comparison circuit 20 and the input of the decoder 21.

The output of the decoder 21 individual signal appears on only one of the i-th (i=1, ..., m) of its outputs, the corresponding code on the meter 19, and (m+1)-th output of the decoder 21 after changing the code on the meter 19 for subsequent synchronization operation block device.

With the arrival of the next i-th pulse to the input of counter 19 to the i-th (i=1, ..., m) the output of the decoder 21 receive a single signal which is fed to the control inputs of elements And 3_ij7_ij(i=1, ..., m, j=1, ..., n), the second input of which receives the values of$$P_{ij}^{\max }$$from the output of the register 1_ijand$$P_{dij}^{\min }$$from the output of the register 6_ijrespectively. From the outputs of the element And 3_ijand element And 7_ijcodes go through the elements OR 4_j(j=1, ..., n) and the elements OR 8_jthe first inputs of multiplier units 5_jand 9_jrespectively. On the second inputs of blocks multiplied by the I 5 _jand 9_jenters code correction factor b_jfrom the output of the register 2_jand on the third inputs - isolated signal with (m+1)-th output of the decoder 21. The outputs of multiplier units 5_jand 9_jconnected to the same inputs of the adders 10 and 11, respectively. On the control input of the adders 10 and 11 receives the signal from the output of the delay element 22, which delays the input signal with (m+1)-th output at time reliable operation of the unit elements And 3_ij, item, OR 4_jand block multiplication 5_j.

Upon reaching the counter 19 m at the output of the comparison circuit 20, you receive a single signal which resets the counter 19 in the zero state and the second output of the comparison circuit 20, you receive a zero signal which is fed to the third input element And 18, thereby stops the flow of pulses from the output of the generator 17 through a private member And 18 at the counting input of counter 19.

In addition, the signal from the m-th output of the decoder 21 to the input of the delay element 23, which delays the signal on time reliable actuation elements 3, 4, 5, and adders 10 and 11. The output signal from the delay element 23 is fed to the input of delay element 24 and to the control input of the adder 12, the information input of which receives codes from the outputs of the adders 10 and 11. Code from the output of the adder 12 is supplied as Delhi is left on the first input unit 13, divider to the second input unit 13 is supplied from the output of block multiplication 14, and the control input receives the delayed signal to the reliable operation of the adder 12 from the output of the delay element 24.

The output of delay element 24 is connected to the input of the delay element 25, which delays the input signal for reliable operation of unit 13, then at the output of the delay element 25 appears to signal the end of the operation of the device 27.

The result of the operation of the device code is output 26 of the block 13 after the signal termination device 27.

Thus, the technical result of the claimed invention is achieved by technical means (blocks and items) together with the constraints mentioned in the description of the operation of the device. The described device makes it possible to eliminate bias in solving a range of complex issues of science, technology and Economics.

Industrial applicability of the invention is that it can be used in different areas (sectors) production in quantifying qualitative index that consists of individual components (factors).

Sources used

1. Patent No. 2448364, CL G06F 17/00, 2012.

2. Troyanovsky V.M. Mathematical modelling in management. -M.: Russian business books, 1996.

The mouth of austo to quantify qualitative indicator, containing a matrix of m∗n first 1_ijand second registers 6_ij(i=1, ..., m, j=1, ..., n), n third registers 2_j(j=1, ..., n), n first multiplier units 5_jn second multiplier units 9_j(j=1, ..., n), the first adder 10, the second adder 11, the third adder 12, the fourth register 15, the fifth register 16, a generator of clock pulses (GTI) 17, the third block multiplication 14, unit 13, an output of the third register 2_j(j=1, ..., n) is connected to the first input of the first block multiplication 5_jand to the first input of the second unit 9 multiplication_jwhose output is connected to the same input of the adder 11, the output of the first block multiplication 5_jconnected to the same input of the adder 10, characterized in that it also includes the first delay element 22, the second delay element 23, the third delay element 24 and the fourth delay element 25, the first and second matrix of m∗n the first 3_ijand second elements And 7_ij(i=1, ..., m, j=1, ..., n), n first elements OR 4_j(j=1, ..., n), n second elements OR 8_j(j=1, ..., n), the third element And 18, the counter 19, the comparison circuit 20, a decoder 21, the output of the GTI 17 is connected to the first input of the third element And 18, the second input is connected to the first output of the comparison circuit 20, the second output of which is connected to the first input of the counter 19, the second input is connected to the output of trateg the item And 18, and the output to the first input of the comparison circuit 20 and to the input of the decoder 21, the i-th (i=1, ..., m) the output of which is connected to the first inputs of the i-th (i=1, ..., m) are the first elements And 3_ijand to the first inputs of the second elements And 7_ij(i=1, ..., m, j=1, ..., n), the output of the fourth register 15 is connected to the second input of the comparison circuit 20 and to the first input of the third block multiplication 14, the output of the first register 1_ij(i=1, ..., m, j=1, ..., n) is connected to the second input of the first element And 3_ijthe output of the first element And 3_ij(i=1, ..., m) are connected to the same input element OR 4_j(j=1, ..., n), the output of which is connected to the second input of the first block multiplication 5_j(j=1, ..., n), the third input of which is connected to the (m+1)-th output of the decoder 21, the output of the second register 6_ij(i=1, ..., m, j=1, ..., n) is connected to the second input of the second element And 7_ij(i=1, ..., m), the output of which is connected to the same input element OR 8_j(j=1, ..., n), the output of which is connected to the second input of the second unit 9 multiplication_j(j=1, ..., n), the third input of which is connected to the (m+1)-th output of the decoder 21, the control input of the adder 11 is connected through a delay element 22 to the (m+1)-th output of the decoder 21, and the output to the first input of the adder 12, the control input of which is connected through a delay element 23 to m-th output of the decoder 21, the control input of the adder 10 podshoev the EN through the delay element 22 to the (m+1)-th output of the decoder 21, and the output to the second input of the adder 12, the output of which is connected to the first input unit 13, the control input of which is connected through a delay element 24 to the output of the delay element 23 and the second input to the output of the third block multiplication 14, the second input is connected to the output of the fifth register 16, the input of the delay element 25 is connected to the output of the delay element 24, and the output of the delay element 25 is output 27 of the finished device.