Control computer system. RU patent 2520350.

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used to design computing devices (computers) which are part of mobile object control systems. The control computer system comprises a processor with a storage device connected to said processor, and a clock pulse former whose outputs are connected to the processor and the storage device. The processor is connected to the clock pulse former by a control output. The system comprises a blocking signal former, an interval former and an external factor sensor whose output is connected to the input of the interval former and to the first input of the blocking signal former, connected by the first output to the blocking input of the storage device, by the second input to the control output of the processor and by the third input to the interval former, the zero setting outputs and timestamps of which are respectively connected to the processor and the storage device, and phasing outputs are connected to the clock pulse former.

EFFECT: faster operation at each time interval and restoring operating capacity of a system when external action ceases.

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The invention relates to the computer engineering and may be used for creation of control systems of moving objects, such as robotic systems or products of rocket and space technology, working under adverse external influences, including the powerful electromagnetic influences. These impacts can be caused by discharges of atmospheric electricity or pulsed ionizing radiation of space, caused by solar flares or technogenic accidents at nuclear power plants or nuclear industry. In the result of external influences during the pulse action disrupted the computer means, after which the evaluators are able to function properly if to repair the computing process through the use of a prepared in memory of calculation results of previous cycles recovery and real-time. However, ionizing effects due to radiation violations can change the speed, which also leads to the disruption, which in the absence of catastrophic failures can be selected in compliance with the current performance of the components, selecting the necessary performance test results of inspections, which requires you to provide reorganization of frequency oscillator, pulsing shaper clock.

The famous three-channel computer system (See, for example, the AU №1156273 containing in each channel external device and computer, information, the output of which is connected to the first input of the first majoritarian element and to the first input of the first element of comparison of all channels. The second entrance of the first element of comparison is connected to the output of the first majoritarian element and with the input of an external device, the output of which is connected to the first information input of the second majoritarian element of all channels, second and third information input of which is connected respectively with the second and third informational inputs second majoritarian elements of other channels and outputs external devices, respectively. The output of the second majority element connected to the first input of the second element of comparison and to the first input of a computing device. The second input of the second element of comparison connected to the first input of the second majority element, and the output - output relationships. Each channel contains also register a channel number, four blocks of the analysis, the group of controls And the control register and the element OR, the output of which is connected to the input interrupt computing device. The first input of the control register connected to the output of the serial communication computing device. The inputs of the control register is connected to the outputs of the group of elements I. the Second outputs are connected to the inputs of the element, OR. In addition, each channel contains an element NOT, and each block of analysis made in the form decoder associated with the inputs to the outputs of the elements of comparison.

It is a known device, thanks to the installation of majority elements in the output information tires calculators provides the neutralization of malfunction, resulting in one of the channels for proper operation of the other two channels. In addition, thanks to the introduction of schemes comparison connected to the external relations of the devices can detect malfunction of one of them for distinguishing him from the other two, which allows diagnosing failures external devices by state analysis of the control register computing device. These properties are quite positive. Especially important is the neutralization of a malfunction in one of the channels computing device. At the same time after the occurrence of a fault in one of the channels reliability of the further work of the system dramatically reduced, as the occurrence of a fault in any of the two remaining healthy computing devices leads to a complete failure of the system. This is because the intensity of failure in two channels twice more than in single-channel transmitter. It is advisable to maximize the use of existing redundancy in the form of two additional entered channels calculators to keep the system working after the second occurrence of a malfunction. The task of preserving the health of the system in the event of two faults in the system partially solved in a redundant computing device. AU №1200292). This device to improve the reliability between memory and processors introduced switch, switching units on signals embedded devices operational control.

A common disadvantage of computing devices is that for work schemes coincidence logic, and for work on the switch, the switch units in the process of work, requires synchronous and common mode, all channels of the device, which is provided by the introduction of a single generator of pulses. With the backup failure of the generator leads to failure in General, in addition, a temporary mismatch same signals of different channels redundant device requires performance to take into account interchannel mismatches caused some differences delays elements of different channels. Moreover, in the process of work in blocks computing device under the influence of temperature and especially due to the impact of external ionizing radiation, for example, the space degradation parameters of components to consider when planning is impossible. In addition, under the action of external factors, such as high-power pulsed electromagnetic or ionizing radiation, occurs a temporary denial of all blocks and modules of the system. In the result, despite the absence of catastrophic failures stops solution of functional tasks, which leads to a control system failure, and even loss of control object. This is especially true for mobile objects. To address the noted deficiencies in critical of the failure of a single generator of pulses maximize performance on each interval of time, and restore system functionality after the end of external actions proposed by the Managing computing system.

The disclosure of the invention

The managing computing system includes (see figure 1) processor identified by the number 1, attached bidirectional links storage device (storage)is identified by the number 2, the driver signals lock (FSB), see number 3, shaper clock (VIF), indicated by figure 4, the forming device intervals (UFI), see number 5, and the sensor of the external factor (DWF), see number 6. The controller inputs synchronization and interrupt connected respectively to the VIF and UFI, whose output timestamp connected to the input of memory and environment outputs are connected to the same input VIF connected clock outputs to the memory and processor, the first managing the output of which is connected to the same input VIF, and the second control output is connected to the control input of UFI. The UFI and FSB triggering inputs and connected to the output of the DWF. Outputs VIF connected to a sync inputs to the processor and memory, blocking the input of which is connected to the outputs of the FSB.

Figure 2 and 3 shows the composition ZU respectively with two and three drives. Figures 21, 22, 31, 32 and 33 designated non-volatile storage. Each memory drives are connected to the data bus, and blocking the inputs connected to the bus lock, an entrance-access memory. Figures 23-1, 23-2, 34-1, 34-2 and 34-3 marked adders time marks and numbers 24-1, 24-2, 35-1, 35-2 and 35-3 marked adders arrays. Inputs adders labels are used as inputs ZU connected to the unions, and their outputs are connected to the inputs of the drives. Adders arrays connected bilateral ties to data bus ZU on the one hand and to the drives.

Figure 4 shows the structure of the former master, which contains 3 identical channels, in which the numbers 41-1, 41-2 41-3 and marked accordingly, the first, second and third setpoint generators connected outputs to their units phasing first 42-1, second 42-2 and third 42-3, outputs, which are the outputs of the driver and the VIF. While the first and the second installation inputs generators and environment entrances of the blocks are phasing same inputs shaper.

Figure 5 shows the composition of the UFI, which contains three stable quartz oscillator pulse: the first 51-1, second 51-2 and third 51-3, the outputs are connected to the first frequency dividers: first 52-1, second 52-2 and third 52-3, environment outputs which are the outputs of UFI, and the interval outputs are connected to the inputs of a majority item 54, the output of which is the output of the device. In addition, the output of each of the generators connected to the input of your driver timestamp, respectively the first 53-1, second 53-2 and third 53-3, outputs, which are the outputs of TIDs.

Figure 6 shows the composition of the shaper blocking signal, which contains a register 61 is connected output to the decoder 62, the output of which is connected to the input trigger 63, connected with the exit to the first input element And, second input of which is the input of the driver that is connected to the sensor external influences, and the output of an element is the output of the driver.

Figure 7 shows the block circuit phasing that contains the logical element 71, the first sign of which is the entrance of the block is connected to the pulse generator, and the output is connected to the shift register 72, the outputs of which are connected to the inputs of shear decoder 74, the output of which is connected to the trigger input trigger stop 73, the output of which is environment-unit output and is connected to the second entrance gate and the first sign of a majority item 78, second and third input of which is connected outputs triggers binding 77, clock entrance merged with the first input element And, as the first and second inputs are environment the unit. Output majority element is connected to the input trigger start 76, the output of which is connected to the reset input trigger stop, and the outputs of the odd and even bits of the shift register are respectively trigger and reset inputs triggers shapers 75-1-75-n, outputs, which are the outputs of the unit.

On Fig the scheme of the generator of pulses, which contains n series-connected inverters 81, the outputs are connected to the multiplexer 82, the output is connected to the input of the first inverter, forming a ring generator, and the input buffer 83 and the frequency counter 84, output buffer 83 is the output of the generator. Outputs counter code frequency is connected to the first input schema comparison 86, connected first and second outputs respectively to increment and decrement the counter inputs code frequency whose outputs are connected to the control inputs of the multiplexer. At that the second input of the differential amplifier connected exit code register frequency, which input and frequency register are respectively the first and second inputs master oscillator.

Figure 9 shows a diagram of the drive, where the figure 91 marked actually non-volatile storage element, which can be implemented on the basis mnogoatomnykh ferrite plates or thin cylindrical magnetic films and modern integral elements of type FRAM or MRAM, figure 92 marked NC key (MOS transistors with built-in channel)connected drain and source parallel to write buses storage element, bi-directional tires are tires drive and the shutter key is blocking the entrance of the drive.

Thus, the restoration of the result array, using data from a locked memory areas and formed interval real-time ensures the recovery of the computing process, caused by a temporary malfunction during the duration of the pulse, and the dose of changes in performance are taken into account by setting the proper values clock frequency oscillator.

The system works as follows.

In the initial state register 61 FSB written code permitting recourse to the law of Ukraine on the part of the processor, which writes the resulting arrays each cycle calculations turn in different drives, so that at every moment of one of the drives remains blocked. Upon receipt of another word in the record from a fixed address is called a checksum, which is adjusted in the accumulator with the value of the recorded words and re-written to a fixed address. The current real time is also stored in a separate address and incremented by his adder at admission time stamps. At occurrence of external influence the sensor activates a signal which causes the formation of UFI signal lock drives, and alarm reset of the processor. After removing the blocking signal and reset the processor comes out to the recovery program, in which he writes to the register 61 FSB allows the reference to the law of Ukraine determines reliable array by using the checksum or for torowang drives selects a work array by comparing the data or checksums on the principle of "2 of 3", adds to the current time fixed value equal to the duration of the signal zero and goes on routine management tasks, working with alternately blocked areas memory drives up the next exposure.

1. Controlling computing the system that contains the processor with attached mass storage device driver clock whose outputs are connected to the processor and storage device, wherein the control output processor connected to the driver of the clock, and also introduction of signal shaper locking, conditioning instrument intervals and sensor of the external factor, the output of which is connected to the inlet of the instrument intervals and to the first input shaper blocking signal that is connected first exit for blocking the entrance of the storage device, second entrance to the managing the exit of the processor, and the third sign is the instrument of the intervals at which the outputs are reset and time stamps attached respectively to the processor and storage device, environment and outputs to the driver sync.

4. The system of claim 1, characterized in that the former clock contains three blocks phasing and three pulse generator, in which the first and second installation inputs are the same inputs shaper and the output of each generator is connected to the entrance of his block phasing environment entrance of each of which is connected to the environment inputs two other blocks, and synchronization outputs of the block are the same outputs of the driver.

5. The system of claim 1, wherein the driver intervals contains three oscillator, three frequency divider, three former labels and majoritarian element whose output is the output, and the output of each generator is connected to the inputs of the shapers of labels and frequency dividers your channel, interval outputs are connected to the inputs of the majority of the element and their environment outputs and outputs shapers labels are the outputs of the device.

6. The system of claim 1, wherein the driver blocking signal contains case, the output of which is connected to the input of the decoder, the output of which is connected to the first input trigger, the second input of which is the input of the shaper and the output is connected to the first input element And, second input of which is the entrance of the shaper and the output - output driver.

7. The system in claim 4, wherein the driver timestamp contains logical element, the first sign of which is the input of the shaper and the output is connected to the input shift register, the output of which is connected to the input shear decoder connected output to the trigger input trigger shutdown, the output of which is environment-shaper's output and is connected to the second entrance gate and the first sign of a majority of the item, the output of which is connected to the input trigger start, connected with access to the reset input trigger the shutdown, and to the second and third entrance majority element connected outputs triggers binding inputs which are environment-unit, and their word clock input combined with the first entrance gate, with outputs odd and even the shift register is connected respectively to the trigger and reset inputs trigger-shapers, outputs, which are the outputs of the unit.

8. The system of claim 2, characterized in that the drive contains a non-volatile memory element inputs and outputs are the same inputs-outputs drive, and in parallel to its tyres account connected MOS transistors with built-in channel entrance gate which is blocking the entrance of the drive.

9. The system in claim 4, wherein the pulse generator contains n-series inverters connected outputs to the inputs of the multiplexer, the output of which is connected to the input of the first inverter buffer element, the output of which is the output of the generator, and the input of the counter code frequency, the outputs of which are the first input schema comparison, the first and second outputs which connected respectively to increment and decrement the counter inputs code frequency whose outputs are connected to the control inputs of the multiplexer and counter inputs and inputs code register frequency and are the first and the second input of the generator.