RussianPatents.com
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Tracking and synchronising partial change in elements. RU patent 2421780. |
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FIELD: information technology. SUBSTANCE: changes in elements are tracked in accordance with a defined group of properties, and each group is tracked independent of the other. For example, one group may contain large data elements, for example inputs, while the other group may include highly changeable properties, such as an execution control flag feature. Rate of synchronisation between a client and a server is increased by synchronising only selected parts of the element which have changed without controlling change in each separate property within the element. Accordingly, if change has been made with respect to a small information property (for example, an execution control flag feature) in a relatively large email message, such a change will not initiate a large load on the client working in cache mode, and will also not require considerable storage space and processing in order to track each separate property. EFFECT: high rate of synchronisation between a client and a server. 20 cl, 6 dwg
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![]() Situations A≥B and A<B or A>B and A≤B or A=B and A≠B, where A=an-1…a0, B=bn-i…b0 - n -bit binary numbers given by binary signals a0,…, an-1 b0…, bn-1∈{0,1}, are detected and the relationship between bitness of the compared binary numbers and the maximum signal propagation delay time is excluded. The device has n groups of switches, each consisting of 6 switches. |
![]() Invention may be used to build means of automatics, functional units of control systems. Device comprises two delay elements, two AND elements, four OR elements, two NOT elements. |
![]() Invention can be used to design automation apparatus and functional parts of control systems. The comparator has 29 transistors grouped into nine groups and 14 resistors. |
![]() Invention relates to computer engineering and can be used as a means of information preprocessing. The device contains 4n inhibit circuits, 2n 2OR elements, 2n opening and 2n closing switches. |
![]() Invention relates to computer engineering and can be used for evaluating and comparing operating efficiency of same-type organisations with the objective of drawing up recommendations for improving quality of their operation. The device contains groups of input and output registers, a group of subtracting units, group of squaring devices, groups of delay elements, groups of adders, square-root extractor, groups of commutators, groups of display units, clock-pulse generator, pulse distributor, input registers and dividers. |
![]() Invention relates to computer engineering and can be used in digital computer engineering systems as an information pre-processing device. The device contains 7n majority elements, each with three inputs, and 2n NOT elements. |
![]() Invention relates to computer engineering and can be used in digital comparators, associative processors and database machines. The technical outcome of the invention is increased functionalities of the device for comparing binary numbers due to recognition of relationships A>B, A=B, A<B, where A and B are four-bit binary numbers. The said device for comparing binary numbers contains eight 2OR elements (11, …, 18), eight 2AND elements (21,…, 28), four NOT elements (31,…,34). There is recognition of relationships A>B, A=B, A<B due to the given elements and a new connection circuit. |
![]() Invention relates to computer engineering and can be used in digital comparators, associative processors and database machines. The technical outcome of the invention is increased functionalities due to recognition of relationships A>B and A=B. The device for comparing binary numbers is meant for comparing four-bit binary numbers A and B, defined by binary signals. The device contains four EXCLUSIVE OR elements (11, …,14), four inhibition elements (21,…,24), four 3AND elements (31,…,34), four 2OR elements (41,…,44) and a NOT element (5). Functionalities of the device are increased due to the given elements and a new connection circuit. |
![]() Invention relates to computer engineering and can be used in digital comparators, associative processors and database machines. The device for comparing binary numbers is meant identifying characters xn-1,…x0 > yn-1,…y0, xn-1,…x0 = yn-1,y0, xn-1,…x0 < yn-1,…y0, where xn-1,…x0, yn-1,…y0 n-bit binary numbers, defined by binary signals x0,…,xn-1, y0,…yn-1∈{0,1}. The device contains 4(n-1)+2 implicators (111, I21, 112,…14n), 2(n-1) conjunctors (212, …,22n). The maximum signal propagation delay time is reduced due to the given logic elements and a new connection circuit. |
![]() Invention relates to computer engineering and can be used in digital computer engineering systems as an information pre-processing device. The said device for selecting the greater of two binary numbers is meant for processing n-bit binary numbers, defined by binary signals. The device comprises 4(n-1) inhibition gates (111, 121, 112,…( 14(n-1), 11n, 12n and 3(n-2)+2 OR elements 212,…,23(n-1), 211, 21n). Compositional uniformity is increased due to the given elements and connections between them. |
![]() Device has coefficients memory elements, comparison blocks, keys, OR elements, indicators. |
![]() Device has numeric conversion block for converting numbers to digit-wise signals, block for forming selection strobes, commutator of selection of minimal or maximal number. |
![]() Device contains two AND elements, two OR elements, two implicative devices. |
![]() Device contains 2(n-1) AND elements, 2(n-1) AND-NOT elements, 2n implicative devices. |
![]() Device for selecting the lesser one of two binary numbers contains AND element, 4(n-1) implication units and 3(n-2)+1 AND elements. Implication units and AND elements are grouped in n groups. Group number J contains two implication units and AND element. Group number M additionally contains two implication units and two AND elements. In group number r the output of i implication unit is connected to i input of first AND element. In m group output of i implication unit, connected by inverting input to first input of (i+1) AND element, and output of (i+1) AND element, connected by second input to of (3-i) implication unit, are connected respectively to inverting and non-inverting inputs of (i+2) implication unit. In first group, inverting and non-inverting inputs of first implication unit are connected respectively to non-inverting and inverting inputs of second implication unit, first and second inputs of first AND element. Output of i implication unit of first group and output of (i+2) implication unit of m group are connected respectively to inverting input of i implication unit of second group to inverting input of i implication unit of (m+1) group. Inputs of first AND element of first group, non-inverting inputs of implication units of r group and output of first AND element of j group form respectively (n+1), r, (n+r) inputs and j output of device for selecting the lesser one of two binary numbers. |
![]() Binary number comparator contains OR logical element, OR-NOT logical element and two XOR logical elements, three AND-NOT logical elements. First input and output of i XOR logical element are connected respectively to first and second inputs of i AND-NOT logical element, connected by second input to i input of OR-NOT logical element. First, second inputs and output of OR logical element are connected respectively to output of second, by second input of first logical element AND-NOT and second input of third logical element AND-NOT, connected by first input and output respectively to output of first logical element AND-NOT and to first output of binary number comparator, second output and i, (i+2) inputs of which are connected respectively to output of logical element OR-NOT and first, second inputs of i XOR logical element. |
![]() In accordance to invention, into comparator of binary numbers, containing two elements "2OR" (2), six elements "2OR" (2ij) are introduced, sixteen elements "forbidden" (1ij), where and element "2OR-NOT" (3), while all elements are grouped in four groups in such a way that j-th group contains two "2OR" (2ij) elements and four "forbidden" elements (1ij), and fourth group additionally contains "2OR-NOT" element (3). |
![]() Device contains two NOT elements, four AND elements and two OR elements. |
![]() In accordance to method, for generating sign of equality of two binary signals x1=x2∈{0,1}, setting compared one-bit numbers, these signals are added by modulus two adder, and addition results are inverted by NOT element, for creating a sign of relation x1 < x2, result of modulus two addition of given signals and binary signal x2 are sent to AND element. |
![]() Device for selecting the greater one of two binary numbers contains OR element, 2(n-2) AND elements, 3(n-1) AND-NOT elements and 2(n-1) implication units. All implication units and AND, AND-NOT, OR elements are grouped in n groups. Groups numbered k and r contain, respectively, two implication units and three AND-NOT elements. First and m groups additionally contain, respectively, OR element and two AND elements. In r group output of i AND-NOT element, connected by second input to first input of i AND element and output of i AND element, connected by its second input to output of (3-i) AND-NOT element, are connected respectively to inverting and non-inverting inputs of i implication unit. In first group inverting and non-inverting inputs of first implication unit are connected respectively to non-inverting and inverting inputs of second implication unit, first and second inputs of OR element. Output of i implication unit of k group is connected to second input of i element AND-NOT of (k+1) group, while first inputs of first and second AND-NOT elements of r group, first and second inputs of OR element and output of third AND-NOT element of r group, output of OR element form, respectively, r, (n+r), (n+1), first inputs and r, first outputs of device for selecting the greater one of two binary numbers. |
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