Device for data exchange between four-phase self-synchronised and synchronised parallel interface |
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IPC classes for russian patent Device for data exchange between four-phase self-synchronised and synchronised parallel interface (RU 2402802):
          
 Device of mobile communication equipped with sensor screen and method of its control / 2402179
Device of mobile communication, comprising sensor screen, and method of its control are proposed. Method includes displaying multiple elements, reception of the first sensor signal, indicating that an element was selected, having a position on screen, reception of the second sensor signal, and scrolling through part of displayed elements that differ from selected element, while selected element remains fixed in its initial position on sensor screen, in response to the second sensor signal.
 Data access and data organisation through diagrams / 2402060
In a method for providing display in form of data diagrams and in a system of individually configured data diagrams, a link for a set of multivariate data on which the initial data diagram should be based is used. Based, at least partially, on this information, a data diagram is generated, which is a graphic presentation of units which correspond to data from this multivariate data set. This data diagram which can be altered by the user is displayed. The used apparatus can provide tools which enable the user to change the order of the units of the data diagram, change the form of the units of the data diagram, change the colour or format of the units of the data diagram, and can also provide functionalities which enable the user to carry out top-down analysis of aspects of the data diagram based on a certain partitioning scheme.
 Complex pixel element, complex touch-sensitive liquid-crystal panel and method of controlling said panel / 2401448
Complex pixel element has a transistor matrix substrate, a colour filter substrate which is parallel to the transistor matrix substrate, and a layer of liquid crystals between said substrates. The transistor matrix substrate includes a first transistor, a first memory capacitor connected to the first transistor, a second transistor, a second memory capacitor connected to the second transistor, and a conducting projection. The conducting projection has a position which corresponds to the position of the first memory capacitor and is made with possibility of electrical connection of the second memory capacitor and the colour filter substrate.
 Method and system for exchange of data between computer systems and auxiliary displays / 2400802
By means of API-calls of programs information is provided in one and the same format, independently on capabilities of device and/or type of connection. Platform of auxiliary display converts information into format that device driver understands, which then filters information, in the manner desirable for its specific hardware device prior to information transfer. Feedback returns data on condition and user communication with reflected information. Software suppliers may therefore write a code once, in order to display information into auxiliary displays, while manufacturers of hardware may instruct their devices to work as auxiliary displays with small changes or without changes relative to existing hardware.
 Upgradable preliminary visualiser of object in browser-shell / 2400801
Browser-shell provides for mechanism of expansion so that detached developers could upgrade functional capabilities of previewing facility specified as default for certain types of files. Graphic user interface includes control facility, which makes it possible for the user to select previewing facility for displayed files from multiple available previewing facilities. Alternatively, browser-shell may automatically select previewing facility from multiple available previewing facility.
 Universal method of entry by means of "x, y" coordinates arrangement / 2400800
Entry of selected letters/symbols displayed on screen is done by pressing of buttons that correspond to coordinates of selected entered letter/symbol location. Multiple letters/symbols and/or functional buttons are combined into multiple versions of letters/symbols for formation of menu comprising columns, for each version of letter/symbol selection there is an x-coordinate identified, combination of which represents horizontal row of figures for all versions of letters/symbols selection. Horizontal row of figures is controlled by means of digital keys for selection of x-coordinate, and value of y-coordinate corresponding to version of letter/symbol selection in horizontal row is established for y-coordinate of specified row of version of letter/symbol selection, at the same time arrow keys are used to select and control y-coordinates, and one row of version of letter/symbol selection is selected simultaneously, besides required selected letter/sign is displayed in menu of coordinates selection, to complete entry of letter.
 Systems and method for training of interactive communication with computer program, having graphic user interface / 2400799
Script is generated so that it includes step-by-step instructions, instructing the user how to complete the task with the help of computer program by means of communication with GUI objects of computer program. Script is formulated by reference to chart of substances containing program instructions for access to GUI objects of program with the purpose of completing task operation. Script is performed by displaying actual non-simulated GUI of program on screen of partial graphic overlay. Each graphic overlay instructs user how to provide suitable user entry of GUI objects of computer program. Partial graphical overlay is installed next to according GUI object of program independently on location of this object, excluding reprogramming of the main computer program.
 Method of determining manipulator coordinates on touch panel / 2399949
Method of determining coordinates on touch panel for entering data into a computer, game consoles, POS terminals and data panels is characterised by that a stream of modulated radiation of electromagnetic waves in the infrared region, which covers the surface of the touch panel, is generated over the surface of the touch panel using at least one radiator. Electromagnetic waves reflected from the manipulator near the surface of the touch panel are received using at least two spatially spaced apart receivers. Phase difference of the modulated signals is measured on radiators (radiator) and receivers. Coordinates of the manipulator on the touch panel are calculated from the ratio of phase difference.
 Mobile terminal / 2399085
Mobile terminal has a housing with a first and second region and a sensor layer which detects contact with the first and second regions. The sensor layer has a part of a touch screen structure which includes multiple conducting lines for detecting contact with the first region and multiple parts of a structure of touch-sensitive buttons arranged such that they have a defined area on the second region. The multiple parts of the structure of touch-sensitive buttons are spaced out from each other and at least one through opening is formed between the part of the structure of touch-sensitive buttons.
 Preview method, system and device / 2398263
According to the method, a preview handler provides an interface for one or more preview tools. The preview tools are software components which enable preview generation for one or more types of documents. In response to a request from the main application program for document preview generation, the preview handler identifies the corresponding preview tool designed for document preview generation. The preview hander may then call the preview tool and order the preview tool to load the document and show a preview in a subwindow provided by the called main application program.
 Information input device / 2246749
Device has keyboard, mounted on a panel, including at least one key, which has at least one operating area, at least one radiation source and one radiation detector, mounted in such a way as to provide possible effect by at least one working tool on route of passing of radiation from emitter to detector and/or on key in appropriate operating area.
 User devices interface / 2247423
Device has base, at least one assembly, consisting of key and means for determination of operation of key, first means for determination of displacement of device elements relatively to one another, while the key is mounted with possible outside access to it, a platform is provided, mounted with possible displacement relatively to base, key is mounted with possible displacement of it together with platform relatively to base, first means for determination of device elements mutual displacement is mounted with possible recording of platform displacement relatively to base, and means for detecting key operation is made or positioned relatively to key in such a way, that it can record well operation in neutral position, and/or in case of platform displacement from neutral position.
 Recording system and method for controlling thereof / 2248032
System, for direct connection of image feed device and recording device through common interface, transferring image data to recording device from image feed device and recording these data, has setting means for setting communication procedure by means of using software applications, mounted in recording device and in image feed device, and for setting of each of multiple functions to either image feed device or recording device, while these functions serve as recording system, and means for controlling recording for data transfer and commands between functions, assigned to image feed device or recording device by setting, or for performing recording operation via recording device on basis of image data, sent from image feed device.
 Atm and method for its operation (variants) / 2248044
Methods for inputting data into ATM include following steps: forming an input signal when function key or auxiliary keyboard key is pressed at ATM panel, at the same time data inputted into ATM are assigned to pressed key, conversion of input signal from key to input signal, matching coordinate data of point of a point on screen of ATM, previously matched with pressed key, redirection of coordinate data input signal into computer data flow, meant for data input from mouse. Method for data input may have additional steps: forming of signal by pressing key of auxiliary keyboard, conversion of input signal from auxiliary keyboard key to input signal, matching key on standard letter-digit keyboard, previously matched with pressed key; redirection of received input into data flow of computer, meant for inputting data from standard keyboard. ATMs have computer and at least one device for performing financial operations in response to data input in computer, performed in accordance to methods for inputting data into ATM. Devices for storing software have software, providing for control of ATM in accordance to methods for inputting data in ATM.
 Ball manipulator / 2248604
Side and lower support elements of leading ball are made in form of circular rolling bearing, containing outer ring, in respective sockets of which two rows of balls are present, inner ring of circular rolling bearing is absent, while function of inner ring of circular roller bearing is performed by leading ball.
 Device for controlling information display in remote education system / 2248605
Device has base address selector, registers, delay elements, elements of OR groups, OR elements, memory block, reverse counter, comparator.
 Method and system for registering domain names with use of national languages in non-english-speaking countries / 2249843
Method includes detection of connection of user computer to Web-site of sub-domain on national language and selects service of registration of domain name on national language, performing software extension for automated forming of combination of symbols of English alphabet, matching domain name, based on national language, determining, whether such combination of English symbols was registered before as existing domain name, and, if not, then it is registered as domain name.
 Hardware-software device for multichannel conversion and recording of analog signals / 2250494
For each channel device has digital signal converter, block for setting conversion digitization frequency, conversion level adjustment block, block for transferring electric signals to physical values, block for observing converted signals, block of precision of signal conversion, block of signal conversion time, block for disabling unused channels, block for synchronization of analog signals, visualization block, converted signal recording block. Device allows to convert signals of different levels, to change digitization frequency and conversion time, to disable unused channels, transfer sensors signals to physical values with consideration of sensors scales, observe signals at different scales, appropriate to levels of converted signals, to measure precision of recording of converted signals.
 Method for inputting data into pc and device for inputting data into pc / 2251725
Method includes mounting information input device of wrist of operator, device has flexible cover in shape approximately matching shape of hand, and sensors connected to cover, then sensors are activated by pressing against a stop, which is a portion of operators body or object, external to operator body and placed within limits of range of free hand action by operator with mounted device.
 Device for inputting image into personal computer / 2256210
Device has CPU, control block, receipt register, buffer memory block, address counter, first and second channel transmitters blocks, PC connection block, amplifier, pulse generator, control signals generator, second receipt register, second buffer memory block, first, second and third buffer registers, receipt-transmission register, strings counter, adder, first string counter and digital comparator.
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FIELD: information technology. SUBSTANCE: invention relates to connecting devices for transmitting information for functional elements and can be used in designing self-synchronised digital computing devices and information processing systems based on microcircuits having large- and very-large integration level. The device consists of a channel for transmitting data from a four-phase self-synchronised interface to a synchronised parallel interface and a channel for transmitting data from a synchronised parallel interface to a four-phase self-synchronised interface. EFFECT: provision for two-way connection of digital microelectronic devices: with a synchronised parallel interface, and self-synchronised with a four-phase interface, with possibility of indicating readiness to receive data. 5 dwg
The invention relates to a device for the processing of digital data by means of an electrical device, in particular to the connecting devices transmit information to the functional elements, and is the interface device of the self-timed and synchronous interfaces of digital technology, and can be used when building a self-timed digital computing devices and systems for digital information processing on the basis of the chips are introduced into the degree of integration. When designing integrated circuits very large scale integration (VLSI), such as systems on a chip, one of the major problems is the mate of their constituent functional blocks. In modern VLSI shared digital devices operating on a synchronous basis, and devices with auto-synchronizing [2]. Use the four interfaces in the functional blocks with auto-synchronizing is the most efficient from the point of view of design and energy consumption by reducing the bit data bus (relative to interface with a two-rail representation of the data) and the number of elements in the schema pair of interfaces. The unification of the internal interconnect interfaces can significantly improve the time and cost performance. Current of the device is the means of interfacing synchronous parallel interfaces [1] and interface devices with auto-synchronizing are unidirectional and may not be universal, because they do not contain feedback signals, signaling readiness to receive the data unit receiver, which is a major drawback. It is known device SYNCHRONOUS INTERFACE TO A SELF-TIMED MEMORY ARRAY" (US patent 006,601,293 A 09.05.2000) of the same purposes, as proposed, but with common characteristics selected for the prototype, consisting of a data channel, the channel address and channel synchronization, and channel data consists of identical subchannels, each of which contains a buffer input (Input Buffer)connected to data inputs of the first latch (1st Stage Transparent Latches), the output of which is connected to data inputs of the first clocked flip-flop (2-nd Stage Pulsed Latches) and the first inverter, the output of which is connected to the data input of the second clocked trigger; channel address consists of series-connected input buffer address strobe (Input Buffer), the second latch (Transparent Latches) and the third clocked trigger; channel synchronization consists of series-connected buffer clock signal (Input Buffer), a configurable delay (Setup-Hold Adj. Delay) and the series connected second and third inverter, and the output of the second inverter is connected to the enable inputs of the first and second latches, the output of the second inverter is clocked by the input first, second and third, and the output of the second latch with inputs RA the decisions of the first and second clocked flip-flops. The main disadvantage of the considered device is that it provides for the transfer of information in one direction only, from the synchronous self-timed interface to; another disadvantage is the lack of feedback signals indicating readiness to receive the data unit receiver; not is not the task of interfacing to synchronous and four self-timed interfaces. The essence of the invention is a data exchange device for connecting digital functional blocks VLSI with four interface with auto-synchronizing [2] and synchronous parallel interface is designed to transmit information between unified microelectronic devices using different communication protocols within a VLSI, and allows the signal transmitting unit on availability of data reception. The technical result is the provision of bilateral linkages digital microelectronic devices with synchronous parallel interface and self-timed four interface with alarm ready acceptance of the data inside the chip. Comparative analysis with the prototype shows that the proposed device is characterized by the presence of new elements: data channel from cataractes the CSO self-timed interface in synchronous parallel, and consisting of a signal shaping circuit PROOF, the signal shaping circuit RESOLUTION and schema data, and diagram of the signal CONFIRMATION consists of the first buffer with a third state, connected to the first and the second input of the first NAND gate, the output of which is connected to a clock input of the first D flip-flop to the reset input of which is connected to the output of the third NAND gate, and the non-inverted output of which is connected to the input of the first pulse shaper, the output of which is connected to the input of the first element "NOT"connected to the first input of the second NAND gate, the output of which is connected to the input of the installation of the first RS-flip-flop, the non-inverted output of which is connected to the input data of the second buffer with a third state, with the second input of the third NAND gate, the output of which is connected to the reset input of the first D-flip-flop and the inverted output of the first RS-flip-flop is connected to the second input of the first element And whose output is connected to the reset input of the second D-flip-flop and the first input is combined with the second input of the second NAND gate and the second input of the second NAND gate"; the first element And whose output is connected to the reset input of the second D-flip-flop, the non-inverted output of which is connected to the input of the second pulse shaper connected to the PE the K input of the second element And, the output of which is connected to the reset input of the first RS-flip-flop, and the output of the first buffer with a third state is connected to the data input of the second D-flip-flop and the input set is combined with the input data and the setup of the first D-flip-flop and with the log. "1"; the scheme of signal RESOLUTION consists of the third buffer with a third state, connected with the data input of the third D-flip-flop, the non-inverted output of which is connected to the data input of the fourth buffer with a third state, with the second input of the fourth NAND gate and data inputs of the fourth D-flip-flop inverted output of which is connected to a second input of the fifth element "And"the entrance of the installation log. "1"and the reset input from the output of the fourth NAND gate, and the first input of the fifth element "And" combined with the second input of the fourth NAND gate, and an output connected to the reset input of the third D-flip-flop, the input set which is connected to the log. "1"; the scheme of data transmission consists of the fifth buffer with a third state, connected with the data input register, the output of which is connected to the data input of the sixth buffer with a third state, and the data transmission channel of the synchronous parallel interface in four self-timed, the output of which is connected to the input, and the input - output channel data from the four smashington the wow interface in synchronous parallel, consists of the seventh buffer with a third state, the output of which is connected with the second input of the first element "OR" and with the third pulse shaper connected to the input of the second element "NOT", the output of which is connected to the first input of the third NAND gate, and an output connected to the input of the second RS-flip-flop, the output of which is connected to the first input of the first element of "OR" and the eighth data input buffer with a third state; the ninth buffer with a third state, and the output connected to the input data of the fifth D-flip-flop, the signal - to log. "1", and the non-inverted output from the fourth pulse shaper, the output of which is connected to the first input of the fifth element "And", United with the reset input of the second RS-flip-flop; the third item is "NOT"connected with the control input of the eleventh buffer with a third state and control inputs of the seventh, eighth, ninth and tenth buffers with a third state. Therefore, the device meets the criterion of "novelty". Comparison with other technical solutions shows that the device has the elements of a duplex device interacts with a synchronous parallel interface and self-timed devices with four interface with signaling readiness to accept data. Image is eenie illustrated by drawings: figure 1 - structural diagram of the device for data exchange between the four self-timed and synchronous parallel interface; figure 2 - block diagram of the data transmission channel of the four self-timed interface in synchronous parallel; figure 3 - functional diagram of the data transmission channel of the synchronous parallel interface in four self-timed; 4 is a timing chart explaining the operation of the device in the data transmission mode of the four with auto-synchronizing parallel synchronous interface; 5 is a timing chart explaining the operation of the device in the data transmission mode of the synchronous parallel in the four interface with auto-synchronizing. The device data exchange between the four self-timed and synchronous parallel interface (figure 1) consists of a data transmission channel of the four self-timed interface in synchronous parallel 41, consisting of a signal shaping circuit PROOF 35, the signal shaping circuit RESOLUTION 36 and schema data 40 (figure 2), and the data transmission channel of the synchronous parallel interface in four self-timed 37 (3), the output of which is connected to the input, and the input - output channel data from the four samsungdong the interface in synchronous parallel 41, and the scheme of formation of the CONFIRMATION signal 35 (figure 2) consists of the first buffer with a third state 1, the input of which is the input QUERY, connected to the first and the second input of the first element "AND NOT" 4, the output of which is connected to a clock input of the first D-flip-flop 8 to the reset input R which is connected to the output of the third element "And" 5, and the non-inverted output Q connected to the input of the first pulse shaper 12, the output of which is connected to the input of the first element "NOT" 38 connected to the first input of the second NAND gate" 14, the output of which is connected with the input set S of the first RS-flip-flop 17, the non-inverted output Q of which is connected to the data input of the second buffer with a third state 19 whose output is the output of the CONFIRMATION, with the second input of the third element And 5, the output of which is connected to the reset input R of the first D-flip-flop 8, and the first input is combined with the RESET input, and the inverted output the scheme of signal RESOLUTION 36 (figure 2) consists of the third buffer with the third state 2, the inlet of which is the entrance BUSY, connected with the data input D of the third D-flip-flop 10, the non-inverted output Q of which is connected to the data input of the fourth buffer with a third state 20 whose output is the output RESOLUTION, with the second input of the fourth element "And" 16 and to data inputs D of the fourth D-flip-flop 18, the inverted output diagram data 40 (figure 2) consists of the fifth buffer with a third state 3, the input data which is combined with the input ADANYA connected to data input D of the register 11, a clock input which is combined with the signal CYCLE, the reset input is combined with the RESET input, and an output Q connected to the data input of the sixth buffer with a third state 21 whose output is the output STANNIE, and control inputs 3 fifth and sixth 21 buffers with a third state is connected to the input DIRECTION, and the data transmission channel of the synchronous parallel interface in four self-timed 37 (figure 3) consists of the seventh buffer with a third state 23, the input data which is combined with the entry CONFIRMATION, and the output is connected to the second input of the first element OR 32, and the third pulse shaper 27 connected to the input of the second element "NOT" 39, the output of which is connected to the first input of the third NAND gate" 29, the second input is connected with the RESET input and the output with the input set S of the second RS-flip-flop 31, the output of which is connected with the first input of the first element OR 32 and the eighth data input buffer with a third state 33, the output of which I have provided is the output REQUEST; the ninth buffer with a third state 24, the input data which is input RESOLUTION and the output is connected to data inputs D of the fifth D-flip-flop 26, the clock input C of which is connected to the input of the QUANTUM setting signal S is connected to the log. "1", the reset input R with a RESET input, and the non-inverted output Q from the fourth pulse shaper 28, the output of which is connected to the first input of the fifth element "And" 30, a second input connected to the RESET input, and an output connected to the reset input R of the second RS-flip-flop 31; the third element "NOT" 22, the inlet of which is the entrance DIRECTION, connected with the control input of the eleventh buffer with a third state 25, the inlet of which is the entrance STANNIE, and the output is ADANYA, and control inputs 23 seventh, eighth 33, 24 ninth and tenth 34 buffers with a third state, respectively. The device operates as follows. At the entrance DIRECTION of the device is set to a logical signal that determines the mode (direction) data. In the data transmission mode from the four interface with auto-synchronizing to a synchronous parallel with the log. "0" at the input of the DIRECTION diagram of the formation of the CONFIRMATION signal 35 through the first buffer with a third state 1 and the second buffer with the third condition 19, the signal RESOLUTION 36 through t eti buffer with a third state 2 and the fourth buffer with a third state 20 and diagram data 40 through the fifth buffer with a third state 3 and the sixth buffer with a third state 21 are connected to the inputs and outputs of the device. The data transmission channel of the synchronous parallel interface in four self-timed 37 is disconnected from the inputs and outputs of the device with the seventh 23, 33 eighth, ninth, 24, 34 tenth and eleventh 25 buffers with a third state. On the negative edge of signal CONFIRMATION device input ADANYA served transmitted data (figure 4). After the submission of the data signal at the output of the QUERY is set to log. "1", the device enters standby mode of arrival of the leading edge of the clock signal CLOCK. On the leading edge of the clock input signal CYCLE at the output of the circuit SANNIE is set to logical value, taken from the entrance ADANYA, the output RESOLUTION is set to log. "1", kept during the period of the clock signal. After setting a new value on the output device STANNIE, at the exit CONFIRMATION is set to log."1", then the device waits establish the input QUERY log. "0"; when the event occurs on the exit CONFIRMATION is set to log. "0". The level change of the output signal CONFIRMATION from the log. "1" on the log. "0" indicates the device is ready to receive and transmit a new datum. After the establishment of the signal at the input QUERY in the log. "1" on the leading edge of the clock signal at the input CYCLE to direct the output Q of the second D-flip-flop 9 is out of the log. "1". When the input signal from the log. "0" in the log. "1" the first pulse shaper 13 generates a pulse output, which, through the second element And 15 is fed to the reset input R of the first RS-flip-flop 17 and through the first element "NOT" 38 the second element "AND NOT" 14, the output of which sets the log. "0". In accordance with the standard truth table of the first RS-flip-flop 17 is set to direct the output Q is in the state log. "1", and the inverse After changing the signal level on the input QUERY from the log. "1" on the log. "0" at the output of the first NAND gate" 4 there is a change in signal from the log. "0" in the log. "1". On the resulting positive edge transition on the direct output Q of the first D-flip-flop 8 is set to log. "1". After changing the signal at the input of the first pulse shaper 12 from the log. "0" to the log. "1" at the output of the latter generates a pulse at the input of the second NAND gate" 14. In accordance with the standard truth table to direct the output Q of the first RS-flip-flop 17 is set to the alarm log. "0"and the inverse of - log. "1", which enters through the first item And 6 to the reset input R of the second D-flip-flop 9, and the signal is directly output through the third element "And" 5 to the reset input R of the first D-flip-flop 8, the direct output Q is set to log. "0". The input BUSY enters through the third buffer with the third state 2 to the input D of the third D-flip-flop 10. During the installation log. "1" on input D from the positive edge of the clock input CYCLE to direct the output Q of the third D-flip-flop 10 and the output RESOLUTION is set to log. "1". After installation, log. "1" at the input D of the fourth D-flip-flop 18 at its inverted output The input ADANYA through fifth buffer with a third state 3 is fed to the input D of the register 11 and on the positive edge of the clock signal CYCLE through sixth buffer with a third state 21 is transmitted to the output STANNIE device. In the data transfer mode from synchronous parallel interface to four with auto-synchronizing, with the log. "1" at the input DIRECTION, the data transmission channel of the synchronous parallel interface in four self-timed 37 is otkluchaetsia to the inputs and outputs of the device with the seventh 23, eighth 33, ninth, 24, 34 tenth and eleventh 25 buffers with a third state. In the log. "0" at the input of the CONFIRMATION in the log. "1" at the inputs of the RESOLUTION on the positive edge of the clock signal CYCLE at the outputs BUSY and the REQUEST to set the log. "1" (figure 5). When the BUSY output is set to log. "1", the device does not accept new data for transmission. When the output REQUEST is established log. "1", the device waits for establishing the input CONFIRMATION log. "1", after which the output REQUEST is set to log. "1", and the output BUSY is set to log. "0"that indicates the device is ready to accept new data for transmission. On the output device ADANYA input signals go directly. At the time of the establishment of the log. "0" on the RESET input of D-triggers: the first 8, second 9, the third 10, 18 fourth, fifth, 26, and RS-triggers: the first 17, the second 31 and the register 11 are set in the initial state, and their reinvestiruja the outputs are set to log. "0". After installation on the input RESOLUTION in the log. "1", which enters through the ninth buffer with a third state 24 to the input D of the fifth D-flip-flop 26, after the arrival of the leading edge of the clock input CYCLE, the direct output Q of which is set the alarm log. "1"at the input of the fourth pulse shaper 28, the output is which pulse appears, coming through the fifth element "And" 30 to the reset input R of the second RS-flip-flop 31, and then, on its direct output Q is set to the alarm log. "1", coming through eighth buffer with a third state 33 to the output REQUEST device. After establishing the input CONFIRMATION device log. "1", coming through the seventh buffer with a third state 23 to the input of the third pulse shaper 27, the output of the last generated pulse received through the second element "NOT" 39 to the input of the third NAND gate" 29 and with its output to the input set S of the second RS-flip-flop 31, the direct output Q of which is set to log. "0". The output signal of the seventh buffer with a third state 23 and the direct output Q of the second RS-flip-flop 31 receives the inputs of the second element OR 32, the output of which through the tenth buffer with a third state 34 signal on the BUSY output device. Data from input devices STANNIE through eleventh buffer with a third state 25 are output devices ADANYA. The signal from the RESET input goes through the elements "And"third 5, the first 6, 7 fifth and fourth 16 to the reset input R of the D flipflops: the first 8, second 9, the third 10 and fourth 18, respectively, through the second element "AND NOT" 14 and the second element "And" 15 - to the reset input R of the first RS-flip-flop 17; through the third element "AND NOT" 29 and the fifth element is" 30 - to the reset input R of the second RS-flip-flop 31 and directly to the reset input R of the fifth D-flip-flop 26 and the register 11. In the log. "0" on the reset input R direct outputs Q of the trigger and register are in the log. "0"and the inverse The pulse shapers: the first 12, second 13, 27 third and fourth 28 may be made under the scheme with Schmitt trigger and RC-circuit, described in [3], p.83. The result is a two-way communication between a device with a synchronous parallel interface and the device with self-timed four interface; this ensures the alarm ready acceptance of data by the receiver in all modes of operation. Sources of information 1. Patent US 006,601,293 A 09.05.2000 ((SYNCHRONOUS INTERFACE TO A SELF-TIMED MEMORY ARRAY. 2. Jens Spars⌀, Steve Furber. Principles of asynchronous circuit design - A System Perspective. Kluwer Academic Publishers. ISBN 0-7923-7613-7. 3. Novikov YU.V. fundamentals of digital circuitry. Basic elements and circuits. Design methods. - M.: Mir, 2001. - 379 C., Il. - (Modern circuitry). ISBN 5-03-003449. The device data exchange between the four self-timed and synchronous parallel interface containing the channel data from the four self-timed interface in a synchronous and parallel data transmission channel of the synchronous parallel interface in the four with makingany, the output data of which is connected with the corresponding input, and the input data with the corresponding channel output data from the four self-timed interface in synchronous parallel, the output of the CONFIRMATION of the data transmission channel of the four self-timed interface in synchronous parallel connected to the input of the CONFIRMATION of the data transmission channel of the synchronous parallel interface in four self-timed, the output RESOLUTION of the data transmission channel of the four self-timed interface in synchronous parallel connected to the input RESOLUTION of the data transmission channel of the synchronous parallel interface in four self-timed, the output REQUEST of the data transmission channel of the synchronous parallel interface in four self-timed connected to the input of the channel REQUEST data from four self-timed interface in synchronous parallel, the BUSY output of the data channel of the synchronous parallel interface in four self-timed connected to the input BUSY data channel from the four self-timed interface in synchronous parallel, characterized in that the data transmission channel of the four self-timed interface in synchronous parallel consists of the formation pattern of the signal is and the CONFIRMATION the signal shaping circuit RESOLUTION and scheme data, the scheme signal CONFIRMATION consists of the first buffer with a third state, the input data which is input to the channel REQUEST data from the four self-timed interface in synchronous parallel, and the output is connected to the first and second inputs of the first NAND gate, the output of which is connected to a clock input of the first D flip-flop to the reset input of which is connected to the output of the third NAND gate, and the non-inverted output of which is connected to the input of the first pulse shaper, the output of which is connected to the input of the first element "NOT", the output of which is connected to the first input of the second NAND gate, the output of which is connected to the input of the installation of the first RS-flip-flop, the non-inverted output of which is connected to the data input of the second buffer with a third state, with the second input of the third NAND gate, the output of which is connected to the reset input of the first D-flip-flop and the inverted output of the first RS-flip-flop is connected to the second input of the first element And whose output is connected to the reset input of the second D-flip-flop and the first input is connected with the second input of the second NAND gate" and the second input of the second element "And"non-inverted output of the second D-flip-flop connected to the input of the second driver impul the sa, the output of which is connected to the first input of the second element And whose output is connected to the reset input of the first RS-flip-flop, and the output of the first buffer with a third state is connected to the data input of the second D-flip-flop and the input set is combined with the input data and the setup of the first D-flip-flop and the input of the log."1" channel data from the four self-timed interface in synchronous parallel, the output of the second buffer is the CONFIRMATION of the data transmission channel of the four self-timed interface in synchronous parallel; the scheme of signal RESOLUTION consists of the third buffer with the third condition, the input data which is input BUSY data channel from the four self-timed interface in synchronous parallel, and the output is connected to the data input of the third D-flip-flop, the non-inverted output of which is connected to the data input of the fourth buffer with a third state, with the second input of the fourth NAND gate and data inputs of the fourth D-flip-flop, inverted output of which is connected to a second input of the fifth element "And", the input set with the input log."1" channel data from the four self-timed interface in synchronous parallel, and the reset input from the output of the fourth NAND gate, and the first input of the fifth ele the enta And combined with the second input of the fourth element "And", and the output is connected to the reset input of the third D-flip-flop, the input set which is connected to the input log."1" channel data from the four self-timed interface in synchronous parallel, the output of the second buffer is the output RESOLUTION of the data transmission channel of the four self-timed interface in synchronous parallel; a data transmission consists of the fifth buffer with a third state, the input of which is the entrance DIRECTION of the channel data from the four self-timed interface in synchronous parallel, and the output connected to the input data register, the output of which is connected to the data input of the sixth buffer with a third state, the output of which is output data of the channel data from the four self-timed interface in synchronous parallel clock inputs of the second, third, D-triggers and register are clocked input data channel from the four self-timed interface in synchronous parallel, the second input of the second NAND gate, the first input of the third element And the second input of the second element And the first input of the first element And the first input of the fifth element "And", the second input of the sixth NAND gate and the output of the reset register are reset input channel data from the four self-timed is of interfaces in synchronous parallel, the control inputs of the first, second, third, fourth, fifth, sixth buffers are input DIRECTION of the channel data from the four self-timed interface in synchronous parallel; a data transmission channel of the synchronous parallel interface in four self-timed consists of the seventh buffer with a third state, the input of which is the input of the CONFIRMATION of the data transmission channel of the synchronous parallel interface in four self-timed, and the output is connected to the second input of the first element "OR" and with the input of the third pulse shaper, the output of which is connected to the input of the second element "NOT", the output of which is connected to the first input of the third element And-NOT", the output of which is connected to the input of the second RS-flip-flop, the output of which is connected to the first input of the first element of "OR" and the eighth data input buffer with a third state, the output of which is an output REQUEST of the data transmission channel of the synchronous parallel interface in four self-timed; the ninth buffer with a third state, the input of which is the input RESOLUTION of the data transmission channel of the synchronous parallel interface in four self-timed, and the output connected to the input data of the fifth D-flip-flop, signal installation which is connected to the progress log."1" channel data from the synchronous parallel interface in four self-timed, and non-inverted output to the input of the fourth pulse shaper, the output of which is connected to the first input of the fifth element "And", the output of which is connected to the reset input of the second RS-flip-flop; a third element "NOT", the entrance of which is the entrance DIRECTION of the data transmission channel of the synchronous parallel interface in four self-timed, and the output connected with the control input of the eleventh buffer with a third state and control inputs of the seventh, eighth, ninth and tenth buffers with a third state, the input data of the tenth buffer with a third state is connected to the output of the first element, "OR", and the output is output "BUSY" data transmission channel of the synchronous parallel interface in four self-timed, and the input data of the eleventh buffer with a third state is the input data of the data channel of the synchronous parallel interface in four self-timed, and the output of the output data of the data channel of the synchronous parallel interface in four self-timed, the second inputs of the seventh and eighth elements "And" and the reset input of the fifth D-flip-flop are reset input of the data transmission channel of the synchronous parallel interface in four self-timed.
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the first RS-flip-flop 17 is connected to a second input of the first item And 6, the output of which is connected to the reset input R of the second D-flip-flop 9, and the first input combined with the second input of the second NAND gate 14 to the second input of the second element And 15 and a RESET input; the first item And 6, the output of which is connected to the reset input R of the second D-flip-flop 9, the non-inverted output Q to the which is connected to the input of the second pulse shaper 13, connected to the first input of the second element And 15, the output of which is connected to the reset input R of the first RS-flip-flop 17, and the output of the first buffer with a third state 1 is connected to the data input D of the second D-flip-flop 9, a clock input which is combined with the signal CYCLE, and the input set S is combined with the input data D and the installation's first D-flip-flop 8 and the log. "1", and the control inputs of the first 1 and second 19 buffers with a third state is combined with the input DIRECTION;