Device for inputting image into personal computer

FIELD: computer science.

SUBSTANCE: device has CPU, control block, receipt register, buffer memory block, address counter, first and second channel transmitters blocks, PC connection block, amplifier, pulse generator, control signals generator, second receipt register, second buffer memory block, first, second and third buffer registers, receipt-transmission register, strings counter, adder, first string counter and digital comparator.

EFFECT: higher speed of operation.

2 cl, 2 dwg

The invention relates to computer technology and can be used in vision systems for entering information into a computer.

A device for inputting image in the computer (A.S. No. 1432494 the USSR, CL G 06 F 3/00, 1988, bull. No. 39), containing the shift register, the control unit, the bit counter, a register, and the address counter, the pulse shaper, the block buffer memory block channel transceivers, the communication unit with a computer.

A disadvantage of this device is a low speed, as for image input in the computer you want to transfer to the device address of each input picture element.

Closest to the present invention is a device for inputting image in the computer (U.S. Pat. No. 2166790 RF, CL 7 G 06 F 3/00, 2000, bull. No. 13)that contains a control unit, a register, and the buffer memory, the address counter, the communication unit with a computer, the ADC, the first and second blocks channel transmitters.

A disadvantage of this device is a low speed.

The technical task of this device is to increase the speed of the image input in the computer.

The technical problem is solved in that the device for image input in the computer that contains the ADC, the control unit, register, buffer memory, the address counter, the first and second blocks channel transmitters, the communication unit from the computer, put the amplifier, the pulse generator is in, driver control signals (FSD), second register receiving the second block of the buffer memory, the first, second and third buffer registers, the register of acceptance, row count, adder, counter, first line, and a digital comparator, and an information output of the cameras connected to the input of the amplifier, the output of which is connected to the ADC input and the input of the shaper control signals (FSD), the first group of outputs of which are connected with the first group of inputs of the control unit, the first output FSD connected to the third input of the register of acceptance and to the first input of the control unit (cu), and the second output FSD is connected to a second input of the counter of the first line, the output of the ADC connected to the first input register of acceptance, a second input connected to the output of pulse generator (GI) and the seventh input of the control unit (cu), the eight-bit output register of reception and transmission is connected to the data inputs of the first and second registers of admission, the first control input of the first register connected to receive the first Manager of the input of the first buffer memory and the first output of the third group of outputs BO, the second control input of the first register connected to receive the first Manager of the input of the second register and receive a second output of the third group outputs BO, the second control input of the second register connected to receive Ervin managing input of the second buffer memory and the third output of the third group of outputs BOO, information outputs of the first register connected to receive information inputs-outputs of the first buffer memory and information inputs of the first block channel transmitters, information outputs which together with the information outputs of the second block channel transmitters are a group of outputs of the device to connect to the data bus of the computer, the information outputs of the second register connected to receive information inputs-outputs of the second buffer memory and information inputs of the second block channel transmitters, the control input of the first and second blocks channel transmitters connected to the first output of the first group of outputs BO, the second control inputs of the first and second blocks of the buffer memory is connected to the second output of the first group outputs BOO, the third output of the first group of outputs BOO is connected to the enable input data output of the third buffer register, the information outputs of which are combined with the information outputs of the first buffer register and connected to information inputs-outputs of the first and second blocks of the buffer memory, the information input of the third buffer register connected to the information output row count, the first input of which is connected to the sixth output of the second group of outputs BOO, and the second input row count is otklyuchen to the fifth output of the second group of outputs BOO, the first output of the second group of outputs BOO is connected to a second input of the counter is the length of the string, the first input of which is connected with the second output of the second group of outputs BOO, and information outputs of the counter is the length of the string is connected to the second group of inputs of the digital comparator, the output of which is connected with the eighth input BU, the third output of the second group of outputs BOO is connected to the enable input data output of the first buffer register, the fourth output of the second group of outputs BOO connected to the first input of the counter of the first row, the outputs of which are connected to the first group of inputs of the adder, to the information input of the first buffer register and the first group of inputs of the digital comparator in addition, the first, second and third outputs of the fourth group of outputs BOO connected respectively with the first, second and third inputs of the address counter whose outputs are connected to the address inputs of the first and second blocks of the buffer memory and the second group of inputs of the adder, the outputs of which are connected to information inputs of the second buffer register, a control input which is connected to the fourth output of the fourth group of outputs BOO, information outputs of the second buffer register connected to information inputs of the address counter, the address lines of the ISA bus is connected with the first group of inputs of the unit for communication with a computer, the first, the second and the third outputs which are connected respectively with the first, the second and third inputs of the second group of inputs BOO, control lines on the ISA bus, namely RESET, AEN, T/C, IOR and OUTLETS connected respectively to the sixth, fifth, fourth, third and second inputs BOO, the sixth input BU also connected with the third input of the counter of the first row, and the fifth input BU is also connected to the first input of the unit for communication with a computer, the first output BU connected to the control line DRQ ISA bus.

The invention is illustrated by drawings, where figure 1 presents a structural diagram of a device for inserting an image into a computer, and Fig. 2 presents a diagram of the control unit.

A device for inputting image in the computer contains information on input 1, the imaging unit control signals 2, amplifier 3, the pulse generator 4, the control unit 5, a communication unit with a computer 6, the ADC 7, the register of acceptance 8, the counter first-line 9, the counter length of the string 10, the first and second registers receive 11 and 12, the adder 13, the first, second and third buffer registers 14, 16 and 18, the digital comparator 15, the row count 17, the address counter 19, the first and second blocks of the buffer memory 20 and 21, the first and second blocks channel transmitters 22 and 23, a data bus 24, the address bus 25, bus control signals 26, and the information output of the TV camera 1 is connected to the input of the amplifier 3, the output of which is connected to the ADC input 7 and input shaper control signals (FSD) 2, first gruppovuha which is connected with the first group of inputs of the control unit 5, the first output FSD 2 is connected to the third input of the register of acceptance 8 and to the first input of the control unit (cu) 5, and the second output FSD 2 is connected to a second input of the first counter line 9, the ADC output 7 connected to the first input register of acceptance 8, a second input connected to the output of pulse generator (GI) 4 and the seventh input of the control unit (cu) 5, the eight-bit output register of acceptance-transmission 8 is connected to the data inputs of the first and second registers receive 11 and 12, the first control input of the first register receiving 11 is connected with the first Manager of the first input block buffer memory 20 and the first output of the third group of outputs BU 5, the second control input of the first register receiving 11 is connected to the first Manager of the input of the second register receiving 12 and a second output of the third group of outputs BU 5, the second control input of the second register receiving 12 is connected with the first Manager of the input of the second buffer memory 21 and the third output of the third group of outputs BU 5, the information outputs of the first register 11 is connected to receive information inputs-outputs of the first block of the buffer memory 20 and the information inputs of the first block channel transmitter 22, the information outputs of which together with the information outputs of the second block channel transmitter 23 are a group of outputs of the device to connect the program to the data bus of the computer 24, information outputs of the second register receiving 12 is connected to information inputs-outputs of the second buffer memory 21 and the information inputs of the second block channel transmitter 23, the control input of the first and second blocks channel transmitters 22 and 23 connected to the first output of the first group of outputs BU 5, the second control inputs of the first and second blocks of the buffer memory 20 and 21 is connected to the second output of the first group of outputs BU 5, the third output of the first group of outputs BU 5 is connected to the enable input data output of the third buffer register 18, the information outputs of which are combined with the information outputs of the first buffer register 14 and connected to the information inputs-outputs of the first and second blocks of the buffer memory 20 and 21, the information input of the third buffer register 18 is connected with the information output row count 17, the first input of which is connected to the sixth output of the second group of outputs BU 5, and the second counter input lines 17 is connected to the fifth output of the second group of outputs BU 5, the first output of the second group of outputs BU 5 is connected to a second input of the counter is the length of the string 10, the first input of which is connected with the second output of the second group of outputs BU 5, and the information outputs of the counter length of the line 10 is connected to the second group of digital inputs comparator 15, the output of which is connected with the eighth input BU 5, the third output of the second group of outputs BU 5 is connected to the enable input data output of the first buffer register 14, the fourth output of the second group of outputs BU 5 connected to the first input of the first counter line 9, the outputs of which are connected to the first group of inputs of the adder 13 to the information inputs of the first buffer register 14 and to the first group of inputs of the digital comparator 15, the first, second and third outputs of the fourth group of outputs BU 5 are connected respectively with the first, second and third inputs of the address counter 19, the outputs of which are connected to address inputs of the first and second blocks of the buffer memory 20 and 21 and the second group of inputs of the adder 13, the outputs of which are connected to information inputs of the second buffer register 16, the control input of which is connected to the fourth output of the fourth group of outputs BU 5, the information outputs of the second buffer register 16 is connected to information inputs of the address counter 19, the address lines of the ISA bus 25 is connected with the first group of inputs of the unit for communication with a computer 6, the first, second and third outputs of which are connected respectively with the first, second and third inputs of the second group of inputs BU 5, control lines on the ISA bus 26, namely RESET, AEN, T/C, IOR and OUTLETS connected respectively to the sixth, fifth, fourth, third and second inputs BU 5, the sixth input BU 5 is connected with the third in the Odom counter of the first row 9, and the fifth input BU 5 is also connected to the first input block connection to the computer 6, the first output BU 5 is connected with the control line DRQ ISA bus 26.

The driver control signal 2 is designed to generate control signals. From the signal coming from the camera, FSD allocates personnel, line pulses, their inversion, polugotovye impulse and its inversion, the momentum of the beginning of the odd frame, the momentum of the mid-frame and the second line impulse, but of less duration. All these pulses are on BOO 5.

Amplifier 3 provides the amplitude of the video signal required for normal operation of the ADC 7 and FSD 2.

The pulse generator 4 generates a sequence of pulses with a frequency of 7 MHz.

The control unit 5 is designed to control the reception or transmission of one frame of the television image in the computer. The control unit contains the first 27 and second 29 and 30 third counters, the first 28 and second 32 and third 33, 34 fourth, fifth, 35, 38 sixth, seventh 39, 41 eighth, ninth 42, tenth 44, eleventh 45, twelfth 46, thirteenth 48, fourteenth 53, fifteenth 54, sixteenth 58, seventeenth 60, eighteenth 61, nineteenth 66, twentieth 72 and twenty-first 86 items are NOT the first 31, second 40, third 69, 82 fourth and fifth 83 elements OR the first 36, second 51, the third 52, 55 fourth, fifth, 59, 62 sixth, seventh 63, 70 eighth and ninth 75 triggers, p. the pout 37, the second 43, 47 third, fourth, 49, 50 fifth, sixth, 56, 57 seventh, eighth 65, ninth 71, tenth 79, eleventh 81, twelfth 84 and thirteenth 85 elements AND IS NOT, the first 64, 67 second, third, 68, 74 fourth, fifth, 76, 77 sixth, seventh 78 and 80 eighth elements And element AND-OR-NOT 73, AND the input From the first counter 27 is combined with the reset input of the sixth trigger 62 and is the seventh sign-BOO, and the entrance SR first counter 27 United with the input set of the seventh trigger 63, to the inputs of SER, D, the SET of the first and second counters 27 and 29, the inputs D and the SET of the third counter 30 filed logical unit, the output 2 of the first counter 27 is combined with the input of the eighth element 41 and connected to the first input of the seventh element AND 57, the output of the eighth element 41 is connected to the input of the twelfth element 46, the output of which is connected to the input of the fourteenth item NO 53, whose output is connected to the second input of the seventh element AND-NOT 57 whose output is the second output of the third group outputs BU 5 and is connected to the input of the installation of the sixth trigger 62, whose direct output connected to the first inputs of the second 67 and 68 third element And the second input of the second element And 67 connected to the output of the nineteenth item NO 66, whose input is combined with the second input of the third element And 68, connected to the output 3 of the first counter 27, the output of the second element And 67 is connected to the first input of the twelfth element AND-NOT 84, the output of the third element And 68 connected to the first input of the thirteenth element AND-NOT 85 and to the input of the twentieth element 72, the output of which is connected to the input setup ninth trigger 75, a second input of the sixth element And 77 and a second input of the seventh element And 78, a direct output of the ninth trigger 75 is connected to the fourth input of the sixth element And 77 and the first input of the seventh element And 78, the input of the first element 28 is combined with the first input of the third element AND-NOT 47, and is the first entry of the first group of inputs BOO, the output of the first element 28 is connected to the input the fourth element 34, the output of which is connected to the input of the ninth element 42 whose output is connected to a second input of the third element AND 47, the output of which is combined with the reset inputs of SR 29 second and third 30 meters and is connected to the input of the tenth element 44, the output of which is connected to a second input of the eleventh element AND-NOT 81, exit ART of the second counter 29 is connected to the input of the SERIES of the third counter 30, the output 0 of which together with the output 3 of the second counter 29 are respectively the second and first inputs of the second element AND 43, whose the output is connected to the input of the installation of the fourth flip-flop 55, the direct output of which is input to the fifteenth element 54, the first input of the eighth element AND-NOT 65, the fourth input of the seventh element And 78, the second input is m the tenth element AND-NOT 79, a second input of the eighth element 80, the fourth input of the first element And element AND-OR-NOT 73, a second input of the third element And element AND-OR-NOT 73, the output of the fifteenth element 54 is input sixteenth element 58, the output of which is connected to the input of the eighteenth item NO 61, whose output is connected to a second input of the eighth element AND-NOT 65, the output of which is connected to the input of the installation eighth trigger 70, the reset input of which is combined with the reset input of the ninth trigger 75 and the input synchronization 29 second and third 30 meters, the first inputs 76 fifth and eighth 80 elements And is the fourth sign of the first group of inputs BU 5, direct access to the eighth trigger 70 is connected to the third input of the sixth element And 77 and to the second input of the third element OR 69, the output of which is connected to the fourth input of the twelfth element AND 84, with the fourth input of the thirteenth element AND-NOT 85 and the second input of the first element And element AND-OR-NOT 73, the inverted output of the eighth trigger 70 is connected to the first input of the tenth element AND 79, the input of the fifth element 35 is the sixth entry the first group of inputs BU 5 and combined with the first input of the sixth element AND 56, the third input of the third element And element AND-OR-NOT 73, the first input of the fourth element And 74 and with the reset input of the seventh trigger 63, with direct access to the showing connected to the third input of the seventh element And 78, to the third input of the twelfth element AND 84 and to a third input of the thirteenth element AND-NOT 85, the output of the fifth element 35 is connected to the input of the eleventh element 45, the output of which is input to the thirteenth item NO 48, whose output is the second input of the sixth element AND 56 whose output is the first output of the second group of outputs BU 5, the first input of the first element 31 is combined with the input of the third element 33 and is the sixth sign-BU 5, the second input of the first element 31 is combined with the input of the seventh element 39 and is the fourth entrance BU 5, the output of the first element 31 is connected to the reset input of the first trigger 36, set input connected to the output of the second element 32 and the third output of the first group of outputs BU 5, direct the first flip-flop 36 is connected to the first input of the fourth element AND-NOT 49, the second input is combined with the first input of the fifth element AND-NOT 50, with the second input of the fifth element And 76, and is the fifth sign of the first group of inputs BU 5, the output of the fourth element AND-NOT 49 is a reset input of the fifth trigger 59, inverted output the first flip-flop 36 is connected to the second input of the fifth element AND-NOT 50, the output of which is the fifth output of the second group of outputs BU 5, and the input set of the fifth trigger 59, straight out of which the connection is to the third input of the ninth element AND-NOT 79, to the second input of the twelfth element AND-HE 84, to the second input of the thirteenth element AND 85, to the third input of the eighth element, And 80, to the first input of the eleventh element AND 81, the third input of the first element And element AND-OR-NOT 73, the first input of the second element And element AND-OR-NOT 73, the first input of the third element And element AND-OR-NOT 73, in addition, the inverted output of the fifth trigger 59 is connected to the first input of the fourth element And element AND-OR-NOT 73 to the first input of the ninth element AND 71, the output of the third element 33 is connected to the first input of the first element AND NOT 37, the second input is a second input BU 5 and combined with the second input of the second element OR 40, and the output is the reset input of the second trigger 51, the input set which is connected to the output of the sixth element 38, the inverted output of the second trigger 51 is connected to the first input of the second element OR 40 whose output is the input set of the third trigger 52, a reset input which is the output of the seventh element 39, and the outlet of the third the trigger 52 is connected to the first input of the first element And 64, a third input connected to the output of the seventeenth element 60, the output of the first element And 64 connected to the second input of the fourth element And element AND-OR-NOT 73, to the second input of the ninth element AND 71 and to the first input of the fourth the element OR 82, the second input is combined with the input of the second element 32 and is the first entry of the second group of inputs BU 5, the third input of the fourth element OR 82 is combined with the input of the twenty-first element 86 and the second input of the second group of inputs BU 5, the outputs of the fifth 76 and 77 sixth elements are respectively first and second inputs of the fifth element OR 83, the output of which is connected to the first input of the first element And element AND-OR-NOT 73 and is the fourth output of the second group of outputs BU 5, you can also sign seventeenth element 60 is the third entrance BU 5, the second input of the first element And 64 is the fifth sign-BU 5, the first input of the third element OR 69 is the eighth sign-BU 5, the reset input of the fourth trigger 55 is a second input of the first group of inputs BU 5, the first input of the sixth element, And 77 is the third entry of the first group of inputs BU 5, the second input of the second element And element AND-OR-NOT 73 is the seventh sign of the first group of inputs BU 5, the input of the sixth element 38 is the third entry of the second group of inputs BU 5, direct the output of the second trigger 51 is the first output BU 5, the output of the fourth element OR 82 and the output of the ninth element AND 71 are respectively the first and second outputs of the first group of outputs BU 5, the output of the seventh element And 78, the output of the twenty-first element 86 is the output of the eighth element And 80 are respectively the second, the third and sixth outputs of the second group of outputs BU 5, the output of the twelfth element AND-NOT 84 and the output of the thirteenth element AND 85 are respectively the first and third outputs of the third group of outputs BU 5, the output of the tenth element AND 79, the output of the eleventh element AND 81, the output of element AND-OR-NOT 73 and the output of the fourth element And 74 are respectively the first, second, third and fourth outputs of the fourth group of outputs BOO 5.

Block connection to the computer 6 is designed to organize information exchange device for inputting image in the computer with the computer, its function is the decoding of the address.

ADC 7 is a one-bit analog-to-digital Converter and designed for converting the analog video signal coming from the amplifier 3, in a digital binary code.

Register of acceptance 8 is designed to form a parallel eight-bit code from the sequence of signals received from the ADC 7.

The counter of the first row 9 counts the number of bytes of the first line of odd field.

The meter is the length of the string 10 is designed to count the number of bytes in each line except the first line of odd field.

The registers receive 11 and 12 are designed to receive the incoming eight-bit code, and then send it in the first 20 and second 21 blocks of the buffer memory.

Sum the ATOR 13, buffer register 16, the address counter 19 are used to form the address of RAM (blocks of buffer memory 20 and 21), in which data of odd fields are written in odd rows of RAM, while the even - numbered lines.

Buffer registers 14, 18 are used to form the delay data and addresses.

Digital comparator 15 is designed to compare the length of the first line image with the length of the subsequent rows.

Row count 17 is designed to count the number recorded in the blocks of the buffer memory 20 and 21 rows of the image frame. The first counter input lines 17 is a counter input and the second input row count 17 is a reset input.

The blocks of the buffer memory 20 and 21 (RAM) are used for memorizing and storing the entered frame of the television image. The blocks are static memory elements.

Blocks channel transmitters 22 and 23 are intended for information transfer in channel computer and consist of two eight transmitters each.

The device operates as follows. A device for inputting image in the computer operates in two modes: input from cameras in blocks of buffer memory 20 and 21 and the transmission of information in the computer.

The mode information input from the camera in the blocks of the buffer memory 20 and 21.

In this mode, the video information received from the camera enters the mouth of austo and stored in blocks of the buffer memory 20 and 21 (RAM). The order of operations the following. After power on, the computer generates a RESET signal, the duration of which standard ISA for at least 1 MS. When the counter RESET signal of the first row 9 is reset to 0 and prepares BU 5 to work.

Write data received from the camera, in the blocks of the buffer memory 20 and 21 begins with the 24-th row of each field.

Information signal from the camera is amplified by the amplifier 3 and is supplied to the ADC 7, which converts this signal into a binary code and passes in case of acceptance 8. The signal received from the amplifier 3, is supplied also to the input of FSD 2, which allocates personnel, line pulses, their inversion, polugotovye impulse and its inversion, the momentum of the beginning of the odd frame, the momentum of the mid-frame and the second line impulse, but of less duration. These signals form the first group of inputs BOO 5. The pulse generator 4 generates rectangular pulses with a frequency of 7 MHz is supplied to the second input register of the reception-transmission 8 and the counter 27, to the inputs of SER, D, the SET of which is filed with the logical unit. Upon receipt of these pulses the contents of register acceptance 8 arrives at its outputs. One pulse corresponds to one bit of information. In the beginning of each line register of acceptance 8 is set to zero. With the help of the counter 27 is counting the number of pulse of the century Every eight pulses is write the contents of the register of transfer and acceptance of 8 registers receive 11 or 12. Write eight bits in the register of the receiving 11, the following eight bits in register receive 12 etc.

To write in blocks of buffer memory lines of the same length, the device includes a first counter line 9, which performs counting the number of elements in the first row. Count string length 10 counts the number of elements in all the other rows, and a digital comparator 15 compares the number of elements of the 1st line with the amount recorded in the blocks of the buffer memory 20 and 21 items for each of the subsequent rows. In case of equal number of elements of the 1st row and the current record is terminated and the current value of the address is added to the number stored in counter 1-th row. Thus, the entry in the blocks of the buffer memory 20 and 21 elements of the next row begins with addresses, separated from the current on 1 line. Record items in the following fields of the frame will start from the address following the address of the last element of the 1st row. Thus, it is interlaced recording the received information in the blocks of the buffer memory 20 and 21.

The counter 17 provides the number of lines recorded in the blocks of the buffer memory 20 and 21. If necessary, the ISA bus can be considered as the counter contents of the first row 9 what about the address 0361 and the contents of the count of rows 17 to address 0360. When the respective addresses of the communication unit with a computer 6 generates a signal supplied to the second or first input of the third group of inputs BU 5 BU 5 sends a signal that enables the data output buffer register 14 or 18, respectively.

The mode of data transmission in computers.

In this mode, the information recorded in the blocks of the buffer memory 20 and 21, is read by the computer when performing the operation “Enter”. In the address space of the computer device takes three addresses.

When performing a read controller PDP computer generates the address of a memory location where data is read, and then on the fifth input BU 5 and the first input of the unit for communication with a computer 6 sends a signal AEN, allowing to exchange. Then on the third input BU 5 receives a read strobe IOR (RAP)that is used for reading data from blocks channel transmitters 22 and 23 (the RAM buffers 22 and 23). These data are SM ISA.

To read the number of elements in the first row (in all other lines of the same number of elements) computer puts on the address bus AD0..11 address 0361. When this address block connection to the computer 6 generates a second output signal which is fed to the element 86 and NOT the item OR 82, thereby allowing the data output buffer register 14, which contains the number of elements of the first row, and the issue of data blocks of channel p is redaccion 22 and 23 on the ISA bus.

When addresses 0360 unit for communication with a computer 6 generates a first output signal which is fed to the element 32 and the element OR 82. The signal after the element OR 82 permits the issuance of data blocks channel transmitters on the ISA bus. The signal after the element 32 allows the data output buffer register 14, which contains the number of rows written to the blocks of the buffer memory 20 and 21. Thus, the ISA bus is given information about the number of rows contained in the blocks of the buffer memory 20 and 21. When the start of frame pulse, indicating that began digitizing the next frame, the output element AND-NOT 49 is formed logical 0, which resets the trigger 59. A logical 1 on the inverse of the output of the trigger 59 and logical unit output element 64 is formed at the output of element AND-NOT 71 logical 0, which goes to the inverted enable input of the read blocks of buffer memory 20 and 21.

If the computer sends the address 0362, the communication unit with a computer 6 generates at its 3rd output signal, which inverters on the item is NOT 38, switches the trigger 51 in one state, thereby forming a request to RAP on line DRQ, which is the first exit BOO 5. After the liberation of the ISA bus (the bus can be occupied by sharing with another device) current setpoint becomes the controller of PDP computers. The controller PDP computer generates the ACK signal on the second input BU 5, which, together with the logical 0 to the inverse output of the trigger 51 generates a logic 0 at the output of the OR element 40 that allows you to set the trigger 52 in one state. When RAP the computer generates a signal AEN, a negative signal IOR that arrive on the 3rd and 5th input BU 5, respectively. Thus, the inputs of the element 64 receives a logic 1 from the output of the trigger 52 and the output element 60, and the signal AEN. Output element And 64 thus forming a logical 1, which, when input element AND NOT 71, generates a logic 0 at its output which is fed to an inverse input resolution reading blocks of buffer memory 20 and 21. Logic 1 from the output element And 64 passing through the element OR 82, is supplied to the enable input of the data output units channel transmitters 22 and 23.

After reading the computer generates a signal T/S, confirming that the transfer has finished and prepares the device for a new cycle of operation.

Thus, with the introduction of the amplifier, pulse generator, generator control signals (FSD), second register receiving the second block of the buffer memory, the first, second and third buffer register, register of acceptance, row count, adder, counter first line and a digital comparator increases the speed of the image input in the computer.

1. The input device is zobrazenie in the computer, contains an ADC, a control unit, a register, and the buffer memory, the address counter, the first and second blocks channel transmitters, the communication unit with a computer, characterized in that the device entered amplifier, pulse generator, the driver control signals (FSD), second register receiving the second block of the buffer memory, the first, second and third buffer registers, the register of acceptance, row count, adder, counter, first line, and a digital comparator, and an information output of the cameras connected to the input of the amplifier, the output of which is connected to the ADC input and the input of the shaper control signals (FSD), the first group of outputs of which are connected with the first group of inputs of the control unit, the first output FSD connected to the third input of the register of acceptance and to the first input of the control unit (cu)and the second output FSD is connected to a second input of the counter of the first line, the output of the ADC connected to the first input register of acceptance, a second input connected to the output of pulse generator (GI) and the seventh input of the control unit (cu), the eight-bit output register of reception and transmission is connected to the data inputs of the first and second registers of admission, the first the control input of the first register connected to receive the first Manager of the input of the first buffer memory and the first output of the third group in the moves BOO, the second control input of the first register connected to receive the first Manager of the input of the second register and receive a second output of the third group of outputs BO, the second control input of the second register connected to receive the first Manager of the input of the second buffer memory and the third output of the third group of outputs BOO, information outputs of the first register connected to receive information inputs-outputs of the first buffer memory and information inputs of the first block channel transmitters, information outputs which together with the information outputs of the second block channel transmitters are a group of outputs of the device to connect to the data bus of the computer, the information outputs of the second register connected to receive information inputs-the outputs of the second buffer memory and information inputs of the second block channel transmitters, the control input of the first and second blocks channel transmitters connected to the first output of the first group of outputs BO, the second control inputs of the first and second blocks of the buffer memory is connected to the second output of the first group of outputs BOO, the third output of the first group of outputs BOO is connected to the enable input data output of the third buffer register, the information outputs of which are combined with the information outputs of Pervov the buffer register and connected to information inputs-outputs of the first and second blocks of the buffer memory, the information inputs of the third buffer register connected to the information output row count, the first input of which is connected to the sixth output of the second group of outputs BOO, and the second counter input lines connected to the fifth output of the second group of outputs BO, the first output of the second group of outputs BOO is connected to a second input of the counter is the length of the string, the first input of which is connected with the second output of the second group of outputs BOO, and information outputs of the counter is the length of the string is connected to the second group of inputs of the digital comparator, the output of which is connected with the eighth input BU, the third output of the second group of outputs BOO is connected to the enable input data output of the first buffer register, the fourth output of the second group of outputs BOO connected to the first input of the counter of the first row, the outputs of which are connected to the first group of inputs of the adder, to the information input of the first buffer register and the first group of inputs of the digital comparator, the first, second and third outputs of the fourth group of outputs BOO connected respectively with the first, second and third inputs of the address counter whose outputs are connected to the address inputs of the first and second blocks of the buffer memory and the second group of inputs of the adder, the outputs of which are connected to information inputs of the second buffer register, a control input which Saint is associated with the fourth output of the fourth group outputs BOO, information outputs of the second buffer register connected to information inputs of the address counter, the address lines of the ISA bus is connected with the first group of inputs of the unit for communication with a computer, the first, second and third outputs of which are connected respectively with the first, second and third inputs of the second group of inputs BOO, control lines on the ISA bus, namely RESET, AEN, T/C, IOR and OUTLETS connected respectively to the sixth, fifth, fourth, third and second inputs BOO, the sixth input BU also connected with the third input of the counter of the first row, and the fifth input BU is also associated with the first an input unit for communication with a computer, the first output BU connected to the control line DRQ ISA bus.

2. The device according to claim 1, characterized in that the control unit includes first, second and third counters, first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, fifteenth, sixteenth, seventeenth, eighteenth, nineteenth, twentieth and twenty-first elements are NOT, first, second, third, fourth and fifth elements, OR first, second, third, fourth, fifth, sixth, seventh, eighth and ninth triggers, the first, second, third, the fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, twelfth and thirteenth elements AND IS NOT, first, second, third, fourth, fifth, sixth, who adimai and eighth elements And, an AND-OR-NOT, and the input From the first counter is combined with the reset input of the sixth trigger and is the seventh sign-BOO, and the entrance SR first counter is combined with the input set of the seventh trigger on inputs SER, D, the SET of the first and second counters, inputs D and the SET of the third counter filed logical unit, the output 2 of the first counter is combined with the input of the eighth element and connected to the first input of the seventh element AND-NOT output of the eighth element is NOT connected to the input of the twelfth element, the output of which is connected to the input of the fourteenth element whose the output is connected to the second input of the seventh element AND whose output is the second output of the third group of outputs BOO and connected to the input of the installation of the sixth trigger whose direct output connected to the first inputs of the second and third elements And the second input of the second element And is connected to the output of the nineteenth element, whose input is combined with the second input of the third element And connected to the output 3 of the first counter, the output of the second element And connected to the first input of the twelfth element AND-NOT output of the third element And connected to the first input of the thirteenth element AND IS NOT and to the entrance of the twentieth element, the output of which is connected to the input setup ninth trigger, a second input of the sixth element And a second input of the seventh e is amenta And direct access of the ninth trigger connected to the fourth input of the sixth element And the first input of the seventh element And the input of the first element is NOT United with the first input of the third element AND IS NOT and is the first entry of the first group of inputs BOO, the output of the first element is NOT connected to the input of the fourth element, the output of which is connected to the input of the ninth element, whose output is connected to a second input of the third element AND IS NOT, the output of which is combined with the reset inputs of the SR of the second and third counters, and is connected to the input of the tenth element, the output of which is connected to a second input of the eleventh element, And-NO, the output ST of the second counter is connected to the input of the SERIES of the third counter, the output 0 of which together with the output 3 of the second counter are respectively the second and first inputs of the second element AND whose output is connected to the input of the installation of the fourth flip-flop, a direct output of which is input to the fifteenth element, the first input of the eighth element AND the fourth input of the seventh element And a second input of the tenth element, AND IS NOT, a second input of the eighth element, And the fourth input of the first element And element AND-OR-NOT, a second input of the third element And element And-OR-NOT, exit the fifteenth item is NOT a sign of the sixteenth element, the output of which is connected to the input vosemnadcati what about the element, whose output is connected to a second input of the eighth element AND whose output is connected to the input of the installation eighth trigger reset input which is combined with the reset input of the ninth trigger and synchronization inputs of the second and third counters, the first inputs of the fifth and eighth elements And is the fourth sign of the first group of inputs BOO, direct eighth trigger connected to the third input of the sixth element And to the second input of the third element OR the output of which is connected to the fourth input of the twelfth element AND-NOT, with the fourth input of the thirteenth element AND HE and the second input of the first element And element And-OR-NOT, the inverted output of the eighth trigger connected to the first input of the tenth element, AND IS NOT, the input of the fifth element is the sixth sign of the first group of inputs BOO and combined with the first input of the sixth element AND the third input of the third element And element AND-OR-NOT, the first input of the fourth element And with the reset input of the seventh trigger, direct the output of which is connected to the third input of the seventh element And to the third input of the twelfth element AND-NOT and a third input of the thirteenth element AND IS NOT, the output of the fifth element is NOT connected with entrance eleventh element, the output of which is input to the thirteenth element, whose output is the second input of the sixth element, And-N is, the output is the first output of the second group of outputs BO, the first input of the first element OR combined with the input of the third element and is the sixth sign of BU, the second input of the first element OR combined with the input of the seventh element and is the fourth sign-BOO, the output of the first element OR connected to the reset input of the first trigger, set input connected to the output of the second element and the third output of the first group of outputs BOO, direct the first flip-flop connected to the first input of the fourth element AND-NOT, the second input is combined with the first input of the fifth element AND IS NOT, with the second input of the fifth element And is the fifth sign of the first group of inputs BOO, the output of the fourth element AND is NOT a reset input of the fifth trigger, the inverse output of the first flip-flop connected to the second input of the fifth element AND whose output is the fifth output of the second group of outputs BOO, as well as the input set of the fifth trigger, direct the output of which is connected to the third input of the tenth element AND-NOT to the second input of the twelfth element AND-NOT to the second input of the thirteenth element AND NOT to a third input of the eighth element And to the first input of the eleventh element AND the third input of the first element And element AND-OR-NOT, the first input of the second element And element AND-OR-NOT,the first input of the third element And element AND-OR-NOT, inverted output of the fifth trigger connected to the first input of the fourth element And element AND-OR-NOT and to the first input of the ninth element AND-NOT output of the third element is NOT connected to the first input of the first element AND the second input is a second input BU and combined with the second input of the second OR element, and the output is the reset input of the second trigger, the input set which is connected to the output of the sixth element, the inverted output of the second trigger connected to the first input of the second element, OR whose output is the input set of the third trigger a reset input which is the output the seventh item is NOT a direct output of the third trigger is connected to the first input of the first element And the third input connected to the output of the seventeenth element, the output of the first element And connected to the second input of the fourth element And element AND-OR-NOT, to the second input of the ninth item AND IS NOT and to the first input of the fourth element OR the second input is combined with the input of the second element and the first input of the second group of inputs BOO, the third input of the fourth element OR combined with the entrance of the twenty-first element and the second input of the second group of inputs BOO, outputs the fifth and sixth elements are respectively first and second inputs of the fifth element OR the output of cat is, which is connected to the first input of the first element And element AND-OR-NOT and is the fourth output of the second group of outputs BOO, additionally, the entrance of the seventeenth item is NOT a third input BU, the second input of the first element And is the fifth input BU, the first input of the third element, OR is the eighth sign-BOO, the reset input of the fourth trigger is the second input of the first group of inputs BOO, the first input of the sixth element And the third input of the first group of inputs BOO, the second input of the second element And element AND-OR-NOT is the seventh sign of the first group of inputs BOO, the input of the sixth element is the third entry of the second group of inputs BOO, direct the output of the second trigger is the first release of BOO, the output of the fourth element OR and the output of the ninth element AND are respectively the first and second outputs of the first group of outputs BOO, the output of the seventh element, And the output of the twenty-first element and the output of the eighth element And are respectively the second, third and sixth outputs of the second group of outputs BOO, the output of the twelfth element AND-NOT and the output of the thirteenth element AND are respectively the first and third outputs of the third group of outputs BOO, the output of the tenth element AND-NOT output of the eleventh element AND-NOT gate output AND-OR-NOT and the output of the fourth element And are respectively the first, the second, third and fourth outputs of the fourth group of outputs BOO.