Device for controlling information display in remote education system

FIELD: computers.

SUBSTANCE: device has base address selector, registers, delay elements, elements of OR groups, OR elements, memory block, reverse counter, comparator.

EFFECT: higher speed of operation.

3 dwg

 

The invention relates to computing, and in particular to devices for controlling the presentation of information in distance learning systems.

The known device that could be used to solve the task (1, 2).

The first known device contains a computer unit connected with input data and logical processing, the outputs of which are connected to the memory unit, the display unit connected to the computing unit and to the decision block (1).

A significant disadvantage of this device is its low performance, due to the fact that for filing personnel with training information you need every time you re-access the data they need to make their re-search.

Known and other device containing memory blocks, registers the first and second groups, triggers the one-shot, group elements AND, OR, elements of the delay and pulse shapers (2).

The last of the above technical solutions closest to being described.

Its disadvantage is the limited performance due to the loss of time on the formation of address documents - representatives of subject areas, which need to be presented to the learner.

The latter circumstance on the agreed topics what constructive performance of this device does not provide for its use as a client of the workplace in the distance learning system.

The purpose of the invention is improving the performance of the device by reducing the time spent on the search and formation of the addresses of the documents, the content of which should be presented to the learner.

This objective is achieved in that the device containing the first register, the information input of which is the first information input device, and the clock input of the first synchronizing input of the second and third registers, information inputs which are connected to the output of the memory block, and outputs connected to one input elements And the first and second groups, respectively, whose outputs are connected to inputs of the respective elements OR groups whose outputs are connected to the address input of the memory block, the first delay element, the input of which is connected with the first synchronizing input of the second delay element, the output of which is connected to the clock the inputs of the second and third registers with one input of the first element OR the first element And one input of which is the first Manager of the input device, and the output connected to another input of the first element, OR trigger, a single entrance to the showing is the second managing input device, installation input is connected to the output of the first OR element and a single output connected to one input of the second element And to the other inputs of elements And the second group, the third delay element, the input of which is connected to the second control input device and an output connected to another input of the second item, and the item OR the first and the second input of which is connected to the outputs of the first and second elements And put the selector base address, an information input connected to the output of the first register, a clock input connected to the output of the first delay element, an information input connected to the third inputs of the respective elements OR group, and the clock output selector base address is connected to the third input of the OR element, the output of which is connected to the input of the second delay element and to the input of the read memory block, the output of which is an information output device, a reversible counter, summing input connected to the output of the first element OR subtractive input connected to the output of the second element, And installation input is connected to the output of the first delay element, and a comparator, one data input of which is connected to the output of the reversible counter, the other information is the second information input device, direct access to the narator connected with the control input selector base address, and the inverted output is connected to the other input elements And the first group and to the other inputs of the first and second elements And the inverse of the trigger output is connected to other inputs of elements And the first group.

The invention is illustrated by drawings, where figure 1 shows the block diagram of the device, figure 2 shows an example of a specific structural embodiment of the selector base address, and figure 3 presents the structure stored in the memory block of the document.

The device (1) contains the first 1 memory block, the first 2, second 3 and third 4 registers, reversible counter 5, a comparator 6, the trigger 7, the first 8 and second 9 elements And the first 10 and second 11 group elements And the first 12 and second 13 element OR a group 14 element, OR the first 15, second 16, 17 third delay elements, the selector base address 18.

The selector base address (figure 2) contains the decoder 19, the memory block 20, made in the form of a persistent storage device, the register 21, the elements 22-24 And group elements 25 And the elements 26, 27 delay. In addition, the drawing shows the clock input 28, the information input 29, the control input 30, and an information output 31 and the clock output 32.

Figure 1 also shows the first 33 and second 34 information input device, synchronizing 35 input device, the first 36 and second 37 operated the existing input device and information 38 the output device.

All nodes and elements of the device are made on the standard of potentially switching elements.

The device operates as follows.

As in the known device, the working place of a student consists of a terminal having a screen for displaying the content of the sections of the target subject, and the keyboard is divided into standard (keyboard, personal computer) and functional, which is a set of key shapers.

On the display screen of the workplace learner sequence sections of the studied topics. However, unlike the prototype of the described device operates in the system of distance learning mode client - server, where a server to a client workstation is given only the code of theme to explore. All study subjects in the memory block 1 is presented in the form of the structure shown in figure 3, where the first K1-bits represent the contents of the first partition of the target subject, the second K2-bits contain the address of the previous section on this topic, and others K3-bits contain the address of the next section on this topic (3).

With the beginning of the next cycle from the server to the register 2 write the code of theme, which is presented to study the learner. For this purpose, the input device 33, the server returns the ID numbers of the topics that the synchronization server, p is stepping onto the entrance 35, entered in the register 2, whence it is supplied to the information input of the selector base address 18.

Code topic number is decoded by the decoder 19 and on one of its outputs is formed a high potential, opening one of the corresponding elements 22-24 And. in Parallel, the clock signal server input 35 is delayed by the delay element 15 (at the time of operation of the decoder 19) and from the output of the delay element 15 receives, firstly, the installation log reversible counter 6, resetting it to its original state.

Secondly, the same pulse received at the input 28 of the selector base address and next, by clicking open on the second input of one of the elements 22-24 And is fed to the input of the read fixed memory permanent storage device 20. In the fixed cell of the memory block stores the base address of the first partition of the topics chosen for study. The contents of the fixed cells of the memory unit 2 is read to the input register 21, where it is recorded synchronizing pulse received from the output of the delay element 26 to the clock input of the register 21.

The code base address from the output of the register 21 is supplied to one inputs of the elements 25 And that for other inputs is determined by the capacity of the direct output of the comparator 6, the information input of which receives the code is the output of the reversible counter 6 and the code, the corresponding “zero” input 34.

Given the fact that the reversible counter 6 at the moment is set to zero, the comparator 6 will record the fact of equality codes at its inputs the issuance of a high potential on its direct output and a low potential at the inverted output. High capacity direct output of the comparator is fed to the input 30 of the selector 18 of the base address and then open the items OR 25, thereby connecting the output of the register 21 through the output 31 of the selector 18 to the address input unit 1 memory.

In parallel, the pulse from the output element 27 delay, the detainee at the time of connection of the output of the register 21 to the address input unit 1 memory through the output 32 of the selector 18 and the element 13 is fed to the input of the read block 1 of memory. In the result, the contents of the base address is read on the display screen through the outlet 38 and informational inputs of the registers 3 and 4 in exact accordance with the data structure (figure 3).

The same pulse reading detained element 16 delay time read data from block 1, register 3 is entered address code of the previous section, and in the register 4 - address code subsequent section. Given the fact that no previous sections have not been, when reading the base address is used and as previous addresses during the initial reading bazo the CSOs address.

Simultaneously, the pulse from the output of the delay element 16 through the element 12 OR arrives at the summing input of the reversible counter and changes the code of the counter, making it different from ″zero″. This fact will record the comparator 6, which, giving a low potential for direct access and then through the entrance 30 of the selector 18 to the inputs of the elements 25 And groups, will block the connection of the output of the register 21 to the address input unit 1 memory. At the same time, a high potential with inverted output of the comparator 6 opens items 8,9 And group 10 elements, And connecting the output of the register 3 through the elements 10 and groups, And the elements 14 OR group to the address input unit 1 memory. Thus, the address input unit 1, the memory is given the address of the next section of the target subject.

With the readiness of a student to study in the next section topics he presses “Next” and input 36 receives the impulse, which, passing through the element 8 And, first, through the element 12 OR comes as a summing input of reversible counter, increasing his testimony, and the installation log trigger 7, confirming its initial condition, in which a high potential with its inverted output opens one input element group 10 I.

Secondly, through the element 13 OR the same pulse received at the input of the reading unit 1, the memory and the content of the next section is udaetsya at exit 38, and new values of the previous and the next address is inserted into the corresponding registers 8 and 9.

If in the process, the next section will need to return to the previous section of this topic, the learner presses ″Previous″. In this case, the input 37 pulse appears, which sets the trigger 7 in one state, moving in that last low potential with inverted output closes the elements 10 And groups, blocking the ability to connect the next address register 3 address input block.

At the same time, a high potential with a single exit will be open elements 11 And of the group and element 9 And. as a result, the output of the register 4 with the address of the previous section through the elements 11 And the groups and items 14 OR group connected to an address input unit 1 memory.

In parallel, the pulse input 37 is delayed by a time trigger 7 delay elements 17 and flows through the element 9 And as to the subtractive input of the reversible counter 5, and through the element 13 OR the input of the reading unit 1, a memory, reading the contents of the previous theme.

Thus, unlike the prototype in the process of learning a sequence of different topics in all subject areas the learner immediately gets access to the required time is Elam and understandable without any time spent on the search address find relevant topics.

Sources of information

1. The EPO patent (EP) No. 0505651, CL G 06 F 13/40, 13/38, 1992.

2. The description of the author's certificate No. 1474680, CL G 06 F 15/40, 1989 (prototype).

3. Romanov A.N. and other distance learning technologies - M.: UNITY-DANA, 2000. - 303 S.

Device to control the presentation of information in the system of distance learning, containing the first register, the information input of which is the first information input device, and the clock input of the first synchronizing input of the second and third registers, information inputs which are connected to the output of the memory block, and outputs connected to one input elements And the first and second groups, respectively, whose outputs are connected to inputs of the respective elements OR groups whose outputs are connected to the address input of the memory block, the first delay element, the input of which is connected with the first synchronizing input of the second delay element, the output of which is connected with the clock inputs of the second and third registers, with one input of the first element OR the first element And one input of which is the first Manager of the input device, and the output connected to another input of the first element, OR trigger, a single entrance which is the second managing input devices, installation input is connected to o the house of the first element OR and a single output connected to one input of the second element And to the other inputs of elements And the second group, the third delay element, the input of which is connected to the second control input device and an output connected to another input of the second item, and the item OR the first and the second input of which is connected to the outputs of the first and second elements, And characterized in that it contains a selector base address, an information input connected to the output of the first register, a clock input connected to the output of the first delay element, the information outputs of the selector base address is connected to the third inputs of the respective elements OR group, and the clock output selector base address is connected to the third input of the OR element, the output of which is connected to the input of the second delay element and to the input of the read memory block, the output of which is an information output device, a reversible counter, summing input connected to the output of the first element OR subtractive input connected to the output of the second element, And installation input is connected to the output of the first delay element, and a comparator, one data input of which is connected to the output of the reversible counter, the other information is the second information input device, direct the computer is atora connected with the control input selector base address, and the inverted output is connected to the other input elements And the first group and to the other inputs of the first and second elements And the inverse of the trigger output is connected to other inputs of elements And the first group.



 

Same patents:

The invention relates to portable devices, namely, miniature or pocket computers, mobile phones, communication etc

The invention relates to portable devices, namely, miniature or pocket computers, mobile phones, communication etc

The invention relates to control apparatus (LA), as well as to indicators, displaying information about the flight parameters and LA

The invention relates to input information into the computer

The invention relates to the field of computer engineering and can be used to control your computer

The invention relates to a processing device discretized input image data to enlarge the picture in the horizontal direction

The invention relates to a processing device discretized input image data to enlarge the picture in the horizontal direction

The invention relates to electronics and can be used to display values of various system parameters

The invention relates to a device for displaying graphical information

The invention relates to an indicator device for receiving and displaying digital data, and the method of implementation of orders using the indicator device

The invention relates to electronic engineering

The invention relates to information display

The invention relates to automatic control and computer engineering

The invention relates to automatic control and computer engineering

The invention relates to measuring technique and can be used in control systems of objects with continuous multivariable technological processes in the energy, chemical, metallurgical and other industries

The invention relates to automatic control and computer engineering and can be used to build systems display alphanumeric and alphanumeric information mosaic

Display // 2015536

FIELD: measuring technologies.

SUBSTANCE: method includes setting tolerance for controlled parameter, measuring physical value, associated with said controlled parameter, with numeric characteristic of its value, then measured value is compared to its tolerated values (tolerances for controlled parameter), and decision concerning level of match of measurement results to tolerances for parameter is taken, when determining tolerance for controlled parameter an affiliation function is set for phrase "parameter on basis of measurements in tolerance", and during taking of decision trustworthiness of phrase is evaluated, expressed in non-precise measure, as value of affiliation function, matching value of measured parameter.

EFFECT: higher trustworthiness.

2 dwg

FIELD: computers.

SUBSTANCE: device has control trigger, random pulse generators, block for forming program of functioning of modeled multimode system, working modes and technological mode blocks, operation time counters, random pulses generators, OR block, orders counters.

EFFECT: broader functional capabilities.

3 dwg

FIELD: computers.

SUBSTANCE: system has nine registers, four address selectors, triggers, AND elements, OR elements and delay elements.

EFFECT: higher speed.

8 dwg

Up!