Vertical structure of semiconductor device and method of formation thereof

FIELD: physics.

SUBSTANCE: vertical structure of semiconductor device includes substrate forming essentially horizontal plane, gate electrode with vertical side wall and vertically protruding from substrate, washer attached from one side from vertical side wall, semiconductor nanotube between gate electrode and washer and essentially vertically protruding between its opposite first and second ends, gate dielectric on vertical side wall between nanotube and gate electrode, source electrically connected with first end of nanotube, and drain electrically connected with second end of nanotube. Each nanotube is grown by chemical vapour deposition accelerated with catalyst platform mounted in foundation of elongated passage formed between washer and gate electrode.

EFFECT: allows for application of technology compatible to die mass production technology.

37 cl, 13 dwg

The invention relates to the manufacture of semiconductor devices (devices), more precisely to the field transistor with a vertical channel, in which the role of the channel region play a semiconductor nanotubes, and methods for producing such field-effect transistors with a vertical channel.

Traditional field-effect transistors are conventional known devices, which are widely used as a basic building block of complex circuitry crystals integrated circuits ("chips"). Along with other passive components such as resistors and capacitors, in the composition of the single-chip integrated circuit can come from many thousands to millions of field-effect transistors, which are connected to each other by conductive paths. The principle of field-effect transistors based on the change of resistivity of the channel in the channel region that separates the source and drain. The flow of charge carriers, which move along the channel from the source to the drain is proportional to the change in the electrical resistivity. After the channel conductance of the n-channel field-effect transistors answer the electrons, and the p-channel field-effect transistors for conduction in the channel responsible e-holes. The output current of the FET varies, affecting the voltage at the gate electrode is capacitively coupled, which is located above a channel region between source and drain. The gate electrode is electrically insulated from the channel region of the thin insulating layer (dielectric) shutter. A slight change of gate voltage can cause a large fluctuation of current flow from the source to the drain.

Field-effect transistors can be divided into field-effect transistors with horizontal and vertical channels. The field-effect transistors with a horizontal channel flow of charge carriers moving from the source to the drain in the direction parallel to the horizontal plane of the substrate on which they are formed. The field-effect transistors with vertical channel the flow of charge carriers moving from the source to the drain in the direction vertical to the horizontal plane of the substrate on which they are formed. Since the channel length of field effect transistors with vertical channel does not depend on the size of the smallest element, distinguishable by the equipment and methods of lithography, field-effect transistors with a vertical channel can be channels of smaller length than field-effect transistors with a horizontal channel. Therefore, field-effect transistors with a vertical channel may have a higher switching speed and higher maximum power than field-effect transistors with a horizontal channel.

In the US 2003/132461 described an example of a vertical field-effect transistor based on two nanoelements, electrically connected to the source and the drain, single gate across the opening between the two nanoelements. Nanoelement can have a conductivity controlled by a shutter, so that nanoelement form the channel region of the transistor. However, this design is not suitable for mass production, because there are no guarantees of vertical growth nanoelements.

Thus, there is a need for field-effect transistors with a vertical channel, which channel region is used, one or more semiconductor carbon nanotubes and which are compatible with the technologies of mass production of crystals of integrated circuits.

In the proposed invention the vertical structure of the semiconductor device including a substrate, forming a predominantly horizontal plane, a gate electrode that protrudes vertically from the substrate and has a vertical side wall, and a gasket located on the side of the vertical side wall. Between the gate electrode and the strip is passing preemptive what about in the vertical direction of the semiconductor nanotube with opposite first and second ends. On the vertical side wall between the carbon nanotube and the gate electrode is a gate dielectric. The first end of semiconducting nanotubes is electrically connected to the source, and the opposite end of semiconducting nanotubes is electrically connected to drain.

According to another features of the invention, a method for manufacturing the vertical structure of a semiconductor device in which on a substrate to form the catalyst pad and the gate electrode near the catalytic site. On the vertical side wall of the gate electrode in position over the catalyst pad is formed from a first strip and then forming a second spacer on the first spacer. The first spacer is removed to create a passage or open space, limited by the second spacer and the gate electrode, and the passage has an open outlet at one end and at its opposite end is the catalyst space. On the vertical side wall of the gate electrode is applied to the gate dielectric. On catalyst site synthesize semiconducting nanotube, which is predominantly vertically from the catalyst site to the free end near the open exit of the passage.

In a preferred embodiment of the invention the growth of nanotubes is limited V. the CSOs certain vertical direction within open space or passage with a high width to length ratio, formed by the spacer adjacent to the gate electrode. Due to this solved the traditional problem Omni-directional growth of nanotubes. The gasket may be provided between, allowing you to efficiently and effectively enter into the passage near the interface of the catalytic material and each growing nanotubes reagent or reagents required for the growth of carbon nanotubes. The length of the channel region between source and drain is set to the vertical dimension or thickness of the gate electrode without the limitations imposed by conventional lithography used in the manufacture of semiconductor devices. Due to this, the length of the channel region may correspond to a size smaller items than items that are produced by standard methods of lithography and etching.

The attached drawings, which in the present description reference is made, on his part, illustrate embodiments of the invention and in combination with the above General description and the following detailed description of the variants of its implementation serve to explain the principles of the invention, namely:

figa is a top view of part of the substrate,

figb - cross-section generally along lines 1B-1B in figa,

figa - top view at a subsequent stage of manufacture, a similar view of figa,

figb - poperechnoe section generally along lines 2B-2B in figa,

figa - top view at a subsequent stage of manufacture, a similar view of figa,

figb - cross-section generally along lines 3B-3B in figa,

figa - top view at a subsequent stage of manufacture, a similar view of figa,

figb - cross-section generally along lines 4B-4B in figa,

figa - top view at a subsequent stage of manufacture, a similar view of figa,

figb - cross-section generally along lines 5B-5B in figa,

figa - top view at a subsequent stage of manufacture, a similar view of figa,

figb - cross-section generally along lines 6B-6B in figa,

figa - top view at a subsequent stage of manufacture, a similar view of figa,

figb - cross-section generally along lines 7B-7B in figa,

figa - top view at a subsequent stage of manufacture, a similar view of figa,

figb - cross-section generally along lines 8B-8B in figa,

figa - top view at a subsequent stage of manufacture, a similar view of figa,

figb - cross-section generally along lines 9B-9B in figa,

figa - top view at a subsequent stage of manufacture, a similar view of figa,

figb - cross-section generally along lines 10B-10B on figa,

figa - top view at a subsequent stage of manufacture, a similar view of figa,

figb - cross-section in Celano lines 11B-11B in figa,

figa - top view at a subsequent stage of manufacture, a similar view of figa,

figb - cross-section generally along lines 12B-12B on figa,

figa - top view at a subsequent stage of manufacture, a similar view of figa, and

figb - cross-section generally along lines 13B-13B in figa.

The preferred embodiment of the invention relates to field-effect transistors with a vertical channel, in which a semiconductor material channel region are carbon nanotubes, forming a selective conductive channel between source and drain. In accordance with the present invention, carbon nanotubes are grown in a limited vertical open space or passage with obstruction of Omni-directional growth. Due to this, the carbon nanotubes are oriented predominantly vertically and are located in the desired position near the gate electrode, which serves voltage to regulate the current flowing from the source to the drain. The length of the channel region between source and drain is set by the thickness of the gate electrode, which is mostly equal to the length of the nanotube and does not depend on lithography. To increase the growth rate of nanotubes create an additional path of movement for gaseous or vaporous reactants to the catalytic mA is erial, located in the lower part of the passage for the growth of nanotubes. Due to this, the only way to catalytic material passes from the entrance to the lower part of the elongated passage (with a high ratio of width to length) in a direction which is not vertical.

On figa and 1B shows the plot of the substrate 10 covered with a planar insulating layer 12 with high electrical resistivity relative to the substrate 10. The substrate 10 may be made of any material, used as the semiconductor substrate, including, without limitation, silicon (Si) and gallium arsenide (GaAs)which can be formed an insulating layer, such as layer 12. Insulating layer 12 may consist of, for example, of silicon dioxide (SiO₂) or silicon nitride (Si₃N₄).

On the insulating layer 12 by a method of deposition of a continuous layer of catalytic material and using standard lithography and selective etching to form the catalyst (pin) pad 14 of the catalytic material capable of supporting the growth of carbon nanotruck. A continuous layer of catalytic material is applied to form a catalyst pad 14 may be deposited by any conventional deposition method, including, without limitation, chemical deposition from the vapor (gas) phase by thermal spread out the I/thermolysis of metal-containing source material, such as halide compounds and CARBONYLS of metals, metallization deposition and physical vapor deposition. The catalytic material in the catalyst pad 14 may be any material capable of serving as a center of crystallization and to support the growth of carbon nanotubes after exposure to appropriate reagents under the reaction conditions conducive to the growth of nanotubes. For example, applicable catalytic materials include without limitation, iron, platinum, Nickel, cobalt, and compounds such as silicon compounds with each of the listed metals.

Insulating layer 12 may be omitted, and alternatively, the substrate 10 may consist of structures with thin slit insulation or structures with a local oxidation of silicon, electrically insulated from adjacent portions of the substrate 10 plot shown in figa, 1B, which may also include described in the invention additional structures of devices or other structures of the device. In this alternative embodiment, the catalyst pad 14 is formed or deposited on the area of the substrate 10, an isolated using structures with a thin slit insulation or structures with a local oxidation of silicon, a common method in the form of grooves in the form of strips. On the insulating layer 12 may be provided megastorebrittany sites 14, which corresponds to the technology of mass production.

Fig 2A and 2B shows a thin insulating layer 16, which is conformally deposited over the insulating layer 12 and the catalyst pad 14. An insulating layer 16 formed of a dielectric material such as SiO₂or Si₃N₄that can be deposited by chemical vapor deposition from the vapor phase by thermal decomposition/thermolysis silicon-containing source material or by chemical vapor deposition from the vapor phase under reduced pressure, or alternatively, in the case of using the oxide grown by high-temperature oxidation. On the insulating layer 16 covering the catalyst pad 14, to form the contact column 18 of conductive material. Unprotected (open) the top surface of the contact bar 18 is applied to the photomask (mask) 20 of the solid insulating material.

Bump 18 and the photomask 20, covering the column 18, is formed using standard lithography and etching, in which the insulating layer 16 by chemical vapor deposition from the vapor phase under reduced pressure at first precipitated solid layer of conductive material, such as signalisierung polycrystalline silicon (polysilicon), and then precipitated in a solid layer of conductive by materially insulating material, such as SiO₂or, more accurately, SiO₂based tetraethylorthosilicate. The insulating material is applied in such a way as to leave open unmasked areas of a continuous layer of conductive material and the masked areas, combined with the catalyst pad 14, as explained below, and then etched insulating material, for example, by the method of reactive ion etching, which selectively acts on the insulating material of the photomask 20, to remove the conductive material on the unmasked areas.

Used in the description of terms such as "vertical", "horizontal", etc. are not limiting, but merely serve to create a reference system. Used in the description, the term "horizontal" refers to a plane that is parallel to the conventional plane or surface of the substrate 10 regardless of the orientation. The term "vertical" means the direction perpendicular to the horizontal direction according to the definition above. Terms such as "on", "above", "below", "side" (for "side wall"), "above", "below", "top"," bottom" and "below" refer to the horizontal plane. Means that can be used in various other systems of reference is beyond the scope of invention.

On figa and 3B shows the gasket is temporary barrier material, formed in the vertical side wall 21 of the contact column 18 by conformal deposition of a thin film barrier material and the anisotropic etching, for example, by the method of reactive ion etching, which selectively acts on the material of the insulating layer 12 and the photomask 20. Dividing the material forming the gasket 22 may be, for example, SiO₂or Si₃N₄. The gasket 22 is consumed in the sense that it completely removed during subsequent processing. In one variant of the invention, the insulating layer 12 and the photomask 20 is formed of SiO₂while the seal 22 is formed of Si₃N₄therefore , reactive ion etching, which removes the gasket 22 that selectively acts on the material of the insulating layer 12 and the photomask 20. The gasket 22 is in a horizontal direction beyond the side wall 21.

On figa and 4B shows that the catalyst pad 14 is reduced due to the clipping region boundary areas below the contact column 18. To do this, remove the parts of the insulating layer 16, unmasked contact column 18 and the gasket 22, the etching method, which can be a method of etching that is different from the method of forming the strip 22, or method of continuous etching, in the ode which conditions the etching when etching the insulating layer 16 change accordingly. Then, in order to reduce the area of the unprotected surface of the catalyst pad 14 is removed plots catalyst pad 14, unmasked contact column 18 and the gasket 22, the etching method, which can also be a method of etching that is different from the methods of removing sections of the insulation layer 16, or a method of continuous etching in which the etching conditions in the etching of the catalytic material change accordingly. Catalyst pad 14 is covered with a layer 25 of insulating material, which is not part of the remote insulating layer 16.

On figa and 5B shows that the strip 22 is removed from the side wall 21 of the contact column 18 by any wet or dry etch that selectively acts on the material of the substrate 10, the photomask 20 and the catalyst pad 14. On the substrate 10 by a conformal deposition method, chemical vapour deposition or chemical vapour deposition under reduced pressure is applied by a continuous layer 26 from the corresponding isolating material, such as SiO₂or germanium (Ge). Of the solid areas of the layer 26 covering the side wall 21 of the contact column 18, form the strip 30, as explained below, the thickness of which is approximately equal to the thickness of the strip 22.

On figa and 6B p is shown, that same vertical sections of a continuous layer 26, the photomask 20, the contact bar 18 and the catalyst pad 14 are removed using standard lithography and selective etching to separate the contact column 18 by the multitude of electrodes 28 of the shutter. For this purpose, a continuous layer 26 is applied resisty layer (not shown)capable of transmitting structure of the latent image and to convert the structure of the latent image in the structure of the final image with disguised plots in the form of parallel strips, covering a continuous layer 26 in the places of the future location of the electrodes 28 of the shutter. Upon completion of the etching to expose the areas of the insulating layer 12 between the electrodes 28 of the shutter. The size of the electrodes 28 of the shutter is preferably equal or close to the minimum size of elements, distinct methods of lithography. Spacers 30 are structured plot of a continuous layer, passing vertically near the side wall 31 of each electrode 28 of the shutter over the location of the catalyst sites 14. Spacers 30 are consumed because of their completely removed during subsequent processing.

On figa and 7B shows a strip 32 of a suitable permanent separation material, such as Si₃N₄formed in the side wall 31 of each e is of ctrode 28 of the shutter. The parts of the strip 32 are superimposed on each other and cover each of the strips 30. The material strip 32 is constant, as opposed to the strip 30, the gasket 32 is included in the finished structure. The gasket 32 is formed by conformal deposition of a continuous layer of a permanent barrier material on a substrate 10 and an anisotropic etching of a continuous layer, for example, by the method of reactive ion etching, which selectively acts on the material of the insulating layer 12 and the photomask 20, resulting after etching the spacer 32 on each electrode 28 of the gate is the only remaining site of the continuous constant layer of isolating material. Permanent separation of the material strip 32 may be, for example, Si₃N₄or SiO₂if the material of the spacers 30 is Ge. The gasket 32 is separated from the side wall 31 of each electrode 28 of the gate spacers 30 that are located on two opposite sides over the side edges of the catalyst pad 14, and attach to the other two opposite sides of each electrode 28 of the shutter.

On figa and 8B shows that the spacers 30 on each electrode 28 of the shutter removed by the method of isotropic etching, selectively acting on the material of the photomask 20 and gasket 32. For example, if the strip 30 to perform the trading of Ge, and the strip 32 is made of Si₃N₄or SiO₂to remove the gasket 30 is applicable hydrogen peroxide (H2O₂water etching solution, which selectively acts on the photomask 20 and the gasket 32. For passing the strip 32 and the electrode 28 of the shutter used open spaces or passageways 34 created by isotropic etching in the space previously occupied by the spacers 30. Each of the passages 34 is in terms of the profile is basically rectangular in shape. Method isotropic etching also removes the remaining sections of the structured solid layer 26, to re-expose the insulating layer 12.

Plot layer 25, a naked due to the formation of the passages 34, is removed from the lateral edges of a catalyst pad 14 to expose or open the corresponding region 36 synthesis of nanotubes. Below each strip 32 has a gap 38, previously filled with the site of one of the strips 30, which is located near respective regions 36 synthesis of nanotubes and is held in the vertical direction between the gasket 32 and the insulating layer 12. Each passage 34 is held in the vertical direction from one of the catalyst pads 14 to the open exit 33, located near the photomask 20. Region 36 synthesis of nanotubes are lower vertically than the one corresponding to the open outputs 33.

As shown in figa and 9B, then the open areas of the side wall 31 of each electrode 28 of the bolt the same length with the passages 34 put a layer 40 of insulating material such as SiO₂providing electrical isolation of each electrode 28 of the shutter from the corresponding passage 34. A method of forming a layer 40 is chosen in such a way as to avoid coating outdoor material regions 36 synthesis of nanotubes or any other changes that may cause undesired growth of carbon nanotubes. For example, when forming layer 40 by the method of oxidation in the atmosphere of wet oxygen partial pressure of oxygen can be adjusted so that in the open areas of the side wall 31 has been the growth of SiO₂in areas 36 synthesis of nanotubes was not accompanied by the formation of oxide. The horizontal dimensions of each passage 34, reduced due to the presence of layer 40, sufficient for the vertical growth of carbon nanotubes, as described below, and in other respects, mainly defined by the size of the spacers 30.

On figa and 10B shows the beam or group of carbon nanotubes 42 in the passages 34, adjacent to the areas of the side wall 31 of each electrode 28 of the shutter, covered with a layer 40. Carbon nanotubes 42 are hollow cylindrically the tube, educated hexagonal ring structures of carbon atoms, and typically have a diameter of from about 0.5 nm to about 20 nm and the thickness of the side walls from about 5 nm to about 50 nm. It is assumed that the carbon nanotubes 42 have a certain distribution of heights or lengths, which measure between the front end or tip 43 and the rear end or base 47, opposite the tip 43 on top of one of the areas 36 synthesis of nanotubes. The distribution of the lengths of the carbon nanotubes 42 may be described by the average length and standard deviation. At least one of the carbon nanotubes 42 in each passage 34 is vertically above the horizontal plane bounded by the photomask 20, which covers each electrode 28 of the shutter.

Carbon nanotubes 42 takes place mainly in a vertical direction upward from the regions 36 synthesis of nanotubes and take a share of the volume of empty space within the passages 34 of each of the electrode 28 of the shutter. Each of the carbon nanotubes 42 is oriented perpendicular or at least predominantly perpendicular to the horizontal top surface of the respective regions 36 synthesis of nanotubes, because the presence of strip 32 limits the growth of carbon nanotubes 42. Despite the admitted minor QCD is onanie or skewed orientation within the passages 34, the gasket 32 prevents Omni-directional growth. For example, carbon nanotubes 42 may not grow parallel to the horizontal plane of the substrate 10.

Carbon nanotubes 42 grown using chemical vapour deposition or plasma-chemical deposition from the vapor phase using any applicable gaseous or vaporous carbon-containing reagent, including (without limitation) carbon monoxide (CO), ethylene (C₂H₄), methane (CH₄), acetylene (C₂H₄), a mixture of acetylene and ammonia (NH₃), a mixture of acetylene and nitrogen (N₂), a mixture of acetylene and hydrogen (H₂), xylene (SN₄(CH₄)₂) and a mixture of xylene and ferrocene (Fe(C₅H₅)₂in growth conditions that promote growth of carbon nanotubes on the catalyst material forming area 36 synthesis of nanotubes. To promote growth by chemical vapor deposition from the vapor phase, the substrate 10 is heated. At the initial stage of the flow of the reagent is moved in the lateral direction through each gap 38 and down through each passage 34 to the catalytic material forming area 36 synthesis of nanotubes. The reagent chemically reacts on the catalyst material forming area 36 synthesis of nanotubes, as a center of crystallization of carbon nanotubes 42. P the following vertical growth of carbon nanotubes 42 may occur from the base surface areas 36 synthesis of nanotubes or alternatively, free from the apex 43 of carbon nanotubes 42 opposite to the base 47. Due to the presence of gaps 38 increases the ability of the reagent to reach areas 36 synthesis of nanotubes, as if it wanted the reagent is moved only down through the passage 34, his flow would be significantly limited. Gaps 38 may not be used if the growth comes from the free top 43 or if there are no other restrictions on the flow of reagent.

Growing conditions by the method of chemical vapour deposition or plasma-chemical deposition from the vapor phase is chosen so that it is preferable to obtain the carbon nanotubes 42 with solid-state molecular structure. Alternatively, the carbon nanotubes 42 with solid-state molecular structure is preferably selected from a set of carbon nanotubes 42 immediately after cultivation, which includes nanotubes with metallic and semiconducting molecular structures, which, for example, affect a strong enough current to destroy the nanotubes 42 with metal molecular structure. In some embodiments of the invention in one or more passages 34 may be one semiconducting carbon nanotube 42. Paminophenol, nanotubes 42 may consist of another material, possessing a prohibited area and semiconductor properties.

On figa and 11B shows that the substrate 10 by a deposition method such as chemical vapor deposition under reduced pressure, a layer 44 of insulating material with relatively high electrical resistivity, such as borophosphosilicate glass. Layer 44 smoothly polished by the method of chemical-mechanical polishing or any other applicable method of alignment. In the polishing layer 44 may be removed to a sufficient depth in order to shorten some too long carbon nanotubes 42. Areas of the layer 44 can fill any free space between the individual carbon nanotubes 42. Areas of the layer 44 can also fill each of the gaps 38.

On figa and 12B shows that through the layer 44, the photomask 20, the electrode 28 of the shutter and the layer 25 are created using standard lithography and etching contact openings 46 which terminate at a depth of catalyst pad 14. In the contact window 46 precipitated insulating material and carry out its anisotropic etching to create an insulating spacers 48, which electrically isolate the electrode 28 of the shutter from the catalyst pad 14. Each electrode 28 of the shutter is Astelin the appropriate contact window 46 into two separate electrode 28a, 28b of the shutter. In the layer 44 and the photomask 20 using standard lithography and etching created the contact window 50 which terminate at a depth of electrodes 28a, 28b of the shutter. In the layer 44 using standard lithography and etching created the contact window 52, ending at the depth at which exposed the tip 43 at least one of the carbon nanotubes 42 located in each passage 34.

On figa and 13B shows that in the contact Windows 46, 50 and 52 created contacts 54, 56 and 58, respectively, which contact window 46, 50 and 52 are not necessarily covered by one or more barrier/enhance the adhesion layers (not shown), precipitated on the entire surface of the corresponding metal to fill the contact window, and then remove excess deposited layer of conductive material by any applicable method of alignment, such as chemical-mechanical polishing to create a paste. The tip 43 of at least one of the carbon nanotubes 42, located in the passage 34, located near each electrode 28a, 28b of the shutter, is in electrical contact, preferably ohmic contact with the corresponding contact 58. The top 43 of the contact of the carbon nanotubes 42 may be vertically entering into the internal structure of the corresponding pin 58, or to come into contact with the corresponding contact 58 nagrania. Carbon nanotubes 42 in each passage 34 is electrically connected, preferably amicucci, with catalyst pad 14. The contacts 54, 56 and 58 are electrically isolated from each other and made of any applicable conductive material, including, without limitation, aluminum (Al), copper (Cu), gold (Au), molybdenum (Mo), tantalum (TA), titanium (Ti) and tungsten (W). For the manufacture of patterns of interconnections (not shown), which connects the adjacent finished structure 60 of the device, apply finishing method.

Structure 60 of the device forms a field-effect transistor comprising one of the electrodes 28a, 28b of the shutter, gate dielectric formed by the layer 40, the source of the formed catalyst pad 14 and the contact 54, flow, formed by the corresponding contact 58, and the semiconductor channel region bounded by a length of at least one of the carbon nanotubes 42, passing in the vertical direction on the corresponding passage 34 between the catalyst pad 14 and the contact 58. Channel region formed by the carbon nanotubes are oriented predominantly vertically relative to the horizontal plane of the substrate 10. After the supply of electric voltage to the respective electrodes 28a, 28b of the shutter, creating a channel in the associated carbon nanotubes 42, the flow of charge carriers is sabiratelno moves through the carbon nanotubes 42 from the catalyst pad 14 to the contact 58. Each structure 60 device electrically connected with the other structures 60 and additional circuit components (not shown)which are placed on the substrate 10.

Although the present invention is illustrated in the example is described in detail various embodiments, they do not limit the scope of the invention. Specialist in the art will easily recognize additional benefits and possible improvements of the invention. Thus, the invention in its most General features is not limited to the disclosed and described in specific detail, the illustrated device and method, and illustrative examples. Accordingly, allowed any deviations from such detail is not beyond the scope of the proposed claims.

1. The vertical structure of the semiconductor device including a substrate, forming mainly horizontal plane, the gate electrode having a vertical side wall and protruding in a vertical direction from the substrate, the gasket side of the vertical side wall, a semiconductor nanotube located between the gate electrode and gasket and predominantly elongated in the vertical direction between its opposite first and second ends, the dielectric for the thief, located on a vertical side wall between the nanotube and the gate electrode, a source electrically associated with the first end of the nanotube, and a drain electrically connected with the second end of the nanotube.

2. The structure according to claim 1, in which the source contains a catalytic material for synthesis of semiconducting nanotubes by chemical vapor deposition from the vapor phase.

3. The structure according to claim 1, in which the flow contains a catalytic material for synthesis of semiconducting nanotubes by chemical vapor deposition from the vapor phase.

4. The structure according to claim 1, in which the gasket is separated from the substrate by a gap filled with an insulating material.

5. The structure according to claim 1, in which a semiconductor nanotube formed of ordered carbon atoms.

6. The structure according to claim 1, in which the gasket is separated from the vertical side wall of the passage.

7. The structure according to claim 6, in which the horizontal dimensions of the passage is sufficient for growing semiconducting nanotubes, and its vertical dimensions exceed the height or equal to the height of the vertical side wall of the gate electrode.

8. The structure according to claim 6, in which the passage has in the plan profile of the rectangular form.

9. The structure according to claim 6, in which the source comprises a catalytic material for synthesis of semiconductor nanotribology chemical vapour deposition, and when this source is located on the substrate vertically aligned with the passage.

10. The structure according to claim 9, in which the gasket is spaced vertically from the substrate to form a gap for receiving the reagent in the catalytic material source for synthesis of semiconducting nanotubes by chemical vapor deposition from the vapor phase.

11. Structure of claim 10, in which a gap for receiving the reagent filled with an insulating material after the production of semiconductor nanotubes by chemical vapor deposition from the vapor phase.

12. The structure according to claim 6, including a group of semiconductor nanotubes located between the gate electrode and the spacer, each of the semiconducting nanotubes group passes through the said passage in the vertical direction between opposite first and second ends.

13. The structure indicated in paragraph 12, in which the space inside passage not occupied by the semiconductor nanotubes filled with an insulating material.

14. The structure according to claim 1, including a group of semiconductor nanotubes, passing between the gate electrode and the spacer, each of the semiconducting nanotubes group passes through the said passage in the vertical direction between opposite first and second ends.

15. Structure 14, in which at least od is and semiconducting nanotubes mentioned group has a first end, electrically connected with the source, and a second end, electrically connected to drain.

16. Method of forming a vertical structure semiconductor device, which is formed on the catalyst substrate area of the catalytic material adjacent to the catalyst pad form the gate electrode, on the vertical side wall of the gate electrode in position on the catalyst platform forming the first spacer on the first spacer on the side of the vertical side wall form a second gasket, remove the first strip with the creation between the second spacer and the gate electrode of the passage with an open outlet at one end and catalyst platform at the opposite end, forming a gate dielectric on the vertical side wall of the gate electrode and synthesize on catalyst site semiconducting nanotube, which takes place mainly in the vertical direction from the catalyst site to the free end of the open area of the outlet passage.

17. The method according to clause 16, which when you remove the first strip is carried out by etching, selective with respect to the gate electrode, the second spacer and the substrate.

18. The method according to 17, in which the selective etching of the first spacer includes isotropic etching.

19. The method according to clause 16, which in form is the formation of the second spacers is carried out by isotropic etching.

20. The method according to clause 16, in which when forming the dielectric shutter carry out the oxidation of the side wall of the gate electrode.

21. The method according to clause 16, in which the first strip is separated from the substrate by a vertical gap, creating a flow passage in the direction of catalyst sites, and for the synthesis of semiconducting nanotubes send this created a gap for the passage of the stream, the reagent is able to react on the catalyst platform, ensuring the synthesis of semiconducting nanotubes.

22. The method according to item 21, in which the reagent is used as the carbonaceous reagent, and a semiconducting nanotube is a carbon nanotube.

23. The method according to item 21, in which, after the synthesis of semiconducting nanotubes, the gap fill insulating material.

24. The method according to clause 16, which in the synthesis of semiconducting nanotubes catalyst pad is exposed to the reagent under conditions conducive to the cultivation of semiconductor nanotubes.

25. The method according to paragraph 24, in which the first strip is separated from the substrate by a gap, creating a flow passage in the direction of catalyst sites, and for the synthesis of semiconducting nanotubes is directed through the gap reagent which chemically reacts on the catalyst platform with software synthesis technology is dikovoj nanotubes.

26. The method according to clause 16, in which after formation of the electrode gap and catalyst sites form a third spacer with the formation of the protected area catalyst sites, which it overlaps, and unprotected area, that it leaves open, and remove the unprotected area with decreasing surface area catalyst platform.

27. The method according to p, in which the destruction of unprotected site catalyst site through etching, selective with respect to the gate electrode and the substrate.

28. The method according to clause 16, which form the contact, electrically connected with the free end of the semiconducting nanotubes.

29. The method according to clause 16, in which a semiconductor nanotube is a carbon nanotube formed of ordered carbon atoms.

30. The method according to clause 16, in which a semiconductor nanotube forms a channel region of a field effect transistor with a channel, the current movement which regulate, by acting on the gate electrode controlling voltage.

31. The method according to clause 16, in which synthesize a group of semiconductor nanotubes located between the gate electrode and the spacer, each semiconductor nanotube from the group passes from the catalyst site to the free end zone of the open vyhodkami.

32. The method according to p, which opened the exit passage and the gate electrode is covered with a layer of insulating material and formed in the layer of insulating material contact, electrically connected with the free end of at least one of the semiconducting nanotubes of the specified group.

33. The method according to p, in which the semiconducting nanotubes are carbon nanotubes.

34. The method according to clause 16, in which the horizontal dimensions of the passage is sufficient for growing semiconducting nanotubes, and its vertical dimensions exceed the height or equal to the height of the vertical side wall of the gate electrode.

35. The method according to clause 34, in which the passage has in the plan profile of the rectangular form.

36. The method according to clause 34, in which catalyst the site is located on the substrate, vertically aligned with the passage.

37. The method according to p, in which the gasket is spaced from the substrate with formation of a gap for receiving the reactant to the catalyst site, ensuring the synthesis of semiconducting nanotubes by chemical vapor deposition from the vapor phase.