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Information input device

Information input device
IPC classes for russian patent Information input device (RU 2291476):
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FIELD: automatics and computer engineering; information input, which defines the external device, working with computer.

SUBSTANCE: device contains commutator, storage device, two counters, synchronizer, three gates. Address inputs of commutator and storage device are connected to each other and to byte outputs of counter, which continuously changes its state influenced by clock signal. Each counter state corresponds to the number of external device and to information written in storage device, which defines this external device. Address digit count of storage device is greater than commutator address digit count by one. That is, each external device has an identifier of two words, which is passed to computer during current query cycle.

EFFECT: increased transferred information quantity during current external devices query cycle.

2 cl, 3 dwg

 

The invention relates to automation and computing, specifically for input devices digital computing machines.

A device for entering information (USSR author's certificate No. 1536365, CL G 06 F 3/00 1988, published 15.01.90, bull. No. 2)containing buffer register, the switch decoder, counter, block synchronization, delay element, block compare block of memory. The device is used to enter information about the state of a bistable sensors. In the polling loop in the memory block are recorded addresses of the sensors that have changed their state. After a survey of recent sensor mode read address of the memory block. After all the addresses recorded in the previous cycle of the survey, read, begins a new polling cycle. The disadvantage of this device is that the information coming into the computer, contains only the number of the sensor, has changed its state.

Known closest to the proposed device for inputting information (USSR author's certificate No. 1509858, CL G 06 F 3/00, 1987, published 23.09.89, bull. No. 35), containing the multiplexer, encoder, code Converter, the address counter, the time counter, pulse generator, the unit's permanent memory, three buffer register, the switch data switch flag and more. The device is used to input information from sensors to control or calculate the performance communications system, for example in the display. When triggered some sort of sensor, its number, and the status and response time are written into the buffer registers, and then byte by byte through the switch data is transferred into the display. The disadvantage of this device is that it takes two time series. First queries an external device and stored in the buffer registers, then the information byte is passed to the display.

The invention solves the problem of increasing the amount of information transmitted in the current cycle of the survey.

To achieve this, the technical result in the input device information containing switch information inputs which are the inputs of the input device, the first counter, a storage device, the outputs of which are the first outputs of the device, and the outputs of the first counter is connected with the older bits of the address input of the memory device and the address inputs of the switch, put the synchronizer, the second counter, the first element And the second element And the third element And the output switch connected to the first input of the first element And a second input connected to the output of the second counter, the output of the first element And connected to the first input of the second element And and the first input of the third element And the second output of the input device, the second input Vtorov the element And connected to the first clock input of the second counter, younger bits of the address input of the storage device and the first output of the synchronizer, the output of the second element And is connected to the counting input of the first counter, the second output of the synchronizer is connected to the information input of the storage device and the third output of the input device, the third output of the synchronizer is connected to a second input of the third element And whose output is connected with the second installation input of the second counter.

When the synchronizer contains a master oscillator, a binary counter, a first inverter, a second inverter, the first element 3I, the second element 3, element ILI, and the first output of the counter is connected with the first inputs of the elements 3I, the second output of the counter is connected to the second input of the first element 3 and the input of the second inverter, the output of which is connected with the second input of the second element 3I, a third output of the counter is the first output of the synchronizer and is connected to the third input of the second element 3I and the input of the first inverter, the output of which is connected to the third input of the first element 3I, the output of the first element 3I is connected with the first input element ILI-NOT whose output is the second output of the synchronizer, the output of the second element 3I is the third output of the synchronizer and is connected with the second input element ILI, the generator output is connected to the n input of the counter.

The proposed device input information is illustrated in the drawings, on which:

figure 1 - block diagram of the input device information;

figure 2 - electrical functional diagram of the input device, serving, for example, thirty-two external devices;

figure 3 - timing diagram of the input device.

The input device information contains the switch 1, information 2 inputs are inputs of the input device, the first counter 3, storage device 4, the outputs of which are the first outputs 5 device, and the outputs of the first counter 3 is connected with the older bits of the address input of the storage device 4 and the address inputs of the switch 1, the synchronizer 6, the second counter 7, the first element And 8, the second And gate 9, the third element And 10, and the output of switch 1 is connected to the first input of the first element And 8, a second input connected to the output of the second counter 7, the output of the first element And 8 is connected to the first input of the second element And 9 and the first input of the third element And 10 and the second output 11 of the input device, the second input of the second element And 9 connected to the first clock input of the second counter 7, with the younger bits of the address input of the storage device 4 and the first output of the synchronizer 6, the output of the second element And 9 connected what about the counter input of the first counter 3, the second output of the synchronizer 6 is connected to the information input of the storage device 4 and the third output 12 of the input device, the third output of the synchronizer 6 is connected to a second input of the third element And 10, the output of which is connected with the second installation input of the second counter 7.

In a variant of the device presented in figure 2, the switch 1 has thirty-two information inputs 2 and, accordingly, five address inputs connected to the outputs of the first counter 3 and older bits of the address inputs of the storage device 4. Wires carrying out these connections, labeled 13-17.

The synchronizer 6 contains the master oscillator 18, the binary counter 19, the first inverter 20, the second inverter 21, the first element 3I 22, the second element 3I 23, item 2 OR-NOT 24, and the first output of the counter 19 is connected with the first inputs of the elements 3I 22 and 23, the second output of the counter 19 is connected to the second input of the first element 3I 22 and the input of the second inverter 21, the output of which is connected with the second input of the second element 3I 23, the third output of the counter 19 is the first output of the synchronizer 6 and is connected to the third input of the second element 23 and 3I entrance the first inverter 20, the output of which is connected to the third input of the first element 3I 22, the output of the first element 3I 22 connected to the first input element ILI-NOT 24 whose output is the second output of the synchronizer, the output of the second element 3I 23 is the third output of the synchronizer and is connected with the second input element ILI-NOT 24, the output of the generator 18 is connected to the input of counter 19.

The inputs 2 switch 1 receives logic signals from external devices (not shown). For example, if the first information input of logic "0", the external device connected to this input, properly, if a logical "1", that is defective.

In the storage device 4 recorded information describing each information input 2 switch 1, that is, each external device. Symptom for the first information input can be, for example: "Not good subunit number one in the block number ten in the rack room five." This feature is encrypted is recorded in the storage device 4.

To the timing charts 25, 26, 27 (see figure 3) shows the electrical oscillations respectively, the first, second and third (senior) discharge counter 19. To the timing charts 28 and 29 shows the electrical oscillations respectively from the outputs of the elements 22 and 23. The electrical signals at the output 12 of the input device is represented on the time chart 30.

The input device operates as follows.

If all inputs 2 switch 1 logical zeros, then its output is also zero. The second And gate 9 is open, fluctuations 27 p the foot on the counting input of the first counter 3, output code which sequentially varies from state 00000 to 11111. Thus sequential and cyclic polling of inputs 2 switch 1. This single potential output 11 input device does not interrupt a working computer program.

If one of the inputs 2 switch 1 (for example, on the first) appears logical unit, when the output code 00000 first counter 3 this unit is transmitted to the output switch. As to the second input of the first element And 8 logical unit, at its output, and hence at the output 11 of the input device, a logical zero signal interruption. A logical unit to a second input of the first element And 8 is determined by the output state of the second counter 7, which is at unit potential at the output of the first element And 8 is guaranteed is held in the initial state clocked 29 from the third output of the synchronizer 6, through which the third element And 10 are received in the second installation of the "S"input of the counter 7, the third element And 10 open single potential from the output of the first element And 8 until the interrupt signal.

Since the appearance of the interrupt signal begins to form a time interval Δt, which is necessary for signal processing of interrupts and asynchronous input from the storage device 4 information that characterized the em external device, connected to the first input of switch 1.

Value Δt is counted from the moment of occurrence of the interrupt signal to the output settings Q second counter 7 per unit.

The following active front oscillations 27 the first counter 3 is transferred into the state 00001 and the output of the switch 1 is transferred to the potential of the second input 2.

Thus, during Δt on the address inputs A1...A5 storage device 4 code is not changed. During this time of the storage device can read information that characterizes the external device connected to the selected input 2 switch.

The difference between the proposed device is that the least significant bit A0 of the address of the storage device 4 connected to the first output of the synchronizer 6, the electrical oscillations which are shown on the time chart 27. These oscillations are continuous in time, with them rigidly synchronized pulses 30 reading information from the storage device 4. One of these pulses are always generated at the time when the address inputs A0 storage device, there is zero potential, another pulse is always generated when a single potential at the input A0 of the storage device. Pulses 30 are received at the output 12 of the input device, in this case, for example, the first pulse reads from remember the first device, low byte, and the second byte of the word that characterizes the input selected input device.

Thus, using a simple input device is served by a large number of external devices, each of which may have a sufficiently large volume of information, in the simplest case, for example, a two-byte word. Information is transmitted in the current cycle of the survey of external devices. This is the technical result of the claimed device.

1. The input device information containing switch information inputs which are the inputs of the input device, the first counter, a storage device, the outputs of which are the first outputs of the device, and the outputs of the first counter is connected with the older bits of the address input of the memory device and the address inputs of the switch, characterized in that the input device entered the synchronizer, the second counter, the first element And the second element And the third element And the output switch connected to the first input of the first element And a second input connected to the output of the second counter, the output of the first element And connected to the first input of the second element And the first input of the third element And the second output of the input device, the second input of the second element And connected to the first si is chronicarum input of the second counter, younger bits of the address input of the storage device and the first output of the synchronizer, the output of the second element And is connected to the counting input of the first counter, the second output of the synchronizer is connected to the information input of the storage device and the third output of the input device, the third output of the synchronizer is connected to a second input of the third element And whose output is connected with the second installation input of the second counter.

2. The device according to claim 1, wherein the synchronizer includes a master oscillator, a binary counter, a first inverter, a second inverter, the first element 3I, the second element 3, element ILI, and the first output of the counter is connected with the first inputs of the elements 3I, the second output of the counter is connected to the second input of the first element 3 and the input of the second inverter, the output of which is connected with the second input of the second element 3I, a third output of the counter is the first output of the synchronizer and is connected to the third input of the second element 3I and the input of the first inverter, the output of which is connected to the third input of the first element 3I the output of the first element 3I connected to the first input element ILI-NOT whose output is the second output of the synchronizer, the output of the second element 3I is the third output of the synchronizer and is connected with the second input element OR NOT, the generator output is connected to the input of the counter.

 

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