Device for making image input into computer

FIELD: computation engineering.

SUBSTANCE: device has alphanumeric transformer, control unit and additionally introduced amplifier and transceiver register. Data input is carried out by sequentially reading each byte saved in the transceiver register.

EFFECT: high speed of input.

2 cl, 2 dwg

 

The invention relates to computer technology and can be used in vision systems for entering information into a computer.

A device for inputting image in the computer (autospid. No. 1432494 the USSR, CL G 06 F 3/00, 1988, bull. No. 39), containing the shift register, the control unit, the bit counter, a register, and the address counter, the pulse shaper, the block buffer memory block channel transceivers, the communication unit with a computer.

A disadvantage of this device is a low speed, as for image input in the computer you want to transfer to the device address of each input picture element.

Closest to the present invention is a device for inputting image in the computer (U.S. Pat. Of the Russian Federation No. 2166790, CL 7 G 06 F 3/00, 2000, bull. No. 13)that contains a control unit, a register, and the buffer memory, the address counter, the communication unit with a computer, the ADC, the first and second blocks channel transmitters.

A disadvantage of this device is the low speed of the image input in the computer.

The technical task of this device is to increase the speed of the image input in the computer.

The technical problem is solved in that the device for image input in the computer that contains the ADC, the control unit entered amplifier, case acceptance, and information output of the cameras connected to the input of the amplifier, the output of which connection is to the first input of the ADC, whose second input is connected to the first output of the control unit and with the control input of the register of acceptance, the data inputs of which are connected to the outputs of the ADC, and the information terminals are connected with the first group of inputs of the control unit and are a group of outputs of the device to connect to the younger vosmikaltsievy lines AD [0...7] of the PCI bus, the second and third outputs of the control unit, the first, second and third inputs of the second group of inputs of the control unit and the third group of inputs of the control unit are the bus control signals and connected respectively to the control lines of the PCI bus, namely, TRDY, DEVSEL, CLK, FRAME, IRDY and C/BE [0...3], the fourth group of inputs of the control unit is the address bus of the device and is connected to the multiplexed lines AD [8...11] the PCI bus.

The invention is illustrated by drawings, where figure 1 presents a structural diagram of a device for inserting an image into the computer, and figure 2 presents the scheme of the control unit.

A device for inputting image in the computer contains the information input 1, power 2, the control unit 3 (BU), ADC 4, the register of acceptance 5, the address bus and data 6, the bus control signals 7, the address bus 8, and the information output 1 camera connected to the input of the amplifier 2, the output of which is connected to the first input of the ADC 4, whose second input is connected with the first you the Odom control unit 3 and with the control input of the register of acceptance 5, the data inputs of which are connected to the outputs of the ADC 4, and the information terminals are connected with the first group of inputs of the control unit 3 and are a group of outputs 6 devices to connect to the lower eight multiplexed lines AD [0...7] of the PCI bus, the second and third outputs of the control unit 3, the first, second and third inputs of the second group of inputs of the control unit 3 and the third group of inputs of the control unit 3 are bus control signals 7 and are connected respectively to the control lines of the PCI bus, namely, TRDY, DEVSEL, CLK, FRAME, IRDY and C/BE [0...3], the fourth group of inputs of the control unit 3 is the address bus 8 device and is connected to the multiplexed lines AD [8...11] the PCI bus.

The control unit 3 is designed to control the reception or transmission of one byte of the television image in the computer. The control unit (cu) contains the first 9, 10 and 11 third elements And the element OR NOT 12, the first 13, second 14, third 15 and 16 fourth elements are NOT the first 17 and second 19 and the third 20 items AND IS NOT, a trigger 18, the first 21 and second 22 transistors, and the input of the first element 16 is the third entry of the second group of inputs BU 3, the third input element OR NOT 12, the first input of the first element And 9, the input of the first element 13, the input of the second element is NOT 14 are connected respectively to the control lines C/BE [0...3] of the PCI bus and are third gruppovogo BU 3, the third input of the second element And 10, the second input of the first element And 9, the fourth and fifth inputs of the element OR NOT 12 are connected respectively with multiplexed lines AD [8...11] the PCI bus and are the fourth group of inputs BU 3, first, second and third inputs of the third element And 11, the third input of the first element And 9, the first input element OR NOT 12, the first and second inputs of the second element And 10, the second input element OR NOT 12 are connected respectively with multiplexed lines AD [0...7] of the PCI bus and are the first group of inputs BU 3, the fourth input of the first element AND NOT the 17th is the first entry of the second group of inputs BU 3, the third input element 15 is a second input of the second group of inputs BU 3, the outputs of the first 9 and second 10 and 11 third element And the output element OR NOT 12, the outputs of the first 13, second 14 and third 15 elements NOT connected respectively to the first, second, third, fifth, sixth, seventh and eighth inputs of the first element AND NOT 17, the output of the third element 15 is also connected to the reset input of the trigger 18, the input set which is connected to the output of the first element AND NOT 17, direct trigger 18 is connected to the second input of the second element AND-NOT 19, the first input of which is connected with the output of the fourth element 16, the output of the second element AND-NOT 19 connected to the inlet of the first transistor 21, the first input of the third is lament AND NOT 20 and is the first output BU 3, inverted output of the trigger 18 is connected to the second input of the third element AND-NOT 20, the output of which is connected with gates of the first 21 and second 22 transistors, the first substrate 21, the source and substrate 22 of the second transistor is connected to the ground potential, the drains of the first 21 and second 22 of the transistors are respectively the second and third outputs BOO 3.

ADC 4 is an eight-bit analog-to-digital Converter and designed for converting the analog video signal coming from the amplifier 2, in the digital eight-bit binary code. At first ADC input 4 receives the analog video signal amplified by the amplifier 2. The second ADC 4 is a control, the appearance of a pulse on this input, the data is refreshed on the ADC output.

Register of acceptance 5 is designed to receive ADC 4 eight-bit code and the subsequent data transmission channel of the computer.

The device operates as follows.

Information signal 1 from the camera to the input of the amplifier 2, which provides the signal amplitude required for normal operation of the ADC 4. ADC 4 in the presence of a positive pulse at its second input converts this signal into a parallel eight-bit binary code and passes in case of acceptance 5.

To read a byte of image data is the computer activates the inverse of the signal FRAME and multiplexed lines AD [0...11] sets the device address 036Fh (binary 0011 0110 1111, the most significant bit on the left), and line C/BE [0...3] command read port input/output (binary 0010). At the first input of the second group of inputs BU 3 receives pulses CLK with a frequency up to 66 MHz. The emergence of the input BU 3 device address, a read command and a positive pulse CLK causes a logical 0 at the output of the first element AND NOT 17, and then install the trigger 18 in one state. A logical 0 on the inverse of the output of the trigger 18 causes a logical 1 at the output of the third element AND-NOT 20, which is supplied to the gates of the first 21 and second transistors 22 and opens them. In this case, the drain of the second transistor 22 and respectively on the lines DEVSEL will be low, which means there is a device at address 036Fh.

Upon receipt of the low level on line DEVSEL computer indicates its willingness to exchange data inverted signal IRDY. The occurrence of low level signal IRDY on the third input of the second group of inputs BU 3 will cause the logical unit to the first input of the second element AND-NOT 19. The logical 0 output of the second element AND-NOT 19 arrives at the source of the first transistor 21, causing the logical 0 at the drain of the transistor (the transistor is open and the line TRDY computer, indicating that the device is ready to exchange. In addition, the logical 0 output of the second element AND-NOT 19 is supplied to the control input reg is the country of reception and transmission 5, allowing the issuance of data on the address bus and data 6 device and respectively multiplexed lines AD[0...7] of the PCI bus. Next, the computer sends a high level on the lines of the FRAME and IRDY, resulting to the control input of the register of acceptance 5 receives a logical 1, which prohibits the extradition of data and updates the data at the output of the ADC 4. In addition, a logical 0 at the output of the third element 15 resets the trigger 18 to 0, which causes a logical 0 at the output of the third element AND-NOT 20 and on the gates of the first 21 and second 22 transistors. The first 21 and second 22 transistors are closed, providing a low signal on the second and third outputs BU 3 (high-impedance state). Read the next byte of image process is repeated.

Thus, with the introduction of the amplifier and the register of acceptance increases the speed of the image input in the computer.

1. A device for inputting image in the computer that contains the ADC, the control unit, characterized in that the device entered amplifier, case acceptance, and information output of the cameras connected to the input of the amplifier, the output of which is connected to the first input of the ADC, whose second input is connected to the first output of the control unit and with the control input of the register of acceptance, the data inputs of which are connected to the outputs of the ADC and the information is nnye outputs are connected with the first group of inputs of the control unit and are a group of outputs of the device to connect to the lower eight multiplexed lines AD[0...7] PCI bus, the second and third outputs of the control unit, the first, second and third inputs of the second group of inputs of the control unit and the third group of inputs of the control unit are the bus control signals and connected respectively to the control lines of the PCI bus, namely, TRDY, DEVSEL, CLK, FRAME, IRDY and C/BE[0...3], the fourth group of inputs of the control unit is the address bus of the device and is connected to the multiplexed lines AD[8...11] the PCI bus.

2. The device according to claim 1, characterized in that the control unit (cu) includes first, second and third elements And the element OR NOT, the first, second, third and fourth elements are NOT, first, second and third elements AND NOT the trigger, the first and second transistors, and the input of the first element is NOT a third input of the second group of inputs BOO, the third input element OR NOT, the first input of the first element And the first input element, the input of the second element is NOT connected respectively to the control lines C/BE[0...3] the PCI bus and are the third group of inputs BOO, the third input of the second element And the second input of the first element And the fourth and fifth inputs of the element OR NOT connected respectively with multiplexed lines AD[8...11] the PCI bus and are the fourth group of inputs BOO, first, second and third inputs of the third element And the third input of the first element And the first input element OR NOT, the first and the second input of the second element, And the second input of the element OR NOT connected respectively with multiplexed lines AD[0...7] of the PCI bus and are the first group of inputs BOO, the fourth input of the first element AND is NOT the first entry of the second group of inputs BOO, the entrance to the third item is NOT a second input of the second group of inputs BOO, the outputs of the first, second and third elements And the output of the element OR NOT, the outputs of the first, second and third elements are NOT connected respectively to the first, second, third, fifth, sixth, seventh and eighth inputs of the first element AND NOT, exit the third element is NOT connected to the reset input of trigger, the input set which is connected to the output of the first element AND IS NOT the direct trigger output connected to the second input of the second element AND the first input of which is connected with the output of the fourth element, the output of the second element AND IS NOT connected to the source of the first transistor, the first input of the third element AND IS NOT and is the first release of BOO, the inverse of the trigger output is connected to the second input of the third element AND IS NOT, the output of which is connected with gates of the first and second transistors, the first substrate, the source and substrate of the second transistors connected to the ground potential, the drains of the first and second transistors are respectively the second and third outputs BOO.



 

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