Effective-equipment transceiver incorporating delta-sigma digital-to-analog converter

FIELD: communication system transceivers.

SUBSTANCE: transceiver 80 has digital circuit 86 for converting modulating signals into intermediate-frequency ones. Signal source 114 transmits first periodic reference signal 112 at first frequency. Direct digital synthesizer 84 receives second periodic signal 102 at second frequency from first periodic reference signal. Converter circuit affording frequency increase in digital form functions to convert and raise frequency of modulating signals into intermediate-frequency digital signals using second periodic signal 102. Digital-to-analog converter 82 converts intermediate-frequency digital signals into intermediate-frequency analog signals using first periodic reference signal 112.

EFFECT: reduced power requirement at low noise characteristics.

45 cl, 3 dwg

 

The technical field to which the invention relates.

The present invention relates to communications systems. Specifically, the present invention relates to transceivers used in communication networks.

The level of technology

Cellular communication system are many mobile transceiver that communicates with one or more base stations. Each transceiver contains a transmitter and receiver.

In a typical transceiver input analog radio frequency (RF) signal, the adopted antenna, convert the downconverter RF section into a signal of intermediate frequency (if). The signal processing unit performs the filtering of noise and adjusts the amplitude of the signal through the analog circuit of the automatic gain control (AGC). Section FC then carry out the conversion signal with decreasing frequency to baseband signal and converts the analog signal into a digital signal. The digital signal is then fed to a processor baseband signals for further signal processing to obtain speech signals or data.

Similarly, the transmitter accepts digital input signal from the processor baseband signal and converts the input signal into an analog signal. This signal is then filtered and transform with increasing frequency in the cascade inverter in the signal between the exact frequency. Regulate the amplification of the transmitted signal and the if signal transform with increasing frequency in the RF signal in preparation for the broadcast.

In the transmitting and receiving sections of the gain control signal and the frequency conversion is usually performed in the analog form. This requires multiple local oscillators (GT) to convert the signal with decreasing frequency, transform with increasing frequency and mixing (conversion). Analog oscillators are large and require the use of one or more circuits phase-locked loop. As is known, the circuit phase-locked loop are large, expensive schemes that consume significant power. Therefore, the use of circuits phase-locked loop (PLL) increases the cost, size and power consumption of analog oscillators and transceivers, in which these schemes are used.

Therefore, there is a need for cost-effective, dimensions of the transceiver with low noise performance and minimum power consumption.

The invention

The need is met by the transceiver in accordance with the present invention. The proposed transceiver contains digital circuitry for converting baseband signals in the s intermediate frequency. The source generates a first periodic signal with the first frequency. Direct digital synthesizer receives a second periodic signal of a second frequency of the first periodic reference signal. Converter circuit with increasing frequency in digital form transforms with increasing frequency modulating signals to digital intermediate frequency signals using the second periodic signal. D / a Converter converts the digital intermediate frequency signals into an analog intermediate frequency signals using the first periodic signal.

In a variant implementation of the transceiver digital circuit converts with increasing frequency of the first signal of the first frequency signal with the second frequency in response to the second periodic signal and, in addition, in response produces a digital signal. The second scheme is designed to convert digital transmitted signal into an analog signal. Diagram of transmission and reception are intended for transmission of analog transmitted signal and receiving an analog received signal, respectively.

In a specific embodiment, the analog received signal in a digital form transform with decreasing frequency to generate a digital received signal in response to the second if the second signal. An important feature of the invention consists in the issuance of the first and second periodic signals only lo. Direct digital synthesizer is designed to generate one of the reference signals from the output signal of the local oscillator.

The scheme of transfer contains Delta-Sigma d / a Converter, which includes a first periodic signal as an input. Delta-Sigma d / a Converter has a digital to analog Converter least significant bits and the Delta-Sigma modulator.

In the illustrated embodiment, digital to analog Converter least significant bits is a one-bit digital to analog Converter, Delta-Sigma modulator Delta-Sigma modulator of the sixth order. Delta-Sigma modulator includes amplifiers with approximately the following gains: 3/2, -3/4, 1/8.

The circuit contains a digital transmission scheme of automatic gain control for adjusting the gain of the first signal. The output signal circuit of the automatic gain control serves to the input of the Delta-Sigma digital to analogue Converter. Also in the transmission scheme included a digital lowpass filter, a digital frequency Converter and a digital adder. The output signal of the digital adder is fed to the input circuits of an automatic adjustment pileni is.

New design of the present invention is lightweight due to the elimination of the local oscillator using a direct digital synthesizer and a Delta-Sigma digital to analogue Converter. Eliminating the lo achieve economies of power and size.

Brief description of drawings

The features, objectives and advantages of the present invention will become more apparent from the detailed description below, when considered in conjunction with the drawings, in which similar designation are identified accordingly on all drawings.

Figure 1 depicts a block diagram of a known transceiver.

Figure 2 depicts a block diagram of the transceiver, created in accordance with the present invention and using Delta-Sigma (Δ∑) digital to analogue Converter (DAC) and a direct digital synthesizer (PDB).

Figure 3 depicts a block diagram of the Δ∑ DAC, shown in figure 2.

A detailed description of the preferred embodiments

Although the present invention is described with reference to exemplifying embodiments of for particular applications, it should be clear that the invention is not limited. Specialists in this field of technology are obvious additional modifications, applications and embodiments of its volume and additional areas in which the present invention may be useful.

Following an overview of the typical transceiver is designed to facilitate understanding of the present invention.

Figure 1 depicts a block diagram of a known transceiver 20. The transceiver 20 is a telecommunication transceiver, double-conversion and includes an antenna 21 for receiving and transmitting RF signals. The antenna switch 22 associated with the antenna 21, facilitates the separation of the received RF signals 24 from the transmitted RF signals 26.

The received RF signal 24 is fed to the regimen, which contains the amplifier 28 received RF signals, the transmitter 30 of the RF frequency in the if band-pass filter 32 received signals, analog automatic gain control (AGC) 34 received signals and analog circuit 36 conversion frequencies in the modulating signals. The received RF signals 24 reinforce the amplifier 28 of the received signal converted into the intermediate frequency signals by the inverter 30 frequency RF-to-if filter bandpass filter 32 received signals, regulate the gain of the AGC circuit 34 of the received signals are then converted into digital baseband signals 48 through circuit 36 for converting analog signals of the inverter-in-modulating signals. Digital modulating signal 48 is then applied to the input of the digital processor 46 modulating signal is.

The transmitted RF signals 26 received on the antenna switch 22 from the transmission schemes, which contains the RF amplifier 38 of transmitted signals, the Converter 40 frequency frequencies in the RF band-pass filter 42 of transmitted signals and analog circuit 44 convert the baseband signals in the inverter. Output signals 50 digital processor baseband signals accepted analog circuit 44 convert the baseband signals in the inverter, in which they are converted into analog signals, convert the signals of the inverter, which are then subjected to filtering bandpass filter 42 of transmitted signals, carry out the conversion with increasing frequency to RF using a Converter 40 of the intermediate frequency-to-RF, increase the amplifier 38 of transmitted signals and then transmit through the antenna switch 22 and antenna 21.

Diagram of transmission and reception associated with the digital processor 46 baseband signals, which processes the received digital baseband signals 48 and generates output signals 50 digital baseband processor. The processor 46 of the modulating signals may contain functions such as converting the signal into voice data and/or Vice versa.

Output signals 50 processor baseband signals do not match in phase by 90° in relation to each other and correspond to in-phase (I) and quadrature (Q) is ignall. Output signals 50 serves to the input of digital to analog converters (PAP) 52 in the analog circuit 44 convert the baseband signals in the inverter, in which they are converted into analog signals, which are then filtered by filters 54 of the lower frequencies in preparation for the frequency conversion. Phase adjust signals, converts the frequency and summed by block 56 Phaser 90°, converters 58 frequency of the modulating signal in the inverter and adder 60, respectively. The adder 60 generates signals 62 of the inverter, which is fed to the input of the analog circuit 64 automatic gain control (AGC) of transmitted signals, in which the amplification of the converted signal 62 FC regulate in preparation for filtering by a bandpass filter 42 of transmitted signals, carry out the conversion with increasing frequency to RF by the inverter 40 of the intermediate frequency in the transmitted signals, amplify through amplifier 38 of transmitted signals and, finally, are broadcast through the antenna switch 22 and antenna 21.

DAC 52 in the circuit 44 converting baseband signals-in-FC-takeroot first local oscillator (GT) 66. The sampling frequency of the DAC 52 is determined by the frequency of the local oscillator 66. The local oscillator 66 also generates a clock signal in analog circuit 36 conversion of the if signal at the modulating signals, the which uses analog-to-digital converters (ADC) 68 in the analog circuit 36 conversion of the if signal in the baseband signals.

The second lo (GT) 70 is required for frequency converters 58 in the circuit 44 convert the analog baseband signals in the inverter. The second local oscillator 70 generates a clock signal having a frequency different from the frequency of the output signal of the first local oscillator 66. Typically, the second local oscillator 70 operates at a much higher frequency than the first local oscillator 66.

The third local oscillator 72 is required for the operation of the Converter 30 frequency frequency-FC of the received signals of the inverter 40 of the intermediate frequency in the RF transmitted signals. Usually the same local oscillator 72 is used for both of the inverters 30, 40 frequency.

The fourth local oscillator 73 is used for the analog circuit 75 conversion in the analog circuit 36 conversion of the if signal in the baseband signals to facilitate conversion of the if signal in the baseband signals, perform analog circuit 75 conversion.

All the oscillators 66, 70, 72, 73 require one or more circuits phase-locked loop (PLL). PLLs are typically large analog circuits, which consume excessive power.

Design limitations transceiver 20 limit the degree of signal processing that can be performed in digital form, and require the use of additional large consuming significant power analog with the eat, for example, local oscillators and analog AGC circuits. For example, there are multi-bit DAC 52 before converting the analog signal and filtering performed by the circuit 44 convert the baseband signals in the inverter. This is partly due to the fact that the DAC 52 will generate excessive noise, if they will be included after the translation scheme. That's why the signals 62 FC are more high-frequency signals, which increases the parasitic pulses of the Converter, whereby increases noise. Noise is usually located in the frequency band and is difficult to be filtered by conventional means.

As d / a conversion must take place before converting baseband signals-in-FC-using circuit 44, the circuit 44 convert the baseband signals in the inverter must be carried out in analog form. Analog converters 58 frequency filters 54, adder 60 and the analog AGC circuit 64 are much larger and consume more power than their digital equivalents. In addition, the inconsistency because of the low-precision analog circuitry causes a spurious signal of the local oscillator 70, which may not be filtered used in practice means.

In addition, the design of the transceiver 20 requires the use of at least Proc. of the x oscillators, that is, the first local oscillator 66, the second local oscillator 70 and the third local oscillator 72. The local oscillators 66, 70 and 72 contain large, inefficient power analog PLL.

Figure 2 depicts a block diagram of the transceiver 80, created in accordance with the present invention. The transceiver 80 uses Delta-Sigma (Δ∑) digital to analogue Converter (DAC) 82 and a direct digital synthesizer (PDB) 84. The transceiver 80 analog circuit 44 convert the baseband signals in the inverter shown in figure 1, and analog circuit 36 conversion if-to-baseband signals, depicted in figure 1, replaced, reconstructed scheme 86 converting baseband signals in the inverter and the reconstructed scheme 88 conversion if-to-baseband signals, respectively. Replacement eliminates the need for the second local oscillator 70, depicted in figure 1, significantly reducing power consumption and dimensions of the transceiver.

Δ∑ DAC 82 may convert digital signals to the inverter analog signals without the problems associated with spurious noise multibit DAC. Using Δ∑ DAC 82, converting baseband signals in the inverter can be performed in digital form, thus eliminating spurious signal generator.

Digital circuit 86 converting baseband signals in the if the content is it the first digital filter 90 of the lower frequencies and the second digital filter 92 of the lower frequencies, which filter out unwanted signals such as noise, quadrature (Q) 94 and in-phase (I) 96 signals received from the processor 46 of the modulating signals, respectively. The filtered in-phase signals fed to the input of the first digital Converter 98 frequency, while the filtered quadrature signals fed to the input of the second digital Converter 100 frequency. The first inverter 98 frequency takeroot clock signal 102 from PDB scheme PDB 84. The signal 102 PDB shift the phase by 90° digital phase shifter 106, receiving the shifted clock signal 104. Takirua converters 98, 100 frequency clock signals that differ in phase by 90°the signals I and Q coordinates in phase. Converters 98, 100 frequency transform signals I and Q signals of the inverter, which combine through a digital adder 108. The summed signals of the inverter is then applied to digital circuitry 110 AGC, the construction of which is known. Digital circuit 110 AGC adjusts the gain of signals of the inverter and outputs these signals to Δ∑ DAC 82. Δ∑ DAC 82 converts these signals into analog signals in preparation for further filtering of the bandpass filter 42, the conversion frequency to radio spectrum Converter 40 frequency, the gain of the amplifier 38 and passing through the antenna switch 22 and EN is Anno 21.

Δ∑ DAC 82 uses the signal 112 lo, formed only by the local oscillator 114 to control a single-bit DAC included in Δ∑ DAC 82 (as described in more detail below). Signal 112 of the local oscillator is also used as a signal of frequency control to control PDB 84, which synthesizes the clock signal 102 PDB. The clock signal 102 PDB has a frequency different from the frequency signal 112 lo.

PDB 84 receives the digitized sinusoidal signal corresponding to the clock signal 102 from signal 112 lo, accumulating the phase increment of the digital sinusoidal signal 102 at a higher frequency signal 112 lo. The accumulated phase is converted into a digitized sinusoidal signal 102 by means of a lookup table (not shown). Digitized sinusoidal signal 102 is used as a reference frequency converters 98, 100 frequency to convert the baseband signals 94, 96 in the system.

Design PDB 84 known and described in U.S. patent No. 4965533 (Direct Digital Synthesizer Driven Phase Lock Loop Frequency Synthesizer). Direct digital synthesizer driven by the frequency synthesizer circuit of the phase locked loop.

Specialists in the art it is clear that PDB 84 may be implemented as programmable PDB whose output clock signal 102 is adjusted in response to a transmission error or is of Riem due care lo frequency and/or other related errors. Such measurement errors can be detected by logic circuits in the processor 46 of the modulating signals, or by using additional schemes for error detection (not shown).

Using PDB 84 for forming the clock signal 102 PDB eliminates the need for additional local oscillator with an additional PLL. PDB 84 much less local oscillator and PLL and can be easily implemented in a compact scheme with a high degree of integration (SUISSE) along with a digital converters 98, 100 frequency filters 90, 92, the adder 108, the circuit AGC 110 and Δ∑ DAC 82. In addition, PDB 84 consumes relatively low power. The use of low-noise Δ∑ DAC 82 eliminates the need for additional multi-bit DAC, which is required in the transceiver 20, depicted in figure 1.

A separate local oscillator 70 PLL (Fig 1 and 2)required in the conventional transceiver 20 for converting the baseband signals in the inverter, replaced transceiver 80 of the present invention digital PDB 84. Performance schema 44 convert the baseband signals in the inverter shown in figure 1, is improved in accordance with the present invention. In the present invention, the analog processing functions are implemented in digital circuits, and giving spurious signals multibit DAC 52 replacing the s single-bit Delta-Sigma DAC 82.

In this particular embodiment, the signal 112 lo is also used for clocking digital circuit 88 conversion if-to-baseband signals in the regimen. In this particular embodiment, a digital circuit 88 conversion if-to-baseband signals contains fast Δ∑ analog-to-digital Converter (ADC) 116, a digital circuit 117 frequency conversion and frequency multiplier for frequency conversion signal 112 of the second local oscillator frequency for use in Δ∑ ADC 116. Design Δ∑ ADC, digital circuits frequency conversion and frequency multipliers are known from the prior art.

In the present embodiment, the frequency multiplier 119 divides the frequency (Fs) signal 112 lo four and outputs the received lo signal with the divided frequency as the clock signal for one-bit ADC (not shown)included in the Δ∑ ADC 116.

Signal 112 of the local oscillator provides the reference frequency for digital circuit 117 frequency Converter for use in digital circuit 117 of the frequency Converter to convert with decreasing frequency digital output signals of the inverter from Δ∑ ADC 116 modulating signals 48.

Specialist in the art it is clear that digital conversion function with decreasing frequency, are performed cifrovoy scheme 88 conversion if-to-baseband signals, can be carried out in a manner analogous to the conversion functions with increasing frequency, are performed in the digital circuit 86 converting baseband signals in the inverter. Also analog circuit 34 AGC can be implemented in a digital AGC circuit after Δ∑ ADC 116 in the digital circuit 88 conversion if-to-baseband signals.

Design regimens can be carried out in accordance with the patent application U.S. No. 08/987306 of 9 December 1997 (Receiver With Delta-Sigma Analog-To-Digital Converter. Receiver with Delta-Sigma analog-to-digital Converter).

Specialist in the art it is obvious that a digital circuit 86 converting the if-to-baseband signals may be replaced by another version, such as analog circuit 36 conversion if-to-baseband signals, depicted in figure 1, without deviation from the scope of the present invention. Circuit 84 PDB digital circuit 86 converting baseband signals in the inverter can be implemented in scheme 88 conversion if-to-baseband signals in addition to or instead of the implementation of the digital circuit 86 converting baseband signals in the inverter. That is, the output signal 102 PDB can be used by mapping with decreasing frequency and/or analog-to-digital converters in the circuit 88 conversion if-to-baseband signals. In addition, the circuit 110 AGC can the be implemented in analog form after Δ ∑ DAC 82 without deviation from the scope of the present invention.

Figure 3 is a block diagram Δ∑ DAC 82, shown in figure 2. Δ∑ DAC 82 contains a single-bit DAC 120 output Δ∑ modulator 122. Δ∑ modulator 122 is Δ∑ the modulator of the sixth order. Δ∑ modulator 82 has three main structural unit 124, also referred to as resonators of the second order cascade-connected with each other. Each basic building block 124 includes combining digital blocks 128 delays (z-1), amplifiers 130, which has a gain of voltage αi(where i is an integer index ranging from 0 to 5), the adder 132 and subtractive block 134. The adder 132 receives as parallel input signals the output signals from the amplifiers 130. On one of the amplifiers 130 serves an input signal digital block 128 delays the input signal is also input to another amplifier 130. This input signal to form a digital block 128 delay in subsequent resonator 124 or, in the case of the output of the main unit 124, it is shaped noise output signal 127 from Δ∑ modulator 82.

The first basic building block 124 receives the output signal of the digital circuit 110 AGC figure 2 as a third input to the adder 132. The placenta is the following building blocks 124 receive the output signals of the previous basic building blocks 124 as a third input signals to adders 132.

Specialists in the art will understand that the methods of construction of the main building blocks 124 are well known and can be implemented using a programmable matrix of logic elements.

From the output of the adder 132 signal as an input to the subtractive unit 134. The output signal of the adder 132 passes through the keypad 128 delay, thereby obtaining the output signal of the resonator 124. The output signal of the resonator 124 passes through another digital block 128 delay and is supplied to the second input of the adder 132, forming a feedback loop.

The quantization noise of a linear model element 126 noise, which is before forming unit having the form of a noise output signal 127.

The gain of the voltage amplifier 130 is selected to provide the transfer function and noise transfer function of the signal, which enable Δ∑ the modulator 82 to meet the stability requirements of the formation of noise to be applied. Methods of selection gain α for amplifiers 130 are well known in the prior art. In the present specific embodiment, the gain is equal to: α0=0, α1=3/2, α2=0, α3=-3/4, α4=0, α5=1/8.

Single-bit DAC 120 takeroot signal 112 Goethe is Odin, shown in figure 2. Specialist in the art it is clear that a single-bit DAC 120 may be replaced by a DAC least significant bits, for example, 2 - or 3-bit DAC, without deviation from the scope of the present invention. Design of Delta-Sigma DAC and ADC is widely known in the prior art.

Thus, the present invention is described with reference to the particular variant of implementation for private use. Specialists in this field of technology are obvious additional modifications, applications and embodiments of within its scope.

Therefore, the attached claims are intended to cover any and all such applications, modifications and embodiments within the scope of the present invention.

1. A digital circuit for converting baseband signals to intermediate frequency signals containing a signal source for receiving the first periodic signal, the first frequency, medium frequency synthesis to obtain a second periodic signal of a second frequency of the first periodic signal conversion tool with increasing frequency conversion with increasing frequency digital baseband signals to digital intermediate frequency signals using the second periodic signal and means digital to analogue conversion for conversions is of the digital intermediate frequency signals into an analog intermediate frequency signals using the first periodic signal.

2. Digital circuit according to claim 1, characterized in that the source signal contains a voltage controlled oscillator.

3. Digital circuit according to claim 1, characterized in that the means of frequency synthesis is a digital circuit.

4. Digital circuit according to claim 3, characterized in that the means of frequency synthesis provides a direct digital synthesizer.

5. Digital circuit according to claim 1, characterized in that the conversion tool with increasing frequency contains a digital filter to remove unwanted signals from the baseband signals and/or intermediate frequency signals.

6. Digital circuit according to claim 1, characterized in that the conversion tool with increasing frequency contains the first and second digital frequency converters.

7. Digital circuit according to claim 1, characterized in that the conversion tool with increasing frequency contains digital circuitry automatic gain control.

8. Digital circuit according to claim 1, characterized in that the means digital to analogue Converter comprises a Delta-Sigma d / a Converter.

9. Digital circuit of claim 8, wherein the Delta-Sigma digital to analog Converter comprises a Delta-Sigma modulator having an order higher than the second.

10. Digital circuit according to claim 9, wherein the Delta-Sigma modulator is a Delta-Sigma modulator of the sixth order.

11. Digital is Hema of claim 8, characterized in that the Delta-Sigma digital to analog Converter comprises a digital-to-analogue Converter least significant bits.

12. Digital circuit according to claim 11, wherein the digital to analog Converter is a one-bit digital to analog Converter.

13. The transceiver contains the first means for forming a first periodic signal, the first frequency, second means for forming a second signal of a second frequency in a digital form from the first periodic signal, a third means, using the first periodic signal to perform digital to analog conversion of signals in the circuit of converting baseband signals into intermediate frequency signals or analog-to-digital conversion of signals in the scheme of conversion of the intermediate frequency signals into baseband signals in the specified transceiver, and a third means includes a Delta-Sigma modulator, and fourth means for using the second signal as a signal reference frequency in the specified schema converting baseband signals to the intermediate signals frequency.

14. The transceiver according to item 13, wherein the first means comprises a generator.

15. The transceiver according to item 13, wherein the second means includes a direct digital synthesizer.

16. When operatic indicated in paragraph 13 characterized in that the third means includes a Delta-Sigma d / a Converter least significant bits.

17. The transceiver according to item 16, wherein the Delta-Sigma d / a Converter least significant bits is a one-bit digital to analog Converter.

18. The transceiver according to item 13, wherein the Delta-Sigma modulator is a Delta-Sigma modulator of the sixth order.

19. The transceiver contains a means for forming a first periodic signal, the first frequency, means for receiving the analog signal, and specified the means for receiving includes means for converting a received analog signal into a digital signal, using the first periodic signal, a means for digital processing of the received signal and for receiving the first transmitted signal, means for transmitting the first transmitted signal, and specified the means for transmitting includes means for converting the first transmitted signal from digital form to analog using the first periodic signal, and means for management of digital circuits in the specified means for transmitting and/or specified means for receiving the first periodic signal.

20. The transceiver according to claim 19, characterized in that the said means for upravleniemoeda direct digital synthesizer for converting the first periodic signal, the first frequency of the second periodic signal of a second frequency, and the second periodic signal serves as an input signal in a digital circuit included in the digital frequency Converter.

21. The transceiver according to claim 19, characterized in that the said digital circuits contain a direct digital synthesizer for forming the second periodic signal from the first periodic signal for use by the circuits of the frequency conversion of the signals in the specified tool for the transfer.

22. The transceiver according to claim 20, wherein the direct digital synthesizer is programmable direct digital synthesizer.

23. The transceiver according to claim 19, characterized in that the said means for transmitting includes a Delta-Sigma d / a Converter, and the specified d / a Converter has a first periodic signal as an input signal.

24. The transceiver according to item 23, wherein the Delta-Sigma digital to analog Converter comprises a digital-to-analogue Converter least significant bits and the Delta-Sigma modulator.

25. The transceiver according to paragraph 24, wherein the digital to analogue Converter least significant bits is a one-bit digital to analog Converter.

26. The transceiver according to paragraph 24, wherein the Delta-Sigma modulator is a Delta-Sigma modulator of the sixth order.

7. The transceiver on p, wherein the Delta-Sigma modulator includes amplifiers with approximately the following gains: 3/2, -3/4, 1/8.

28. The transceiver according to claim 19, characterized in that the said means for transmitting includes digital circuitry automatic gain control for adjusting the gain of the first transmitting signal.

29. The transceiver on p, characterized in that the output signal circuit of the automatic gain control is an input signal to the Delta-Sigma analog-to-digital Converter.

30. The transceiver according to clause 29, characterized in that the said means for transmitting includes a digital low pass filter, a digital frequency Converter and a digital adder for receiving an input signal for the circuit automatic gain control.

31. The transceiver according to claim 19, characterized in that the said means for receiving includes a Delta-Sigma analog-to-digital Converter.

32. The transceiver on p, characterized in that the said means for receiving includes a frequency multiplier, receiving the first periodic signal as an input signal and outputs the signal with the adjusted frequency in the response.

33. The transceiver on p, characterized in that the signal with the adjusted frequency frequency is, which is approximately 1/4 the frequency of the first periodic signal.

34. The transceiver on p, wherein the Delta-Sigma analog-to-digital Converter receives the signal with the adjusted frequency as the input signal.

35. The transceiver according to claim 19, characterized in that the said means for forming includes a voltage controlled oscillator.

36. The transceiver according to claim 19, characterized in that the said means for processing includes a baseband processor.

37. Transceiver with high performance, effective size and capacity, containing antenna means for receiving and transmitting radio frequency signals, the first conversion tool to convert RF signals into intermediate frequency signals and Vice versa, the second conversion tool for converting intermediate frequency signals into baseband signals and Vice versa, and the second conversion tool has a single local oscillator, means for filtering to remove unwanted signals from the baseband signals and intermediate frequency signals, means for regulating the gain United with the specified filtering means, for regulating the gain of the modulating signals and intermediate frequency signals, that is s to facilitate signal processing, and the means of processing baseband signals in accordance with predetermined commands transceiver.

38. The transceiver according to clause 37, wherein the second conversion tool performs the conversion using digital circuits frequency conversion.

39. The transceiver according to 38, wherein the second conversion tool provides a direct digital synthesizer for forming a clock signal with a frequency different from the frequency of the signal issued by the first local oscillator.

40. The transceiver according to clause 37, wherein the control device contains a digital gain circuit automatic gain control connected with the scheme of frequency conversion.

41. The transceiver according to clause 37, wherein the processor is a baseband processor of a mobile phone.

42. The transceiver according to clause 37, wherein the filtering means includes band-pass filter of transmitted signals, the bandpass filter of the received signals, at least one low pass filter.

43. The transceiver according to clause 37, wherein the first conversion tool contains the first lo.

44. Transceiver high performance with efficient equipment containing antenna means for receiving the received signals is peredachi transmitted signals, the generator tool for the formation of the first periodic signal, a signal processor for processing transmitted signals and received signals, the receiving, with a first analog-to-digital Converter having a first periodic signal as an input signal, for converting the received signals into baseband signals, and modulating the signals fed to the input of a signal processor, a transmission scheme that has a diagram of frequency conversion for converting the frequency of transmitted baseband signals received from the specified signal processor, the signal range intermediate frequency, a direct digital synthesizer for synthesis of the second periodic signal from the first periodic signal for clocking schemes for frequency conversion, the first analog the Converter transfer scheme, with the first periodic signal as an input signal to transform the signal range of the intermediate frequency analog signals, and the conversion scheme to convert the signal range intermediate frequency signals in a frequency range suitable for radio transmission, and generation of transmitted signals in the form of a response.

45. A digital circuit for converting signals between the signal range of the intermediate frequency signal di is the range of the modulating signals, contains the local oscillator for receiving the first periodic signal, the first frequency, the Delta-Sigma Converter for converting analog signals into digital signals and/or Vice versa using the first periodic signal, a direct digital synthesizer for receiving the second periodic signal based on the first periodic signal and the second periodic signal has a second frequency, and means of frequency conversion for converting digital signals and/or analog signals between the signal range of the intermediate frequency and baseband signals using the second periodic signal.



 

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1 cl, 3 dwg

FIELD: radio engineering for radio communications and radar systems.

SUBSTANCE: proposed automatically tunable band filter has series-connected limiting amplifier 1, tunable band filter 2 in the form of first series-tuned circuit with capacitor whose value varies depending on voltage applied to control input, first buffer amplifier 3, parametric correcting unit 4 in the form of second series-tuned circuit incorporating variable capacitor, second buffer amplifier 5, first differential unit 6, first amplitude detector 7, first integrating device 9, and subtraction unit 9. Inverting input of subtraction unit 9 is connected to reference-voltage generator 10 and output, to control input of variable capacitors 2 and 4. Automatically tunable band filter also has series-connected second amplitude detector 11, second integrating unit 12, and threshold unit 13. Synchronous operation of this filter during reception and processing of finite-length radio pulses is ensured by synchronizer 14 whose output is connected to units 10, 8, and 12. This automatically tunable band filter also has second differential unit whose input is connected to output of buffer amplifier 3 and output, to second control input of variable capacitor of band filter 2.

EFFECT: enhanced noise immunity due to maintaining device characteristics within wide frequency range.

1 cl, 1 dwg

FIELD: radio communications engineering; mobile ground- and satellite-based communication systems.

SUBSTANCE: proposed modulator that incorporates provision for operation in single-channel mode with selected frequency modulation index m = 0.5 or m = 1.5, or in dual-channel mode at minimal frequency shift and without open-phase fault has phase-shifting voltage analyzer 1, continuous periodic signal train and clock train shaping unit 2, control voltage shaping unit 3 for switch unit 3, switch unit 3, switch unit 4, two amplitude-phase modulators 5, 6, phase shifter 7, carrier oscillator 8, and adder 9.

EFFECT: enlarged functional capabilities.

1 cl, 15 dwg

FIELD: electronic engineering.

SUBSTANCE: device has data processing circuit, transmitter, commutation unit, endec, receiver, computation unit, and control unit.

EFFECT: high reliability in transmitting data via radio channel.

4 dwg

FIELD: electronic engineering.

SUBSTANCE: method involves building unipolar pulses on each current modulating continuous information signal reading of or on each pulse or some continuous pulse sequence of modulating continuous information code group. The number of pulses, their duration, amplitude and time relations are selected from permissible approximation error of given spectral value and formed sequence parameters are modulated.

EFFECT: reduced inetrsymbol interference; high data transmission speed.

16 cl, 8 dwg

FIELD: communication system transceivers.

SUBSTANCE: transceiver 80 has digital circuit 86 for converting modulating signals into intermediate-frequency ones. Signal source 114 transmits first periodic reference signal 112 at first frequency. Direct digital synthesizer 84 receives second periodic signal 102 at second frequency from first periodic reference signal. Converter circuit affording frequency increase in digital form functions to convert and raise frequency of modulating signals into intermediate-frequency digital signals using second periodic signal 102. Digital-to-analog converter 82 converts intermediate-frequency digital signals into intermediate-frequency analog signals using first periodic reference signal 112.

EFFECT: reduced power requirement at low noise characteristics.

45 cl, 3 dwg

FIELD: radio engineering; portable composite phase-keyed signal receivers.

SUBSTANCE: proposed receiver has multiplier 4, band filter 6, demodulator 8, weighting coefficient unit 5, adding unit 7, analyzing and control unit 10, synchronizing unit 3, n pseudorandom sequence generators 21 through 2n, decoder 1, and switch unit 9. Receiver also has narrow-band noise suppression unit made in the form of transversal filter. Novelty is that this unit is transferred to correlator reference signal channel, reference signal being stationary periodic signal acting in absence of noise and having unmodulated harmonic components that can be rejected by filters of simpler design than those used for rejecting frequency band of input signal and noise mixture. Group of synchronized pseudorandom sequence generators used instead of delay line does not need in-service tuning.

EFFECT: facilitated realization of narrow-band noise suppression unit; simplified design of rejection filters.

1 cl, 8 dwg

FIELD: mobile radio communication systems.

SUBSTANCE: proposed method and device are intended to control transmission power levels for plurality of various data streams transferred from at least one base station to mobile one in mobile radio communication system. First and second data streams are transmitted from base station and received by mobile station. Power-control instruction stream is generated in mobile station in compliance with first or second data stream received. Power control signal is shaped in mobile station from first power control instruction stream and transferred to base station. Received power control instruction stream is produced from power control signal received by base station; power transmission levels of first and second data streams coming from base station are controlled in compliance with power control instruction stream received. In this way control is effected of transmission power levels of first data stream transferred from each base station out of first active set to mobile station and of transmission power levels of second data stream which is transferred from each base station out of second active set to mobile station.

EFFECT: enlarged functional capabilities.

80 cl, 21 dwg

FIELD: radio engineering.

SUBSTANCE: proposed method and device designed for fast synchronization of signal in wade-band code-division multiple access (WCDMA) system involve use of accumulations of variable-length samples, testing of decoder estimates for reliability, and concurrent decoding of plurality of sync signals in PERCH channel. Receiver accumulates samples required for reliable estimation of time interval synchronization. As long as time interval synchronization estimates have not passed reliability tests, samples are accumulated for frame synchronization estimates. As long as frame synchronization estimates have not passed reliability tests, samples are analyzed to determine channel pilot signal shift.

EFFECT: reduced time for pulling into synchronism.

13 cl, 9 dwg

FIELD: satellite navigation systems and may be used at construction of imitators of signals of satellite navigational system GLONASS and pseudo-satellites.

SUBSTANCE: for this purpose two oscillators of a lettered frequency and of a fixed frequency are used. Mode includes successive fulfillment of the following operations - generation of a stabilized lettered frequency, its multiplication with an oscillator's fixed frequency and filtration of lateral multipliers with means of filters of L1 and L2 ranges and corresponding option of a fixed and a lettered frequencies.

EFFECT: reduces phase noise and ensures synthesizing of lettered frequencies of L1 and L2 ranges of satellite navigational system from one supporting generator at minimum number of analogous super high frequency units.

3 cl, 1 dwg

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