Double-input frequency modulator

FIELD: radio communications engineering; mobile ground- and satellite-based communication systems.

SUBSTANCE: proposed modulator that incorporates provision for operation in single-channel mode with selected frequency modulation index m = 0.5 or m = 1.5, or in dual-channel mode at minimal frequency shift and without open-phase fault has phase-shifting voltage analyzer 1, continuous periodic signal train and clock train shaping unit 2, control voltage shaping unit 3 for switch unit 3, switch unit 3, switch unit 4, two amplitude-phase modulators 5, 6, phase shifter 7, carrier oscillator 8, and adder 9.

EFFECT: enlarged functional capabilities.

1 cl, 15 dwg

 

The invention relates to the field of radio communications and can be used in digital systems, in particular in satellite and terrestrial mobile radio to generate oscillations with angular modulation with compact spectrum.

Analogues of the claimed devices are frequency modulators using quadrature schemes for the formation of the modulated signal, which include, for example, modulator π /4-DQPSK and CQPSK (Ovchinnikov M.A., Vorob'ev S.V., Sergeev S. Open standards digital trunking radio. Series “Communication in business”, M: ICSTI, LLC “Mobile communications”, 2000, at 166 C. Cm. s and 158). These modulators are made by the same structural schemes (RIS on p.74 and 8.10 on s). Block remap table, presented in Fig. 8.10, is presented in more detail. Different modulators π /4-DQPSK and CQPSK only filters and speed of information transmission (p.160). These modulators include unit conversion, two lowpass filter (filters Nyquist), two of the amplitude modulator and the adder, and two output devices transcoding are connected, respectively, to the inputs of low-pass filters, the outputs of low-pass filters are connected to the first input of the amplitude modulator, the second input of the amplitude modulator is supplied a carrier wave with mutual is the motor phase π /2, the outputs of these modulators are connected to the inputs of an adder whose output is the output of the frequency modulator. The disadvantage of these frequency modulators is the presence of accompanying amplitude modulation of the output signal. As a result, the power amplifier of the transmitter, this signal must operate in a linear mode, which eliminates the possibility of using high-efficiency modes of operation transmitter with high efficiency (s.80, p.160). The cause of concomitant AM is used in the method of forming the modulating voltages for modulators in quadrature channels (using response low-pass filters, including filters, Nyquist, under the action of their inputs short excitation pulses).

The closest in technical essence is a modulator performing frequency modulation without breaking phase Minimum Shift Keying (MSK) or, equivalently, the minimum modulation frequency shift (MMS) (see the book: the Banquet V.L., Dorofeev V.M. Digital techniques in satellite communications. - M.: Radio and communication, 1988. - 240 S., ill., S. 39-40, rib, 2.2).

This modulator includes a switch parcel into two quadrature channel (even - in one channel, odd in the other), the block forming the smoothing voltages, two multiplier, a carrier generator, a phase shifter, two amplitude-phase-modulator and sum the ATOR. Alternate switching parcels input baseband signal into two channels provides a two-fold increase in the duration of parcels in each channel. Smoothing the rectangular parcels of duration 2T0according to the laws of

in each channel, respectively, provides the shape of the envelope century-including voltages at the outputs of the amplitude and phase modulators in accordance with the voltages u1and u2consequence of which is a smooth change in phase C.-H. oscillations at the output of the adder for time T0on +π /2 or -π /2 depending on the make of the input modulating signal (0 or 1). This phase shift corresponds to the index of the frequency modulation of the output signal m=0,5. The selected form of the voltages u1and u2at the inputs of the quadrature amplitude and phase modulators provides no concomitant AM output signal, that is, the modulator is missing the main disadvantage of modulators and CQPSK π /4-DQPSK. In addition, the modulator, by doubling the duration of the parcels in the channels and the absence of phase jumps at the boundaries of the parcels, generates a modulated output frequency voltage with compact spectrum. In this modulator, there is no direct impact on the generator carrier, making saves is I high stability of the carrier oscillation, and the possibility of rapid change of the carrier frequency, what is important for systems with abrupt frequency change.

The disadvantage of the modulator MMS is the ability to retrieve only one value of the index of frequency modulation (m=0.5) and the non-implementation of dual-frequency modulation of the Raman seal channels. The reasons for this are, firstly, the use of the modulator smoothing voltages described above, which does not allow you to receive modulated signals with other indexes of modulation, and, secondly, the structure of the modulator, not allowing fluid seal channel.

In the invention solves the problem of the formation futuremusic voltage for amplitude and phase modulators I / q channels of a frequency modulator, which provides 4-frequency modulation without breaking phase with the management of two signals at the inputs of the modulator. This allows you to get the main technical result is the possibility of operation of the frequency modulator in single channel mode with the choice of the modulation index m=0.5 or m=1.5, or in dual mode with frequency modulation with minimal frequency shift and without breaking phase. This technical result extends the functionality of the frequency modulator and can be used in the adaptive communications systems, including cellular.

The solution to this for the ACI is achieved by in the frequency modulator comprising a generator carrier, Phaser, two amplitude-phase modulator and the adder, and the output of the carrier generator connected to the first input of the first amplitude-phase modulator and to the input of the phase shifter, the output of the phase shifter connected to the first input of the second amplitude-phase-modulator outputs the amplitude and phase modulators are connected, respectively, with first and second inputs of the adder, the output of which is the output of two-input of the frequency modulator includes an analyzer status futuremusic stresses, block the formation of a continuous periodic sequence of signals and sequences of clock pulses, the logic unit generating control voltages for the unit key and the block keys, with the first two inputs of the logic unit generating control voltages for the block of keys that are served binary modulating signals are the inputs of two-input of the frequency modulator 4 other input of logic unit generating control voltages for the unit keys are connected, respectively, with 4 outputs of the analyzer status futuremusic stress, 8 outputs a logical block generating control voltages for the unit keys are connected with the first 8 inputs of the block of keys, the second 8 inputs block is Luca connected with 8 outputs block the formation of a continuous periodic sequence of signals and sequences of clock pulses, the first output block of keys is connected with the second input of the first amplitude-phase modulator and to the first input of the analyzer status futuremusic voltage, the second output unit of the keys connected with the second input of the second amplitude-phase modulator and the second input of the analyzer status futuremusic stress, and the 3-rd and 4-th inputs of the analyzer status futuremusic voltages are connected, respectively, with the other two outputs of block formation of continuous periodic sequence of signals and sequences of clock pulses.

Analyzer status futuremusic stress includes two Comparators, two element 4 element And one element OR 4 extender pulses, and the inputs of the Comparators are, respectively, the first and second inputs of the analyzer state, the output of the first comparator is connected to the input of the first element and to the first input of the first element And the output of the second comparator is connected to the input of the second element and to the first input of the third element And the second inputs 1 and 2 elements And connected to the first input of the OR element, which is the third input of the analyzer state, the second inputs 3 and 4th elements And connected with the second input element OR, which is the fourth input of the analyzer status fatouros the operating voltage, the output of the first element is NOT connected to the first input of the second element And the second element is NOT connected to the first input of the fourth element And the outputs of all elements And are connected, respectively, with the first input expanders pulses, the output element OR is connected with the second inputs of all of the extenders pulses, and outputs extenders pulses are output analyzer status futuremusic stress.

Block the formation of a continuous periodic sequence of signals and sequences of clock pulses includes a master oscillator, 5 frequency divider by two, the frequency divider 6, a block preset trigger frequency dividers, two differentiating circuit with a limit on the minimum, two Exclusive OR element, 4 shaper of the sawtooth voltage and 4 driver voltage sine wave and the output of the master oscillator is connected with the first inputs of the first frequency divider by two and the frequency divider 6, the outputs of the first frequency divider by two are connected, respectively, with the first inputs of the second and third frequency dividers by two, the outputs of which are connected, accordingly, with the first inputs of the XOR, the first output of the frequency divider 6 is connected to the inputs of the first differential circuit with limit m is kimumu, the second driver of the sawtooth voltage and the fourth frequency divider by two, the second output of the frequency divider 6 is connected to the inputs of the second differentiating circuit with a limit on the minimum of the third driver of the sawtooth voltage and the fifth frequency divider by two, the first output unit preset triggers of frequency dividers connected to the second input of the first frequency divider by two, the second output unit preset triggers of frequency dividers connected with the second inputs of the second, third, fourth and fifth frequency divider by two and with a second input of the frequency divider 6, the outputs of the differentiating circuits with a limit on the minimum are the first two outputs block the formation of a continuous periodic sequence of signals and sequences of clock pulses, and the output of the fourth frequency divider by two is connected with the second input of the first Exclusive OR element, the output of the fifth frequency divider by two is connected with the second input of the second Exclusive OR element, the output of the first Exclusive OR element is connected to the input of the first driver of the sawtooth voltage, the output of the second Exclusive OR element is connected to the input of the fourth driver of the sawtooth voltage, the outputs of the forming voltage is elobrate forms are connected, respectively, to the inputs of the shapers of the voltage sine wave, direct and inverted outputs of which are the outputs of block formation of continuous periodic sequence of signals and sequences of clock pulses.

Logical unit generating control voltages for the block of keys has two elements are NOT, 20 elements And the eight elements OR, the first input of logic unit generating control voltages for the block of keys is connected to the input of the first element and NOT with the first inputs 3 and 4-th element And the second input of logic unit generating control voltages for the block of keys is connected to the input of the second element with the second inputs of the 2 and 4th elements And the output of the first element is NOT connected with the first inputs 1 and 2 of the first element And the second element is NOT connected with the second inputs 1 and 3rd elements And the output of the first element And connected with the first inputs of 5, 7, 9 and 11-th elements And the output of the second element And is connected with the first inputs 6, 8, 10 and 12-th element And the output of the third element And is connected with the first inputs 13, 15, 17 and 19-th element And the fourth output element And is connected with the first inputs 14, 16, 18 and 20-th element, And the third input of logic unit generating control voltages for the unit key connects with the which inputs 5, 6, 13 and 14-th element And the fourth input of logic unit generating control voltages for the block of keys is connected with the second inputs 7, 8, 15 and 16th of elements And the fifth input of logic unit generating control voltages for the block of keys is connected with the second inputs 9, 10, 17 and 18-th element And the sixth input of logic unit generating control voltages for the block of keys is connected with the second inputs 11, 12, 19 and 20th of elements And the output of the 5th element And connected with the first inputs 1 and 4-th elements OR the output of the 6-th element And is connected to third inputs 1 and 2 of the first element OR the output of the 7-th element And is connected with the first inputs 2 and 3-d elements OR the output of the 8-th element And is connected to third inputs 3 and 4-th elements OR the output of the 9-th element And is connected with the second inputs 1 and 2 of the first element OR the output of the 10-th element And is connected to the fourth inputs 2 and 3-d elements OR, exit 11th element And connected with the second inputs 3 and 4-th elements OR the output of the 12-th element And is connected to the fourth inputs 1 and 4th elements OR the output of the 13th element And connected with the first inputs 6 and 7-th elements OR the output of the 14-th element And is connected with the second inputs 7 and 8-th elements OR output 15-th element And is connected to the fourth inputs 5 and 8-th elements OR output 16-th element And is connected to the second I is DAMI 5 and 6-th elements OR the output of the 17-th element And is connected to third inputs 5 and 6-th elements OR exit 18-th element And is connected to the fourth inputs 6 and 7-th elements OR the output of the 19-th element And is connected to third inputs 7 and 8-th elements OR the output of the 20-th element And is connected with the first inputs 5 and 8-th elements OR, as the outputs of the elements OR are the outputs of the analyzer state.

Key block consists of 8 analog switches, each of the 8 control inputs of the block of keys connected to the control input of the corresponding analog switch, each of the 8 signal inputs of the block of keys is connected to the signal input of the corresponding analog switch, the outputs of the analog switches 1, 3, 5 and 7 are interconnected and form a first output unit key outputs of the analog switches 2, 4, 6 and 8 are also connected to each other and form a second output unit keys.

The set of features characterizing the two-input frequency modulator as a whole, provides the technical result in all cases to which is sought legal protections, and the features related to the analyzer status futuremusic stresses, block the formation of a continuous periodic sequence of signals and sequences of clock pulses, the logic unit generating control voltages for the block of the and keys and unit keys, characterize its only in the specific form of execution.

All the essential features of the claimed invention are in causal relationship with achievable technical result. Analyzer status futuremusic voltage determines the state futuremusic voltages at the inputs of the amplitude and phase modulators in quadrature channels at each clock time, the logic unit generating control voltages for the block of keys on the basis of the results of this analysis and the input of the modulating signal determines the form futuremusic voltages, which are to be received in each quadrature channel during the next clock interval, to make the output voltage had a frequency, and opens the necessary key pair in the block of keys (one for each quadrature channel). Through the public keys necessary futuremouse voltage outputs of block formation of continuous periodic sequence of signals and sequences of clock impulsive come to amplitude and phase modulate a quadrature channels. At the output of dual-frequency modulator are formed or 2-frequency modulated signals without breaking phase with the modulation index of 0.5 or 1.5, or 4-frequency (dual-channel) signal, also without breaking FA is s.

Figure 1 shows the structural diagram of two-input frequency modulator, figure 2 - block diagram of the analyzer status futuremusic stresses, figure 3 is a structural block circuit diagram of the formation of continuous periodic sequence of signals and sequences of clock pulses, figure 4 - structural diagram of the logic unit generating control voltages for the unit keys, figure 5 - block diagram of the block of keys, figure 6 - diagram of the pulse extender, nor Fig.7. diagram of the master oscillator, Fig - block circuit presets the flip-flops of the frequency divider, figure 9 - diagram of the frequency divider 6, figure 10 - diagram of the driver of the sawtooth voltage and shaper voltage sine wave, figure 11 diagram of a differentiating circuit with a limit on the minimum Fig diagram elements 4OR, Fig - waveforms of the voltages at the outputs of block formation of continuous periodic sequence of signals and sequences of clock pulses, Fig - waveform voltage in block form a continuous periodic sequence of signals and sequences of clock pulses, Fig - waveform voltage in the input of the frequency modulator.

Input frequency modulator contains the analyzer 1 status fatouros the operating voltage, unit 2 the formation of a continuous periodic sequence of signals and sequences of clock pulses, logical block 3 generating control voltages for the block key block 4 keys, the first amplitude-phase modulator 5, the second amplitude-phase modulator 6, the phase shifter 7, the generator carrier 8 and the adder 9. The analyzer 1 status futuremusic stress contains the Comparators 10 and 11, the elements 12 and 13 is, items 14-17 And the element 18 OR extenders 19-22 pulses. Unit 2 the formation of a continuous periodic sequence of signals and sequences of clock pulses includes a master oscillator 23, block 24 preset trigger frequency dividers, the dividers 25, 26, 28, 29 and 33 of the frequency by two, the divider 27 frequency 6, a differentiating circuit 31 and 32 with the restriction on the minimum, the elements 30 and 34 XOR, shapers 35, 37, 39 and 41 of the sawtooth voltage and the shaper 36, 38, 40 and 42 of the voltage sine wave. Logical block 3 generating control voltages for the block of keys contains elements 43 and 44 are NOT elements 45-64 And elements 65-72 OR. Unit 4 key contains analog switches 73-80.

The first and second inputs of a logical block 3 generating control voltages for the unit keys (see figure 4, the inputs of the elements 43 and 44), which served binary modulating signals I which are the inputs of the frequency modulator. Four other input of logic unit generating control voltages for the unit keys are connected with 4 outputs of the analyzer 1 state, the output of the expander 19 pulses is connected (see figure 2 and 4) with the second inputs of the elements 49, 50, 57 and 58 And the output of the expander 20 pulses is connected with the second inputs of the elements 51, 52, 59 and 60 And the output of the expander 21 pulses is connected with the second inputs of the elements 53, 54, 61 and 62 And the output of the expander 22 pulses is connected with the second inputs of the elements 55, 56, 63 and 64 I. 8 outputs logical block 3 generating control voltages for the unit keys are connected with 8 control inputs of block 4 keys, while the outputs of the elements 65-72 OR are connected, respectively, with the control inputs of analog switches 73-80. The first output unit 4 keys connected with the second input of the amplitude-phase modulator 5 and the first analyzer input 1 status futuremusic voltages, the outputs of the keys 73, 75, 77 and 79 are connected to the input of the comparator 10 and to the second input of the amplitude-phase modulator 5. The second output unit 4 keys connected with the second input of the amplitude-phase modulator 6 and the second analyzer input 1 status futuremusic voltages, the outputs of keys 74, 76, 78 and 80 are connected to the input of the comparator 11 and the second input of the amplitude-phase modulator 6. Inputs 3 and analyzer 1 status futuremusic voltages are connected to two outputs of the block 2 forming a continuous periodic sequence of signals and sequences of clock pulses, the first input element 18 is connected with the output of the differentiating circuit 32 with a limit on the minimum, and the second input element 18 is connected with the output of the differentiating circuit 31 with a limit on the minimum. Eight other outputs of block formation of continuous periodic sequence of signals and sequences of clock pulses 2 are connected to eight inputs of block 4 of keys, the first output driver 38 is connected with the signal input of the analog switch 73, the first output driver 40 is connected with the signal input of the analog switch 74, the second output driver 38 is connected with the signal input of the analog switch 75, the second output driver 40 is connected with the signal input of the analog switch 76, the first output driver 36 is connected with the signal input of the analog switch 77, the second output driver 42 is connected with the signal input of the analog switch 78, the second output of the shaper 36 connects to the signal input of the analog switch 79, the first output driver 42 is connected with the signal input of the analog switch 80.

The first analyzer input 1 status futuremusic voltage is connected (see figure 2) with the input of the comparator 10, the second analyzer input 1 status futuremusic voltage is connected with the input of the comparator 11, the output of the comparator 10 of the AESA with the input element 12 and to the first input element 14 And, the output of the comparator 11 is connected with the input of the element 13 and to the first input element 16 And second input elements 14 and 15 And connected with the first input element 18, OR, which is the third analyzer input 1 status futuremusic voltage, the second inputs of the elements 16 and 17 And connected with the second input element 18, OR, which is the fourth input of the analyzer status futuremusic voltage, the output element 12 is NOT connected with the first input element 15 And the output element 13 is NOT connected to the first input element 17 And the outputs of the elements 14-17 And are connected, respectively, with the first inputs extenders 19-22 pulses, the output of element 18 is connected with the second inputs of all of the extenders pulses, and outputs extenders pulses are output analyzer status futuremusic stress.

In unit 2 the formation of a continuous periodic sequence of signals and sequences of clock pulses the output of the master oscillator 23 (see figure 3) is connected with the input of the divider 25 of the frequency by two and with the input of the divider 27 frequency 6, the outputs of the divider 25 frequency two are connected, respectively, to the inputs of the dividers 26 and 28 of the frequency by two, the outputs of which are connected, respectively, with the first inputs of the elements 30 and 34 of the Exclusive OR, the first output of the divider 27 frequency 6 is connected to the input di is ferentina circuit 31 with a limit on the minimum shaper 37 of the sawtooth voltage and the first input of the divider 29 frequency by two, the second output of the divider 27 frequency 6 is connected to the input of the differentiating circuit 32 with a limit on the minimum shaper 39 of the sawtooth voltage and the first input of the divider 33 frequency by two, the first output unit 24 preset triggers of frequency dividers connected to the second input of the divider 25 frequency by two, the second output unit preset triggers of frequency dividers connected with the second inputs of the dividers 26, 28, 29 and 33 of the frequency by two and the second input of the divider 27 frequency 6, the outputs of the differentiating circuits 31 and 32 with the restriction on the minimum are the first two outputs of the block formation of continuous periodic sequence of signals and sequences of clock pulses, the output of divider 29 frequency on two connected with the second input element 30 XOR, the output of the divider 33 frequency on two connected with the second input element 34 XOR, the output of element 30 XOR is connected to the input of the driver 35 of the sawtooth voltage, the output element 34 Exclusive OR is connected with the input of the shaper 41 of the sawtooth voltage, the outputs of the shaper 35,37,39 and 41 of the sawtooth voltage are connected, respectively, to the inputs of the generators 36, 38, 40 and 42 N. the voltage sine wave, direct and inverted outputs of which are the outputs of block formation of continuous periodic sequence of signals and sequences of clock pulses.

The first input of logic unit 3 generating control voltages for the block of keys is connected (see figure 4) with the input element 43 and NOT with the first inputs of the elements 47 and 48 And the second input of logic unit 3 generating control voltages for the block of keys is connected with the input element 44 and to the second inputs of the elements 46 and 48 And the output element 43 is NOT connected with the first inputs of the elements 45 and 46 And the output element 44 is NOT connected to the second inputs of the elements 45 and 47 And the output element 45 And is connected with the first inputs of the elements 49, 51, 53 and 55 And the output element 46 And is connected with the first inputs of the elements 50, 52, 54 and 56 And the output element 47 And is connected with the first inputs of the elements 57, 59, 61 and 63 And the output element 48 And is connected to the first inputs of the elements 58, 60, 62 and 64 And second input elements 49, 50, 57 and 58 And connected to each other and a third input of logic unit 3 generating control voltages for the unit key, the second inputs of the elements 51, 52, 59 and 60 And are connected and are the fourth input of logic unit 3 generating control voltages for the unit key, the second inputs of the elements 53, 54, 61 and 62 And connected to each other and is the tsya fifth input of logic unit 3 generating control voltages for a block of keys, the second inputs of the elements 55, 56, 63 and 64 And connected to each other and are the sixth input of logic unit 3 generating control voltages for the unit key, the output element 49 And is connected with the first inputs of the elements 65 and 68 OR the output element 50 And is connected to third inputs of the elements 65 and 66 OR the output element 51 And is connected with the first inputs of the elements 66 and 67, OR, the output element 52 And is connected to third inputs of the elements 67 and 68 OR the output element 53 And is connected with the second inputs of the elements 65 and 66 OR the output element 54 And is connected to the fourth inputs of the elements 66 and 67, OR, the output element 55 And is connected with the second inputs of the elements 67 and 68 OR the output element 56 And is connected to the fourth inputs of the elements 65 and 68 OR the output element 57 And is connected with the first inputs of the elements 70 and 71 OR the output element 58 And is connected with the second inputs of the elements 71 and 72 OR the output element 59 And is connected to the fourth inputs of the elements 69 and 72 OR the output element 60 And is connected with the second inputs of the elements 69 and 70 OR the output element 61 And connected with the third inputs of the elements 69 and 70 OR the output element 62 And is connected to the fourth inputs of the elements 70 and 71 OR the output element 63 And is connected to third inputs of the elements 71 and 72 OR the output element 64 And is connected with the first inputs of the elements 69 and 72 OR, as the outputs of the elements OR show the available outputs of logic unit 3 generating control voltages for the block of keys.

Eight control inputs of block 4 keys (figure 5) are connected, respectively, with the control inputs of analog switches 73-80, 8 signal input unit 4 keys are connected, respectively, with signal inputs analog switches 73-80, the outputs of the analog switches 73, 75, 77 and 79 are interconnected and form a first output unit 4 key outputs of the analog switches 74, 76, 78 and 80 are also connected to each other and form a second output unit 4 keys.

Most of the functional units of the frequency modulator is performed on the IC: 2-input elements 14-17, 45-64 AND - CLI; 2-input accumulating element 18 OR CRL; dilators 19-22 pulse - RSD-triggers KR1533TM2 and inverters CRL according to scheme 6, the master oscillator 23 can be performed on the IC KRHG according to scheme 7, block 24 preset trigger frequency dividers may be made under the scheme Fig transistors CTG, dividers 25, 26, 28, 29 and 33 frequency of two can be performed on RSD-triggers CTM; the divider 27 frequency 6 for receiving the square wave output is in the form of a series connection of divisors on 3 and 2 on the diagram Fig.9 using before the output of divide-by-two form elements ILI NOT CRE; shaper of the sawtooth voltage (PNP) is performed on the integrating RC circuit (with a buffer amplifier operational amplifier, for example, CRU is 8). Driver voltage sine wave (FTS) is performed according to the scheme presented in the book: Earl R. Electronic circuits: 1300 examples: TRANS. from English. - M.: Mir, 1989, 688 S., ill., s; functional scheme of the site, which includes the PNP with the buffer amplifier and the FTS presented on figure 10; a differentiating circuit 31 and 32 with the restriction on the minimum can be performed on RC circuits with elements AND CLI restrict to a minimum, eliminate the negative pulses at the outputs of the differentiating circuits (11), 4-input elements 65-72 OR CLL (combining the outputs of the two elements ILI scheme Fig), the elements 12, 13, 43 and 44 NON - CRL, the elements 30 and 34 XOR - CLP, analog switches 73-80 run on IMS KRKN, the Comparators 10, 11 - CIS.

The operation of the frequency modulator is as follows.

Block the formation of a continuous periodic sequence of signals and sequences of clock pulses 8 2 creates a continuous periodic sequences S1...S8from elements which are formed futuremouse voltage u1and u2and two sequences of clock pulses TO and TI, following with a period of 2T0and mutually shifted by a time T0. The shape of the signals generated by the block formation of continuous periodic sequence signal is in and sequences of clock pulses, shown in Fig. The signals S1-S4frequencies Ω1=π /(2· T0), and the signals S5-S8frequencies Ω2=3π /(2· T0). With a clock pulse sequence TO coincide maximum positive and negative values of the signals S1, S3, S5and S7and with a clock pulse sequence TO coincide maximum positive and negative values of the signals S2, S4, S6and S8. Such mutual phasing of the signals and clock pulses, shown in Fig, is provided by the structure of the block 2, the formation of a continuous periodic sequence of signals and sequences of clock pulses (Fig 3) and the use of pre-installation trigger frequency dividers using block 24 preset trigger frequency dividers. The shape of the signals in the block 2 forming a continuous periodic sequence of signals and sequences of clock pulses presented to the timing charts Fig. The master oscillator 23 generates a square wave with a duration of elements of T0/12, where T0- the duration of the parcels binary signal at the input of the modulator (waveform u23). The shape of the voltages at the outputs of frequency dividers shown in Fig: u25-1and u25-227-1and u27-2- voltage on the direct and inverse outputs of the divider 27 frequency 6; u26u28u29and u33the voltages at the outputs of the respective frequency dividers by two. Differentiation with a limit on the minimum voltage u27-1gives the sequence of clock pulses TI and differentiation with a limit on the minimum voltage u27-2gives the sequence of clock pulses TI. Waveforms u30and u34on Fig show the shape of the voltages at the outputs of the elements 30 and 34 Exclusive OR. Forming a saw tooth voltage (PNP) of rectangular parcels on their inputs form a voltage, the shape of which is shown in the waveform u35u37u39and u41. From these stresses shapers of voltage sine wave (FTS) create the output voltages of the unit forming a continuous periodic sequence of signals and sequences of clock pulses: the direct and inverse outputs of the FTS 36 (u36-1and u36-2) signals S5and S7on direct and inverse outputs of the FTS 38 (u38-1and u38-2) signals S1and S3on direct and inverse outputs of the FTS 40 (u40-1and u40-2) signals S2and S4on direct and invernomuto FTS 42 (u 42-1and u42-2) signals S8and S6.

The unit is preset trigger frequency dividers, the scheme of which is shown in Fig, together with the divider 25 frequency provides two synchronization initial actuation of the dividers 26, 28, 29 and 33 of the frequency by 2 and divider 27 frequency 6 and the necessary mutual arrangement of the output signals on the time axis in the process. It is provided as follows. At power-charging the capacitors in the base circuits of transistors (Fig). The time constant of the charge circuit of the second capacitor is less than the first predetermined level of positive voltage at the output of the second transistor appears earlier than the first. The voltage output of the second transistor is supplied to the inputs R of the flip-flops in the dividers 26, 28, 29 and 33 of the frequency by 2 in divider 27 frequency of 6 and sets these triggers in the same (zero) original state. After this specified level output voltage appears at the output of the first transistor, this voltage is applied to the input R of the divider 25 of the frequency by two and provides it a work mode (frequency division). The first positive voltage swings at the output of this divider will ensure that the switch trigger in the rest of the frequency dividers, i.e. the synchronism of these factors.

The analyzer 1 status futuremusic n is prajini determines the voltage u 1and u2at the outputs of block 4 keys in quantum points and their values shall decide on the status of these outputs. There are 4 different States, including 2 state for clock time when the impulse TO, and 2 States for the moment when he acts TO:

1. TI, u1=+a, u2=0; 2. TI, u1=-and u2=0;

3. TI, u1=0, u2=+a; 4. TI, u1=0, u2=.

This takes into account that if some clock time one of the voltages u1or u2is +a or-a, the second voltage is necessarily equal to zero. In the analyzer 1 status futuremusic stress (figure 2) Comparators 10 and 11 convert bipolar signals u1and u2in unipolar pulses with logic levels. The threshold Comparators is set to logical zero (0.2 to 0.4 In). The elements 12 and 13 do NOT invert the signals at the outputs of the Comparators, the first inputs of a pair of elements 14 and 15 And a pair of elements 16 and 17 And are mutually inverse voltage. If this clock time valid clock pulse sequence TI, and this sequence is served on the upper circuit 2 element 18 OR the pulse arrives at the output of one of the first pair of elements And is 14 or 15. If at this clock time valid clock pulse consequently the STI TI, this pulse will be highlighted on the output of one of the elements of the other pair of elements And is 16 or 17. Thus, in the clock every time you receive a short pulse at the output of one of the four (14-17) elements And defining one of the above 4 conditions voltages u1and u2the outputs of the unit keys. Subsequent dilators 19-22 pulses form of short pulses of a single parcel of duration T0. The emergence of a single parcel at the output of the expander 19 pulses indicates the first voltage u1and u2the appearance of a single parcel at the output of the expander 20 shows the second state of the voltage u1and u2at the exit of the expander 21 is about the third state at the output of the expander 22 is about the fourth condition. In item 18 OR concatenated sequence TI and TI and generates a short sequence of clock pulses, following with a period of T0.

Direct the operation key unit 4 performs a logical unit 3 generating control voltages for the unit keys. On the basis of the voltages u1and u2at a given clock time, determining the value of output voltage phase modulator at this point (this determines the analyzer status futuremusic stress), and operating the modulating signal is in the next clock interval, logical unit generating control voltages for the unit key 2 forms the control voltage applied to the control inputs of analog switches 73-80, and provides opening required pair of analog switches in block 4 keys. This takes into account asked manipulation code that defines the correspondence between a combination of parcels of input signals uc1and uc2transmitted in a given clock interval, and the frequency of the output voltage of the modulator. In the frequency modulator adopted the following manipulation code:

uc10011
uc20101
fif2f3f1f4

Here it is assumed:

f1=f0-3· fd=f0-3/(4· T0), f2=f0-fd=f0-1/(4· T0),

f3=f0+fd=f0+1/(4· T0), f4=f0+3· fd=f0+3/(4· T0),

f0- carrier frequency provided by the generator 8 by the carrier.

The advantage of this manipulation code is that when applying to the first input of the modulator, Ural branch of the nya logical zero manipulation of the second input will ensure the use of only frequency f 2and f3i.e. single-channel transmission with modulation index m=0.5, and when applying to the first input of the level logical units and manipulation on the second input of the used frequency f1and f4that provides single-channel transmission with index m=1.5. When applying to both of the input modulating signal is provided by a two-channel transmission with Raman seal channels.

To ensure their functions when the selected manipulation code logical block 3 generating control voltages for the unit keys must have the following state table.

The state table of a logical block 3 generating control voltages for the unit keys

td align="center"> 1
no PP.X1X2Y1Y2Y3Y4Z1Z3Z5Z7Z2Z4Z6Z8
100100010000100
20001000 1001000
300001010001000
400000101000100
501100010001000
601010001000100
701001001001000
80100 0110000100
910100000010010
1010010000100001
1110001000100010
1210000100010001
1311100000010001
141010000100010
1511001000010010
1611000100100001

In this table, X1and X2- the values of the input modulating parcels uc1and uc2inputs 1 and 2, logical block 3 generating control voltages for a block of keys, which are the inputs of the modulator; Y1 - Y4 - logic levels on the outputs of the analyzer 1; Z1, Z3, Z5, Z7 - logic levels on the outputs of the elements, respectively, 65, 67, 69, 71 OR; Z2, Z4, Z6, Z8 - logic levels on the outputs of the elements, respectively, 66, 68, 70, 72 OR logical block 3 generating control voltages for the unit keys. The structure of the logical block 3 generating control voltages for the unit keys (figure 4) provides an implementation of this state table.

the Work input of the frequency modulator is based on a smooth rotation of the vector of the output voltage without breaking phase at the boundaries of the parcels in accordance with the binary signals at the input of the modulator. During one parcel vector output voltage rotated at an angle of ±π /2, which corresponds to the frequency deviation fd=1/(4· T0) and index of frequency modulation m=0,5 (minimum frequency shift, as in the signal MMC), or at an angle of ±3π /2, which corresponds to the frequency deviation fd=3/(4-T0) and index of frequency modulation m=1.5. Frequency parcels while taking the values of f0±1/(4· T0and f0±3/(4· T0).

The necessary rotation of the vector is the selection of forms futuremusic voltages u1and u2at the inputs of the amplitude and phase modulators 5 and 6 (figure 1). If futuremouse voltage during one parcel change with frequency π /(2· T0and have a mutual phase shift of ±π /2, that is, for example,

u1=±a· sin(π · t/2· T0), u2=±a· cos(π · t/2· T0)

or

u1=±a· cos(π · t/2· T0), u2=±a· sin(π · t/2· T0),

while one parcel phase of the output voltage of the modulator will change to +π /2 or -π /2 (as in the modulator MMS). If futuremouse voltage change with frequency 3π /(2· T0and also have a mutual phase shift of ±π /2, while sending T0the phase of the output voltage will change by +3π /2 or 3π /2. Still the way shape selection (frequency and phase) pair futuremusic voltages u1and u2at the inputs of the amplitude and phase modulators 5 and 6 is required rotation phase of the output voltage during each parcel and a parcel at the output of the modulator with the desired frequency.

The principle of operation of two-input of the frequency modulator is illustrated a time chart Fig. When the enable input of the frequency modulator unit 2 form a continuous periodic sequence of signals and sequences of clock pulses generates 8 sequences of signals Siand two sequences of clock pulses (Fig). Each of the signals Siis supplied to the signal input of the corresponding key in a block of 4 keys. Initially, all the keys are closed, the voltage at their outputs u1and u2is equal to zero. The outputs of the Comparators 10 and 11, the voltage is also zero, and the outputs of the inverters 12 and 13 will be the voltage level of the logical unit. Upon receipt of the clock pulse input 3 or 4 analyzer 1 status futuremusic voltage (the input element 18 OR appears to the clock pulse output of one of the elements And is a 15 or 17, depending on whether the pulse (TI or TI) will go first. Suppose first came the impulse sequence TI, and a clock pulse is havelse output element 17 And. You will see a single parcel of duration T0at the output of the expander 22 pulses, which corresponds, as mentioned above, the 4th state of stresses u1and u2. The numbers of States in each clock time is indicated on Fig (string yi). From the output of the expander 22 pulse unit package arrives at the second input elements 55, 56, 63 and 64 And a logical block 3 generating control voltages for the unit key, and only these four elements are activated at a given clock interval. Suppose that a given clock interval corresponds to the first parcels of modulating signals. In this heartbeat interval for modulating inputs X1and X2(uc1and uc2) apply a single parcel (see Fig). Single parcel X1through the first input of logic unit 3 generating control voltages for the unit keys (input item 43) is supplied to the first inputs of the elements 47 and 48 And, as a single parcel X2via a second input of logic unit 3 generating control voltages for the unit key is supplied to the second inputs of the elements 46 and 48 I. Thus, a single parcel will appear at both inputs of the element 48, And the output of this item, there will be a single parcel, which will go to the first inputs of the elements 58, 60, 62 and 64 And. When this individual parcels will be on both WMO is Ah element 64 And, so with the release of this single element sending through the elements 69 and 72 OR will act on the 5-th and 8-th () outputs a logical block 3 generating control voltages for the unit keys. Next, the parcel will be transferred to the control inputs of analog switches 77 and 80 in block 4 keys; these keys will open, and through them pass signals, respectively, S5and S8in certain phases. These phases are determined from the time charts of signals at Fig. Appropriate signals are displayed on the charts, respectively, u1and u2(Fig) in the first clock interval.

At the end of the first clock interval, i.e. the second clock time, the voltage u1and u2estimated again in the analyzer 1 status futuremusic stress. Input 1 analyzer 1 status futuremusic voltage which is supplied with voltage u1the voltage is, therefore, at the output of the comparator 10 will receive a zero voltage at the output of the element 12 will NOT appear a single voltage that activates the element 15 I. In this clock time appears in clock pulse sequence TO that through the third analyzer input 1 status futuremusic voltage is supplied to the second inputs of the elements 14 and 15 Acting On the element 15 And will match a single voltage, and a clock pulse arrives at the output is lementa 15 And. At the output of the expander 20 pulses will be generated a single pulse T0(the second voltage u1and u2). This pulse is fed to the 4th input of logic unit 3 generating control voltages for the unit key and then on the second inputs of the elements 51, 52, 59 and 60 of this unit. On the 1st and 2nd inputs logical block 3 generating control voltages for the block of keys in this clock interval are input modulating signals: zero voltage X1(uc1) acts on 1-d input and a single voltage X2(uC2- on the 2nd entrance. Zero parcel X1through the element 43 is NOT supplied to the first inputs of the elements 45 and 46 I. Single parcel X2the effect on the second input elements 46 and 48 Acting On the inputs of the element 46 And will match a single stress, resulting clock pulse from the output of this element is supplied to the first inputs of the elements 50, 52, 54 and 56 Acting On the inputs of the element 52 And is provided by the coincidence of a single voltage, and the output of this item, there will be a single pulse T0; the same pulse will appear at the outputs of the elements 67 and 68 OR, i.e. on the 3-m and 4-m (schema) outputs a logical block 3 generating control voltages for the unit keys. These pulses are received at the control inputs of keys 75 and 76 (3rd and 4th account) in order to open these keys. Through the key 75 will be element of S3and through the key 76 is an element of S4. The shape of these signals defined according pig for clock interval after the current clock time TI shown in Fig (u1and u2, clock interval 2).

Continuing the same reasoning, for the next clock interval, obtain timing diagrams futuremusic voltages u1and u2arriving at the inputs of the amplitude and phase modulators 5 and 6 two-input of the frequency modulator. Next usual work items 5-9 input of the frequency modulator included in the restrictive part of the claims. The voltage u1influencing the modulating input of the first amplitude-phase modulator 5, changes the amplitude and phase concerns the voltage at its output; depending on the polarity of the u1the phase of the output voltage amplitude of the phase modulator 5 can take the values 0 or π and the amplitude changes according to the law of the modulating voltage. The voltage u2the effect on the modulation input of the second amplitude-phase modulator 6 and also changes its amplitude and phase; phase depending on the polarity of the u2can take values π /2 or 3 π /2. The addition of the output voltage amplitude and phase modulators in the adder 9 gives the output is Noah voltage of the modulator. The amplitude of this voltage is constant, as determined by the relations:

- frequency panoramaweg voltage Ω1=π /2T0

- frequency panoramaweg voltage Ω2=3π /2P0

and the phase varies linearly with time over the duration of each package:

- frequency panoramaweg voltage Ω1=π /2T0

the frequency panoramaweg voltage Ω2=3π /2P0

Depending on the frequency of the voltages u1and u2at this clock interval, the phase of the output voltage during one parcel may vary on an angle π /2 or 3π /2, which corresponds to the frequency offset of the parcel from the values of f01/4T0) or, respectively, 3/(4T0). Frequencies parcels output voltage of the modulator is indicated on the timing diagram uoFig. Comparison of combinations of transmitted symbols with a frequency of the output voltage of the modulator at each clock interval T0shows that between them there is one mapping defined above manipulation code. Thus, the proposed two-input frequency modulator providing the em 4-frequency FM without breaking phase at simultaneous transmission of two binary digital signals on the basis of Raman seal with the specified manipulation code. In addition, the input of the frequency modulator provides work in single channel mode. When set to the modulation input X1the logic level zero, the modulator operates on the second input (X2using futuremouse voltage only at low frequencies Ω1and forming at the output of 2-FM frequency oscillation without breaking phase with the modulation index of 0.5. If the input X1to establish the level of logical units, the modulator operates at a second input, and uses futuremouse voltage with frequencies Ω2; the output of the modulator thus formed 2-FM frequency oscillation without breaking phase with the modulation index of 1.5. In all modes of two-input frequency modulator provides a compact range of the output signal. Calculations show that when in dual-channel mode, the real width of the spectrum (on the power level of 99%), per channel, is of 1.27-V (a slight increase compared to MMS). Working with a modulation index of 1.5 gives the actual width of the spectrum 2,92-V, i.e. a threefold increase of the modulation index required an increase of the belt is less than 2.5 times. The proposed frequency modulator has other advantages modulator MMS, above.

1. Input frequency modulator comprising a generator carrier, Phaser,two amplitude-phase modulator and the adder, moreover, the output of the carrier generator connected to the first input of the first amplitude-phase modulator and to the input of the phase shifter, the output of the phase shifter connected to the first input of the second amplitude-phase-modulator outputs the amplitude and phase modulators are connected respectively with the first and second inputs of the adder, the output of which is the output of two-input frequency modulator, characterized in that it includes the analyzer status futuremusic stresses, block the formation of a continuous periodic sequence of signals and sequences of clock pulses, the logic unit generating control voltages for the unit keys and unit keys, with the first two inputs of the logic unit generating control voltages for a block of keys, which served binary modulating signals are the inputs of two-input frequency modulator, four other input of logic unit generating control voltages for the unit keys are connected respectively with the four outputs of the analyzer status futuremusic stresses, the eight outputs of logic unit generating control voltages for the unit keys are connected with the first eight inputs of the block of keys, the second eight inputs of block keys are connected to the eight outputs of the shaping unit h is discontinuous periodic sequence of signals and sequences of clock pulses, the first output block of keys is connected with the second input of the first amplitude-phase modulator and to the first input of the analyzer status futuremusic voltage, the second output unit of the keys connected with the second input of the second amplitude-phase modulator and the second input of the analyzer status futuremusic voltage, and third and fourth inputs of the analyzer status futuremusic voltages are connected respectively to the other two outputs of block formation of continuous periodic sequence of signals and sequences of clock pulses.

2. The modulator according to claim 1, characterized in that the analyzer status futuremusic stress includes two Comparators, two of the item, the four elements And one element OR four extender pulses, and the inputs of the Comparators are respectively the first and second inputs of the analyzer status futuremusic voltage, the output of the first comparator is connected with the input of the first element and to the first input of the first element And the output of the second comparator is connected with the input of the second element and to the first input of the third element And the second inputs of the first and second elements And connected to the first input of the OR element, which is the third input analyzer status futuremusic voltage, the second input of the third of the th and fourth elements And connected with the second input element OR which is the fourth input of the analyzer status futuremusic voltage, the output of the first element is NOT connected to the first input of the second element And the second element is NOT connected to the first input of the fourth element And the outputs of all elements And are connected respectively to the first inputs of dilators pulses, the output element OR is connected with the second inputs of all of the extenders pulses, and outputs extenders pulses are output analyzer status futuremusic stress.

3. The modulator according to claim 1, characterized in that the block formation of continuous periodic sequence of signals and sequences of clock pulses includes oscillator, five frequency divider by two frequency divider for a six-unit preset trigger frequency dividers, two differentiating circuit with a limit on the minimum, two Exclusive OR element, four driver sawtooth voltage and four driver voltage sine wave and the output of the master oscillator is connected with the first inputs of the first frequency divider by two and a frequency divider by six, the outputs of the first frequency divider by two connected respectively to the first inputs of the second and third frequency dividers on two, the outputs of which are connected respectively with p the pout inputs of XOR, the first output of the frequency divider of six connected with the inputs of the first differential circuit with a limit on the minimum, the second driver of the sawtooth voltage and the fourth frequency divider by two, the second output of the frequency divider of six connected with inputs of the second differentiating circuit with a limit on the minimum of the third driver of the sawtooth voltage and the fifth frequency divider by two, the first output unit preset triggers of frequency dividers connected to the second input of the first frequency divider by two, the second output unit preset triggers of frequency dividers connected with the second inputs of the second, third, fourth and fifth frequency divider by two and with the second the input of the frequency divider at six, the outputs of the differentiating circuits with a limit on the minimum are the first two outputs of the block formation of continuous periodic sequence of signals and sequences of clock pulses, the output of the fourth frequency divider by two is connected with the second input of the first Exclusive OR element, the output of the fifth frequency divider by two is connected with the second input of the second Exclusive OR element, the output of the first Exclusive OR element is connected to the input of the first driver of the sawtooth voltage, the output of the second element of the Claim is causee OR is connected to the input of the fourth driver of the sawtooth voltage, the outputs of the shapers of the sawtooth voltage are connected respectively to the inputs of the shapers of the voltage sine wave, direct and inverted outputs of which are the outputs of block formation of continuous periodic sequence of signals and sequences of clock pulses.

4. The modulator according to claim 1, characterized in that the logical unit generating control voltages for the block of keys is performed on two elements are NOT, twenty elements And the eight elements OR, the first input of logic unit generating control voltages for the block of keys is connected to the input of the first element and NOT with the first inputs of the third and fourth elements And the second input of logic unit generating control voltages for the block of keys is connected to the input of the second element with the second inputs of the second and fourth elements And the output of the first element is NOT connected with the first inputs of the first and second elements And the output of the second element NOT connected with the second inputs of the first and third elements And the output of the first element And connected with the first inputs of the fifth, seventh, ninth and eleventh elements And the output of the second element And is connected to the first inputs of the sixth, eighth, tenth, and twelfth elements And the output of the third element And soy is inalsa with the first inputs of the thirteenth, fifteenth, seventeenth and nineteenth elements And the fourth output element And is connected to the first inputs of the fourteenth, sixteenth, eighteenth and twentieth elements, And the third input of logic unit generating control voltages for the block of keys is connected with the second inputs of the fifth, sixth, thirteenth and fourteenth elements And the fourth input of logic unit generating control voltages for the block of keys is connected with the second inputs of the seventh, eighth, fifteenth and sixteenth elements And the fifth input of logic unit generating control voltages for the block of keys is connected with the second inputs of the ninth, tenth, seventeenth, and eighteenth elements And the sixth input logical unit generating control voltages for the block of keys is connected with the second inputs of the eleventh, twelfth, nineteenth and twentieth elements And the output of the fifth element And is connected to the first inputs of the first and fourth elements OR the output of the sixth element And is connected to third inputs of the first and second elements OR the output of the seventh element And connected with the first inputs of the second and third elements OR the output of the eighth element And is connected to third inputs of the third and fourth elements OR the output of the ninth element And with distesa with the second inputs of the first and second elements OR the tenth output element And is connected to the fourth inputs of the second and third elements OR the output of the eleventh element And connected with the second inputs of the third and fourth elements OR the output of the twelfth element And is connected to the fourth inputs of the first and fourth elements OR the output of the thirteenth element And connected with the first inputs of the sixth and seventh elements OR the output of the fourteenth element And connected with the second inputs of the seventh and eighth elements OR the output of the fifteenth element And is connected to the fourth inputs of the fifth and eighth elements OR the output of the sixteenth element And is connected to the second inputs of the fifth and sixth elements OR the output of the seventeenth element And is connected to third inputs of the fifth and sixth elements OR output eighteenth element And is connected to the fourth inputs of the sixth and seventh elements OR exit the nineteenth element And is connected to third inputs of the seventh and eighth elements OR exit the twentieth element And connected with the first inputs of the fifth and eighth elements OR, as the outputs of the elements OR are the outputs of logic unit generating control voltages for the block of keys.

5. The modulator according to claim 1, characterized in that the block of keys consists of eight analog switches, each of the eight upravlyayushchego block of keys connected to the control input of the corresponding analog switch, each of the eight signal inputs of the block of keys is connected to the signal input of the corresponding analog switch, the outputs of the first, third, fifth and seventh analog switches connected to each other and form a first output unit key outputs of the second, fourth, sixth and eighth analog switches are also connected to each other and form a second output unit keys.



 

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