Reliable bit circuit for memorizing device of replaceable printer component

FIELD: engineering of printers and memory devices for printers.

SUBSTANCE: in accordance to suggested method for detecting error in data, received from memory device of replaceable printer component, ensured is first evenness control bit, associated with first data element. First data element and first evenness control bit are stored in memorizing device. Printer includes a set of electro-conductive lines. Memorizing device includes a set of bits. At least one of electro-conductive lines is associated with each bit. First data element and first evenness control bit are read from memorizing device. Electric test of at least one of electro-conductive lines is performed. Error is identified in first data element on basis of first evenness control bit, read from memorizing device, and electric test. Other inventions of group envelop printing system, two variants of realization of replaceable printer component for printing system and method for storing information in replaceable printer component are provided.

EFFECT: creation of memory device with increased reliability, timely detection and correction of errors in replaceable components of printers ensures their continuous operation.

5 cl, 7 dwg

 

The technical field to which the invention relates.

The present invention relates to printers and storage devices for printers. More specifically, the invention relates to a reliable bit scheme for a memory device replaceable component of the printer.

Prior art

The technical field of inkjet technology is relatively well developed. Commercial products such as computer printers, graphics plotters and Fax machines are implemented using inkjet technology to create printed media. Normally inkjet image is formed according to the exact placement on the print medium ink drops emitted by the device for generating droplets of ink, known as the jet printhead. The device is an inkjet printhead includes at least one printhead. Typically, the device is an inkjet printhead supported on a movable carriage which moves in the transverse direction above the surface of the print medium and is controlled so as to emit drops of ink at appropriate times pursuant to command of a microcomputer or other controller, in which the synchronization of the application of ink drops is intended to correspond to the pattern of pixels pechati the CSO image.

Inkjet printers have at least one feeder ink. Feeder ink includes an ink container having an ink reservoir. Feeder ink can be placed together with the device of an inkjet printhead in an inkjet ink cartridge or pen or can be placed separately. When the feeder ink placed separately from the device inkjet printhead, users can replace the feeder ink without replacement inkjet printhead. Then the device is an inkjet printhead replace at the end or near the end-of-life printhead, and when not replace the feeder ink.

Modern systems printers typically include one or more replaceable components of printers, including inkjet ink cartridges, devices, inkjet printheads and ink supply. In some existing systems, these replaceable components of printers are equipped with an internal storage device in order to transmit the information to the printer about the replaceable component. Built-in storage device, for example, inkjet ink cartridge, you can store information such as the type of the pen unique ID of the pen, the ink filling level, marketing information, as well as others who Gaya information. Such a storage device may also store other information about the ink container, such as information about the current ink level. Information about the ink level can be transmitted to the printer to indicate the amount of remaining ink. The user can monitor the information about the ink level, and to anticipate the need to replace the emptied container of ink.

If data received by the printer from a storage device component of the printer contains an error, the printer performs the wrong action or may be unable to use the printer. This error may be the result of a short circuit or break in the address line connecting the storage device with other components of the printer such as the printer controller, or due to some other issues.

It is desirable to have a diagram of the storage device that is more reliable than modern circuit memory devices used in the replaceable components of the printer in order to detect and correct errors and to ensure smooth operation.

The invention

The present invention provides a method designed to detect errors in the data received from the storage device replaceable component of the printer. The memory device includes all the I many bits. The method includes providing the first bit of the parity associated with the first data item. The first data element and the first bit of the parity stored in the storage device of the printer. The printer includes multiple conductive lines. At least one of the conductive lines associated with each bit. The first data element and the first bit of the parity read from the storage device. Perform electrical test, at least one of the conductive lines. The error in the first data item identified based on the first bit of the parity read from the storage device, and electrical test.

One aspect of the invention is directed to the print system comprising an inkjet printhead for selective deposition of droplets of ink on the surface of the carrier. Feeder ink stores ink supplied to an inkjet printhead. The storage device stores the first bit of the parity and the first data element. First the parity bit associated with the first data item. A processor coupled with the storage device using the set of conductive lines. The processor responds to the output signal of the storage device. The processor performs an electrical test at IU is e, one of the conductive lines. The processor identifies the error in the first data item based on the first bit parity and electrical test.

Another aspect of the invention is directed to an inkjet ink cartridge for an inkjet printing system having a controller. Inkjet ink cartridge includes a device inkjet printhead having at least one inkjet printhead that selectively guarding the ink droplets on the print media. Feeder ink stores ink supplied to an inkjet printhead. The information storage device stores the first bit of the parity and the first data element. First the parity bit associated with the first data item. First the parity bit is used by the controller in conjunction with an electric test of the conductive lines connected to the information storage device, to identify errors in the first data element.

Another aspect of the invention is directed to a storage device for a replaceable component of an inkjet printer of the print system. The memory device includes a semiconductor crystal. On semiconductor crystal formed many schemes. Each schema is associated with status bits in the storage device is ve and determines the state of the bit. The storage device stores the first data item that provides identifying information regarding the replaceable component of an inkjet printer. The first data element is used by the printing system to determine whether the replaceable component of an inkjet printer suitable for use in the print system. The schema associated with the first data item, are, essentially, about the center of the semiconductor crystal.

List of drawings

Figure 1 is an electrical block diagram of the main components of an inkjet printer in accordance with the present invention.

2 is a diagram illustrating read-only memory (ROM) of the printer depicted in figure 1.

Figure 3 is a table illustrating information stored in a storage device, inkjet ink cartridge in accordance with the present invention.

Figa - illustration of a circuit to determine the status of the fuse bits of the storage device, inkjet ink cartridge of the present invention.

Figw - illustration of a circuit for determining the state of the masked bits of the storage device inkjet cartridge of the present invention.

Figa is a table illustrating two examples of the assignment of bits in the storage device, inkjet ink cartridge in accordance with the present invention.

F. GV - table illustrating the assignment of bits in figa after an error occurred.

Description of the preferred embodiments

In the following detailed description of preferred embodiments reference is made to the accompanying drawings, which form part of the description, and which illustrates specific embodiments of which may be applied to the present invention. It should be understood that there may be used other ways to implement and can be done in a constructive and logical changes, without going beyond the scope of the present invention. Thus, the following detailed description should not be construed in a limiting sense, and the scope of the present invention defined by the attached claims.

Figure 1 is an electrical block diagram of the main components of an inkjet printer in accordance with the present invention. Inkjet printer 10 includes a removable inkjet ink cartridge 12, which includes a device 14 inkjet printhead, integrally mounted storage device 16 and the device 26 of the ink supply. Inkjet ink cartridge 12 is removable from the printer 10 with the connection through the interconnect 18. The device 14 inkjet printhead includes, at m is re, one print head 14A. Storage device 16 may include many types of storage devices, including RAM and ROM) and electrically erasable programmable ROM (EEPROM), and stores data associated with the device 14 of the inkjet printhead and the device 26 of the ink supply. In one embodiment, the storage device 16 includes recorded in the manufacture of the data recorded by the printer data. In one embodiment, the storage device 16 includes 26-bit ROM 16A, with 13 fuse bits and 13 masked bits. In an alternative embodiment, all 26 bits are fuse bits. In another embodiment of the present invention all 26 bits are masked bits. ROM 16A may also include different total number of bits than 26 bits. The advantage of using both fusible and masked bits is that it can be reduced the memory size ROM 16A. Each fuse bits can be set using burnout resistor in the circuit 400A shown in figa), representing fuse bits. Each masked bit can be set by adding a resistor in the circuit 400 shown in figv). In one embodiment, the ROM 16A combined with the device 14 jet p is Catoosa head. In an alternative embodiment, the ROM 16A may be combined with the device 26 of the ink supply. Specialists in the art it will be clear that instead of embedding device 14 of the inkjet printhead and the device 26 of the ink supply in the composition of the inkjet ink cartridge 12, the device 14 of the inkjet printhead and the device 26 of the ink supply can be placed separately and may include a separate storage device.

The printer includes a line 20 connection for communication between the ink-jet ink cartridge 12 and the controller 34. More specifically, line 20 communications includes address lines 20A, the first line of 20V resolution encoding, the second line 20C-resolution encoding and output line 20D, all of which are connected with ROM 16A. In one embodiment, the address lines 20 include the 13 address lines. The first line of 20V resolution coding is used to select the fuse bits in ROM 16A and the second line 20V resolution coding is used to select the masked bits in ROM 16A. Address line 20A are used to select a specific fuse bits or masked bits. The value of the selected fuse or masked bits is read using a read output signal output line 20D.

The device 14 inkjet printing is melting head, the storage device 16 and the device 26 of the ink supply connected to the controller 34, which includes both electronic circuits and software and hardware to control the various components of the printer or individual nodes. Procedure 35 print management, which can be embedded in the printer driver causes the read data from the storage device 16 and regulates the operation of the printer in accordance with the data selected from the storage device 16. The controller 34 controls the device 14 of the inkjet printhead and the device 26 of the ink supply so that the ejection of droplets of ink was carried out in a controlled manner on the circuit carrier 32.

The main CPU 36 is connected to the controller 34 and includes a Central processing unit (CPU, CPU) 38, and the software driver 40 of the printer. The monitor 41 is connected to the main processor 36 and is used to display various messages that serve as status indicators inkjet printer 10. Alternative printer 10 can be configured for stand-alone or network in which messages are displayed on the front panel of the printer.

Figure 2 presents a diagram illustrating ROM 16A of figure 1 in more detail. ROM 16A includes a semiconductor crystal 60, having a set of pads 62. Address Lin and 20A, the first line (E1) 20V resolution encoding, the second line (E2) 20C-resolution encoding and output line 20D is connected with a semiconductor crystal 60 through contact pads 62. Address line 20A includes 13 address lines (A1-A13). In one embodiment, the ROM 16A includes other electrical connections (not illustrated), including ground connections.

Figure 3 shows a table illustrating the information stored in ROM 16A in accordance with the present invention. Table 300 includes identifiers 302 address lines, identifiers 304 lines of resolution encoding identifiers A and B types of bits (together referred to as identifiers 306 types of bits), the values of bits 308 and field 310. Table 300 is divided into part 312 and part 314. Part 312 table 300 represents the information associated with the fuse bits as specified by ID A type "fuse". Part 314 table 300 represents the information associated with the masked bits, as specified by ID V type "masked". As mentioned above, instead, to use as a fuse, and the masked bits, all bits in ROM 16A can be fuse bits or all bits in ROM 16A can be masked bits. Each of the identifiers 302 address lines is one of hell of the forest line and corresponds to either fuse, either masked bit. As fuse, and the masked bits are numbered 1-13, indicating a particular address line 20A, associated with a bit. Identifiers 304 lines of resolution coding point line 20B or 20C resolution encoding, which must be installed in order to choose the appropriate bit. "1" IDs 304 lines of resolution coding corresponds to the first line 20 In resolution encoding, which is used to select the fuse bits. "2" IDs 304 lines of resolution coding corresponds to the second line 20C-resolution encoding, which is used to select the masked bits.

Fuse bits 1-13 and masked bits 1-13 divided into many fields 310. Each bit in a particular field 310 includes the value of bits 308. When this bit is set, it has the value specified in the corresponding value 308 bits. When this bit is not set, it is set to 0. In one embodiment, fuse bits 1-13 and masked bits 1-13 installed during manufacture of the ROM 16A.

Field 310A includes a fuse bit 13. In one embodiment, fuse bit 13 not used for data storage, thus, the field 310A includes the letters "NA" (i.e., not assigned).

Field V filling ink includes fuse bit is 10-12. In one embodiment, fuse bits 10-12 provide a reference level or the trigger level in order to determine when it should be displayed warning small amount of ink.

Field 310C parity includes fuse bits 9. In one embodiment, fuse bit 9 bit parity used in connection with the bits corresponding field 310D marketing. In an alternative embodiment, fusible bit 9 bit parity used in connection with many bits field 310. Fuse bits 9 can also be used in connection with bits of the storage device associated with another component of the printer, such as device 26 ink.

Field 310D marketing includes fuse bits 6-8. In one embodiment, fuse bits 6-8 are used to identify whether to be used in ink jet cartridge in a particular printer.

Field E includes fuse bit 5. In one embodiment, fuse bit 5 is not used for data storage, thus, the field E includes the letters "NA" (i.e., not assigned).

Field 310F uniqueness of the pen includes a fuse bits 2-4. In one embodiment, fuse bits 2-4 represent a random number that uniquely identifies inkjet ink the cartridge, that allows the controller 34 of the printer to determine when you installed a new ink cartridge.

Field 310G includes fuse bit 1. In one embodiment, fuse bit 1 is not used for data storage, thus, the field 310G includes the letters "NA" (i.e., not assigned).

Field N includes masked bits 10-13. In one embodiment, the masked bits 10-13 not used for data storage, thus, the field N includes the letters "NA" (i.e., not assigned).

Field 310I includes masked bit 9. In one embodiment, the masked bit 9 bit parity used in connection with a bit that matches 310J type pen. In an alternative embodiment, the masked bit 9 bit parity used in connection with many bits field 310. Masked bit 9 can also be used in connection with bits of the storage device associated with another component of the printer, such as device 26 ink.

Field 310J type pen includes masked bits 5-8. In one embodiment, the masked bits 5-8 provide identification of the type inkjet ink cartridge, which is associated with the storage device.

Field K uniqueness pen includes masked bits 14. In one embodiment, the masked bits 1-4 represent a random number that uniquely identifies a particular inkjet ink cartridge that allows the controller 34 of the printer to determine when you installed a new ink-jet ink cartridge.

On Figa shows a schematic illustration for determining the status of the fuse bits in ROM 16A. The circuit 400 includes a first input (Eop) 402-resolution encoding, output (id_out) 404, an address input 406, the transistor 408, a resistor 410, the transistor 412, a second input (_off) 414-resolution encoding, transistor 416 and the grounding pin (p_gnd) 418. Address input 406 is connected to one of the address lines 20A (see figure 1). The first input (Eop) 402-resolution encoding is connected to the first line 20 In resolution encoding (depicted in figure 1). The second input (_off) 414-resolution encoding is connected with the second line 20C resolution encoding (see figure 1). The output 404 is connected to the output line 20D (see Fig 1).

In one embodiment, each of the transistors 408, 412 and 416 is a field-effect transistor (FETS, FET). Address input 406 is connected to the drain of transistor 408. The first input 402-resolution encoding is connected to the gate of the transistor 408. The source of transistor 408 is connected to the gate of the transistor 412 and the drain of transistor 416. The gate of the transistor 416 is connected to a second input 414-resolution encoding. Flow t is ancestor 416 is connected to the source of transistor 408 and the gate of the transistor 412. The source of transistor 416 is connected to the grounding conductor 418. The resistor 410 is located between the output 404 and the drain of transistor 412. The source of transistor 412 is connected to ground 418.

Fuse bits in ROM 16A, such as bits, represented by the diagram 400A, is read by setting the high level at the first input 402-resolution coding, installation of the high level of the address inputs 406 and reading the output signal 404. A high level at the first input 402 permits the encoding is set by the controller 34 by setting a high level on the first line of 20V resolution encoding. A high level on the address line 406 is set by the controller 34 by setting a high level on the address line 20A, which is connected to the address input 406. The output voltage at the output 404 is read by the controller 34 using the read voltage on the output line 20D.

Transistor 408 acts as a logical element AND with inputs 402 and 406. If both the inputs 402 and 406 high level, the current flows through the transistor 408, opening the transistor 412. The transistor 412 acts as a control transistor controlling the output 404. If the resistor 410 burned, the output voltage 404 is high, indicating a logical 1. If the resistor 410 is not ruined, the output voltage 404 is low, indicating a logical 0. The transistor 416 is used as activatestate, in order to prevent unlocking of the transistor 412 the leakage current of the transistor 408, when the transistor 412 must be locked. The transistor 416 is unlocked by setting a high level on the second input 414-resolution encoding. When unlocking the transistor 416 removes the current from transistor 408 to the ground.

In one embodiment, each transistor 408 and 416 has a length of about 4 microns, and a width of about 15.5 μm, and transistor 412 has a length of about 4 microns, and a width of about 600 microns. In one embodiment, the resistor 410 has a resistance higher than about 1000 Ohms, when burned, and the lower resistance of approximately 400 Ohms when not burned. In addition to burnout resistor 410 other methods can be used to create an open circuit to determine the status bits in ROM 16A, including mechanical cutting, laser cutting and other methods.

On FIGU presents illustration of a circuit for determining the state of the masked bits in ROM 16A. Diagram 400V, essentially, is the same as the circuit 400 depicted in figa, except that the resistor 410 is replaced by a switch 420, and the transistor 422 includes other characteristics in comparison with the transistor 412. In one embodiment, the switch 420 is not an actual physical switch, and is either p is OUTSTA, or absence of the resistor. If the resistor is present on the place of the switch 420, the resistor has sufficient resistance to act as an open circuit between the output 404 and transistor 422. If the resistor is present in the switch 420, there are no additional resistance between the output 404 and transistor 422. In one embodiment, the transistor 422 is a field-effect transistor (PT) with a length of approximately 4 microns and a width of about 100 microns.

Address input 406 is connected to one of the address lines 20A (see figure 1). The first input 402-resolution encoding is connected with the second line 20C resolution encoding (see figure 1). The second input 414 resolution encoding is connected to the first line 20 In resolution encoding (see figure 1). The output 404 is connected to the output line 20D (see Fig 1).

Address input 406 is connected to the drain of transistor 408. The first input 402-resolution encoding is connected to the gate of the transistor 408. The source of transistor 408 is connected to the gate of the transistor 422 and the drain of transistor 416. The gate of the transistor 416 is connected to a second input 414-resolution encoding. The drain of transistor 416 is connected to the source of transistor 408 and the gate of the transistor 422. The source of transistor 416 is connected to the grounding conductor 418. The switch 420 is located between the output 404 and the drain of the transistor 422. The source of transistor 422 is connected to contact the Ohm grounding 418.

The masked bits in ROM 16A, such as bits, represented by the diagram 400 is read by setting the high level at the first input 402-resolution coding, installation of the high level of the address inputs 406 and reading the output signal 404. A high level at the first input 402 permits the encoding is set by the controller 34 by setting a high level on the second line 20C-resolution encoding. The high level of the address input 406 is set by the controller 34 by setting a high level on the address line 20A, which is connected to the address input 406. The output voltage at the output 404 is read by the controller 34 using the read voltage on the output line 20D.

Transistor 408 acts as a logical element And inputs 402 and 406. If both the inputs 402 and 406 high level, the current flows through the transistor 408, opening the transistor 422. Transistor 422 acts as a control transistor controlling the output 404. If the switch 420 is open (i.e. the resistor is present), the output voltage 404 is high, indicating a logical 1. If the switch 420 is closed (i.e. the resistor is not present), the output voltage 404 is low, indicating a logical 0. The transistor 416 is used as an active interchange, in order to prevent unlocking of the transistor 422 a leakage current of the transistor 408, when the transistor 422 must be locked. The transistor 416 is unlocked by setting a high level on the second input 414-resolution encoding. When unlocking the transistor 416 removes the current from transistor 408 to the ground.

In ROM 16A of the present invention fusible and masked bits can be further classified as either functional or informational. Field of functional bits must match the values expected by the printer to work correctly. An example of a functional field bits field is 310J type pen. If the bits corresponding field 310J type pen point type inkjet ink cartridge, which is not compatible with the printer, the printer can disable inkjet ink cartridge. Thus, the error in the field 310J stylus-type could make the printer mistakenly disable inkjet ink cartridge. Field information bits are not critical for proper operation and can be ignored, or can be taken action on the basis of incorrect information in the information bits, without causing a work stoppage. Examples of fields of information bits include field 310F and K uniqueness of the pen.

Short circuit caused by accident, ink ("ink short circuit") in ROM 16A inkjet cartridge, generally occurs more frequently at the edges of the semiconductor to which Estella 60 (shown in figure 2). Pads 62, which are located near the edges of the semiconductor crystal 60, tend to undergo corrosion, potentially causing electrical failures. In one embodiment, the functional bits and other important bits, such as bits of parity are to the center of the semiconductor element 60, to reduce the likelihood of ink short circuits on these bits and, thus, to provide a more reliable ROM 16A. In one embodiment, bits 310D marketing, bits 310J type pen and bits 310C parity are, essentially, about the center of the semiconductor crystal 60.

In one embodiment, to further increase the reliability ROM 16A inkjet ink cartridge, in accordance with the present invention bits parity assigned to fields significant bits, including the fields of functional bits. As shown in figure 3, bit 310C parity assigned to the field 310D bit of marketing, and bit 310I parity assigned to the field 310J bits type pen. Using bits of parity, such as bits 310C and 310I parity, to improve the reliability ROM inkjet ink cartridge, discussed in more detail below with reference to figa and figv.

On figa presents a table illustrating two examples of what the purpose of the bits in the ROM inkjet ink cartridge in accordance with the present invention. The table includes rows 502 and 504 and columns 506 and A-D. Column 506 includes the value of a bit of parity for each example, such as bits 310C or 310I parity. Columns A-D include the values of the bits in the field of data bits for each example, such as a field 310D marketing or field 310J type pen. In example 1, shown in row 502, the parity bit is set to 0, bit 1 is set to 0, bit 2 is set to 0, bit 3 set to 1 and bit 4 is set to 1. In example 2, shown in row 504, the parity bit is set to 1, bit 1 is set to 1, bit 2 is set to 0, bit 3 set to 1 and bit 4 is set to 0.

In one embodiment, the parity is used to determine what value to assign bits of parity. Because bits 1-4 in example 1 are added to an even number, the parity bit, for example, 1 is set to 0, in order to maintain an even number for the sum of 1-4 bits and bits of parity. Because bits 1-4 in example 2 are added to an odd number, the parity bit for example 2 is set to 1, to get an even number for the sum of 1-4 bits and bits of parity. In an alternative embodiment, the check for odd parity is used instead of parity.

On FIGU depicts a table illustrating assigned to the I bits on figa after an error occurred in the fields of data bits. On FIGU assumes that happened ink short circuit in the address line 20A corresponding to bit 3 of data. The controller 34 determines whether any of the address lines 20A short circuit or open circuit, using electrical test each of the address lines 20A. In one embodiment, the electrical test involves checking the continuity. Methods for testing electrical conductive lines and the electrical circuits known to specialists in this field of technology. After electrical testing address lines 20A, the controller 34 determines that the address line 20A, the corresponding bit 3 has a short circuit. When the address line is ink short circuit, the output signal is read by the controller 34 will be equal to 1, regardless of whether the bit is set to 1 before the ink short circuit. Thus, bit 3 set to 1 for both example 1 and example 2 on FIGU, even though the bit 3 in example 2, should be 0, as shown in figa.

In example 1, the controller 34 examines the parity bit to determine if a field has data bits in error. Since the amount of bits 1-4 bits and parity is an even number, the controller 34 determines that the field of data bits does not contain an error.) - Rev. example 2 after researching bits parity to determine if a field has bits of data error, the controller 34 determines that the error occurred because the amount of bits 1-4 bits and parity is an odd number, and is used even parity. On the basis of the electrical test address line corresponding to bit 3, which indicates ink short circuit, and determining from the test of parity that an error has occurred, the controller 34 determines that the bit 3 must be 0, and accordingly adjusts the bit. Thus, the error does not cause disruption of the printer 10.

Although specific embodiments of illustrated and described in this description for purposes of describing the preferred option implementation, specialists in the art will understand that a wide variety of alternate and/or equivalent implementations may be substituted shown and described specific embodiments of, without going beyond the scope of the present invention. Experts in the field of chemistry, mechanics, electromechanics, electrical and computer engineering will easily understand that the present invention can be implemented in a very wide variety of embodiments. It is understood that this application covers any adaptations or variations of the preferred embodiments discussed what's in the present description. Therefore, explicitly assumes that this invention is limited only by the claims and its equivalents.

1. The method of detecting errors in the data received from the storage device replaceable component of the printer from the printer, and a storage device includes multiple bits, and the printer includes multiple conductive lines, and at least one of the conductive lines associated with each bit, the method contains the steps that provide the first bit of the parity associated with the first data item and the first data element and the first bit of the parity stored in the storage device; reading the first data element and the first bit of the parity of the storage device; perform electrical test at least one of the conductive lines and identify the error in the first data item based on the first bit of the parity read from the storage device, and electrical test.

2. The method according to claim 1, additionally containing a stage at which identify electrical short circuit, at least one of the conductive lines on the basis of the electrical test, the error in the first data item identified on the basis of the first bit counter is La parity, read from the storage device, and identified an electrical short circuit.

3. The method according to claim 1, additionally containing a stage at which identify an open circuit, at least one of the conductive lines on the basis of the electrical test, the error in the first data item identified based on the first bit of the parity read from the storage device, and the identified circuits.

4. The method according to claim 1, in which conductive lines are address lines connecting the storage device with the printer controller.

5. The method according to claim 1, wherein the storage device represent a permanent storage device.

6. The method according to claim 1, additionally containing phase, which determine the suitability of the replaceable printer component for use in the printer, based on the first data element.

7. The method according to claim 1, additionally containing phase, which determines the type of the replaceable printer component that is installed in the printer, based on the first data element.

8. The method according to claim 7, additionally containing phase, which determines the type of cartridge installed in the printer, based on the first data element.

9. The method according to claim 1, further comprising stages, which provide the second bit parity associated with the second data item, moreover, the second data element and the second bit parity stored in the storage device; reading the second data element and the second bit of the parity of the storage device; determine whether the error in the second data item based on the second bit parity read from the storage device.

10. The method according to claim 1, wherein the storage device combined with the cartridge.

11. The method according to claim 1, wherein the storage device together with the device printhead.

12. The method according to claim 1, wherein the storage device combined with the feeder ink.

13. Replaceable component of the printer to the print system having the controller, and a replaceable printer component includes an information storage device that stores first the parity bit and the first data element, and the first bit of the parity associated with the first data item, the first the parity bit is intended for use by the controller in conjunction with an electric test of the conductive lines connected to the information storage device, to identify errors in the first data element.

14. Replaceable printer component according to item 13, in which conductive lines are address lines.

15. Replaceable printer component according to item 13, in which oterom information storage device is a ROM.

16. Replaceable printer component according to item 13, in which the information storage device includes a semiconductor crystal and a variety of circuits formed on the semiconductor chip, and each schema is associated with status bits in the information storage device and indicates the status of bits.

17. Replaceable printer component according to item 16, wherein the schema associated with the first data item, are, essentially, about the center of the semiconductor crystal.

18. Replaceable printer component according to item 16, wherein the schema associated with the first bit parity, are, essentially, about the center of the semiconductor crystal.

19. Replaceable printer component according to item 13, in which the first data element indicates to the controller whether a component of the printer for use in printing system.

20. Replaceable printer component according to item 13, in which the replaceable printer component includes a cartridge.

21. Replaceable printer component according to item 13, in which the replaceable printer component includes a device printhead.

22. Replaceable printer component according to item 13, in which the replaceable printer component includes a feeder ink.

23. Replaceable printer component according to item 13, in which the first data element specifies the component type of the printer, installed the frame in the print system.

24. Replaceable printer component according to item 23, in which the first data element indicates the type of one of the following printer components: a cartridge device printhead or feeder ink.

25. Replaceable printer component according to item 13, in which the information storage device stores the second bit parity and the second data element, and the second the parity bit associated with the second data element, while the second bit parity is intended for use by the controller to determine whether the error in the second data item.

26. The print system that uses a replaceable printer component according to item 13, additionally containing a controller connected to the information storage device using the set of electrically conductive lines, and the controller responds to the output signal of the information storage device, the controller configured to perform an electrical test on at least one of the above-mentioned electrically conductive lines, and a controller configured to identify errors in the first data item based on the first bit parity and electrical test.

27. The print system p, in which the controller is configured to identify an electrical short circuit, less is th least in one of the conductive lines on the basis of the electrical test, the controller configured to identify errors in the first data item based on the first bit parity and identified an electrical short circuit.

28. The print system p, in which the controller is configured to identify an open circuit, at least one of the conductive lines on the basis of the electrical test, the controller configured to identify errors in the first data item based on the first bit of the parity and the identified circuits.

29. The print system p, in which the controller is configured to determine whether a component of the printer for use in printing system, based on the first data element.

30. The print system p, in which the controller is configured to determine the type of the component of the printer that is installed in the printing system, based on the first data element.

31. The print system according to item 30, in which the controller is configured to determine based on the first data item type one of the following printer components: a cartridge device printhead or feeder ink.

32. The print system p, in which the controller is configured for the distribution, is there an error in the second data item based on the second bit parity.

33. The print system p, in which the controller is configured to correct errors in the first data element based on the electrical test and the first bit parity.

34. Replaceable printer component having a built-in memory, for use in the print system, and component includes a semiconductor crystal and a variety of circuits formed on the semiconductor chip, and each schema is associated with status bits in a storage device and indicates the status of bits; a storage device that stores a variety of functional bits that must match the values expected by the printing system for proper operation of the print system, and a storage device stores a set of information bits that are not critical for proper operation of the print system, with essentially all of the circuits associated with the functional bits are essentially near the center of the semiconductor crystal.

35. Replaceable printer component according to clause 34, in which a large percentage of the schema associated with the information bits, is located essentially outside the center of the semiconductor crystal.

36. Replaceable printer component according to clause 34, in which the om many functional bits includes bits representing the first data element, which provides identification information on a removable component of the printer, and the bits representing the first data item, used by the printing system to determine whether or not the replaceable printer component for use in a printing system, in this scheme, associated with the bits representing the first data element, are, essentially, about the center of the semiconductor crystal.

37. Replaceable printer component according to clause 34, in which the replaceable printer component is a cartridge.

38. Replaceable printer component according to clause 34, in which the replaceable printer component is a unit of the printhead.

39. Replaceable printer component according to clause 34, in which the replaceable printer component is a feeder ink.

40. The way of storing information in the replaceable printer component having a built-in storage device, and a replaceable printer component is intended for use in the printing system, the method contains the steps that provide a semiconductor crystal with many circuits formed on the semiconductor chip, and each schema is associated with status bits in a storage device and indicates the status of bits; identify fields of functional bits SV is related with replaceable component of the printer, which should match the values expected by the printing system for proper operation of the print system and identify fields of information bits associated with the replaceable component of the printer that are not critical for the correct operation of the print system; retain a higher percentage of functional fields of bits in the semiconductor crystal by using schemas, which are, essentially, about the center of the semiconductor crystal.

41. The method according to p, optionally containing phase, which retain a high percentage of fields of information bits in a semiconductor crystal, using schemes that are essentially outside the center of the semiconductor crystal.

42. The method according to p in which the fields of functional bits include bits representing the first data element, which provides identification information on a removable component of the printer, and the bits representing the first data item, used by the printing system to determine whether or not the replaceable printer component for use in the print system; and the method further comprises a stage on which retain the bits representing the first data element, in the semiconductor crystal by using schemas, which are, essentially, about a center of the semiconductor, the if crystal.

43. The method according to § 42, in which the fields of functional bits include the parity bit associated with the first element data and the parity bit is used by the printing system to identify errors in the first data item, and the method further comprises a stage on which preserve the parity bit in the semiconductor crystal using the schema, which is, essentially, about the center of the semiconductor crystal.

44. The method according to p in which the fields of functional bits include the parity bit, which is used by the printing system to identify errors in one of the fields of functional bits, and the method further comprises a stage on which preserve the parity bit in the semiconductor crystal using the schema, which is, essentially, about the center of the semiconductor crystal.

45. The method according to p in which the fields of functional bits include bits of parity used by the printing system to identify errors in at least one of the functional fields of bits, and the method further comprises a stage on which save a lot of bits of parity in the semiconductor crystal by using schemas, which are, essentially, about antropologo crystal.



 

Same patents:

FIELD: data transfer systems.

SUBSTANCE: disclosed further are method and system for routing calls in inter-network interface for transferring speech via internet protocol (VoIP), in which on attempt of creation by calling client of VoIP call try station of international information exchange (FXS), inter-network interface VoIP inserts a certain prefix into appropriate port FXS, providing for called inter-network interface the capacity for such identification of calling client on basis of prefix, in case of which port of office of international information exchange (FXO) is assigned in accordance to priority of client.

EFFECT: improved routing of calls in inter-network interface VoIP.

3 cl, 6 dwg

FIELD: technology for automatic roaming between heterogeneous WLAN networks and/or GSM/GPRS/UMTS networks.

SUBSTANCE: for authentication mobile IP-node requests access to WLAN network from access station, mobile IP-node in response to request of access server transfers to access server the IMSI-identifier stored on SIM-card of mobile IP-unit, on basis of IMSI-identifier by means of information stored in SIM-bank of user data, logical IP-channel of WLAN data network is added to appropriate GSM-data for signal channels and GSM network data in accordance to user, and authentication of mobile IP-node is performed in HLR register and/or in VLR register of GSM network.

EFFECT: increased efficiency.

2 cl, 5 dwg

FIELD: engineering of multi-service networks, providing transmission of traffic of different types: data, video, speech, and, in particular, networks, utilizing various commutation algorithms.

SUBSTANCE: method for positioning statistical multiplexing during transfer of information between devices of network ending and commutation nodes includes receiving and recording channel data blocks during transfer, sorting received data blocks in accordance to given transfer directions, data blocks of constant and/or data blocks of alternating length are grouped, which are positioned in multiplexing intervals with header - identifier of data blocks and containing information for their later routing and/or commutation, and are transferred in accordance to transfer directions via network communication channel, and during receipt in network end devices and on each commutation node, data blocks, received from communication channel, are ungrouped in accordance to given transfer directions, while data blocks being received are sorted in accordance to given transfer directions and priorities for different sort of traffic, sorted data blocks depending on presence of free multiplexing intervals are accumulated in transfer buffer and traffic buffer for forming a queue for transferring data blocks, data blocks accumulated in traffic buffer are analyzed, on basis of results of analysis of accumulated data blocks, computation and generation of multiplexing intervals of alternating duration is performed, accumulated data blocks are grouped in generated multiplexing intervals of alternating duration and transferred in accordance to transfer directions via network communication channel, while multiplexing intervals of alternating duration are formed in such a way, that average duration of multiplexing interval, called base length of multiplexing interval, remains the same, while duration of base multiplexing interval is selected to be not less than time of transfer of data block of maximal duration.

EFFECT: increased efficiency of usage of channel resources, decreased jitter and abolished rigid synchronization between commutation nodes.

15 cl, 9 dwg, 2 tbl, 1 app

FIELD: technology for distributing resources of descending communication line in communication system with multiple inputs and multiple outputs.

SUBSTANCE: in accordance to method, for possible data transmission one or more sets of terminals is formed, while each set includes unique combination of one or more terminals and matches hypothesis subject to evaluation. Formed additionally may be one or more sub-hypotheses for each hypothesis, while each sub-hypothesis matches certain assignment of several transmitting antennas to one or more terminals in hypothesis. Then efficiency of each hypothesis is evaluated, one of evaluated sub-hypotheses is selected, based on their efficiency. Then terminal (terminals) in selected sub-hypothesis is planned for data transmission, and after that data are encoded, modulated and transferred to each terminal, planned for transmission, via one or more transmitting antennas, assigned to terminal.

EFFECT: increased efficiency.

7 cl, 9 dwg

FIELD: preventing decoding errors for multimedia systems.

SUBSTANCE: proposed method for preventing errors in the course of decoding plurality of given data bursts includes following steps: (a) decoding of one of plurality of bursts; (b) decoding of other burst when error is detected at step (a); (c) decoding of combination of (a) and (b) bursts or of third burst when error is found at step (b);(d) repetition of step (c) until decoding error is eliminated.

EFFECT: provision for permanent throughput for channel with burst errors, channel with random errors, and channel with both types of errors at a time.

4 cl, 6 dwg

FIELD: the invention refers to the field of combined radio environment that is of radio medium which simultaneously envisage possibility of multi-address broadcasting and include one or more cellular circuits of radio communication.

SUBSTANCE: the essence of the invention is in that many mobile arrangements (1,2,3) of communication are prescribed for receiving of a common content by way of multi-address broadcasting because otherwise it would be necessary to deliver this content along separate channels. At that the prescribed arrangements (1,2,3) of communication are defined out of a great number of arrangements (1,2,3.4) of liaison which till this time could work in various cellular circuits (11,12) of communication.

EFFECT: possibility of multi-address broadcasting and cellular communication simultaneously.

20 cl, 3 dwg

FIELD: method for dispatching scanning for reading data from devices.

SUBSTANCE: method includes following stages: sorting of serviced devices in accordance to their types, sorting various data types of each device with generation of various modules and assignment of priority attribute and scanning periodicity attribute to each module; separation of serviced devices on two groups: group, consisting of devices subject to scanning and group consisting of devices, connection status of which it is necessary to determine; periodic scanning of each module of group, consisting of devices subject to scanning, in accordance to its priority and period of scanning, while it is possible to set various periods of scanning and to use various scanning algorithms depending on data changing speed, and also scanning algorithms may be altered in real time depending on condition of devices.

EFFECT: possible efficient control over total load on system and network load on network control system, and also rational usage of system resources.

10 cl, 1 dwg

FIELD: method for dispatching scanning for reading data from devices.

SUBSTANCE: method includes following stages: sorting of serviced devices in accordance to their types, sorting various data types of each device with generation of various modules and assignment of priority attribute and scanning periodicity attribute to each module; separation of serviced devices on two groups: group, consisting of devices subject to scanning and group consisting of devices, connection status of which it is necessary to determine; periodic scanning of each module of group, consisting of devices subject to scanning, in accordance to its priority and period of scanning, while it is possible to set various periods of scanning and to use various scanning algorithms depending on data changing speed, and also scanning algorithms may be altered in real time depending on condition of devices.

EFFECT: possible efficient control over total load on system and network load on network control system, and also rational usage of system resources.

10 cl, 1 dwg

FIELD: engineering of systems for providing access to multimedia products for consumer through connections of digital client line xDSL.

SUBSTANCE: method includes usage of at least one multiplexer of access to digital client line DSLAM with permitted broadcasting, made for authentication of at least one user locally, and for permitting access to at least one channel in base network, while client information of each user is recorded in DSLAM, which maintains xDSL connection, leading to house of client and each DSLAM supports broadcasting protocols, request is received in DSLAM with permitting of broadcasting at least to one channel from client, where receiving DSLAM locally services xDSL connection for client, information stored in receiving DSLAM is used to determine whether access of client to channel being requested is sanctioned, and if client has sanctioned access to channel being requested, then DSLAM is used to provide such access.

EFFECT: increased speed of switching between channels of audio-visual information through xDSL connection with confirmation in access unit.

5 cl, 9 dwg

FIELD: broadcast transmission systems, in particular, systems and methods for decreasing power consumption of mobile terminals between transfer of impulse packs.

SUBSTANCE: mobile terminal receives packs of content, while some packs of content include information of aligned time, identifying time of transfer of next content pack. Mobile terminal may cut power to receipt module during periods of time when mobile terminal is not scheduled to receive content packs.

EFFECT: increased efficiency of battery usage of mobile terminals.

5 cl, 6 dwg

FIELD: construction.

SUBSTANCE: method comprises using the pipeline to be tested as a wave guide and mounting emitter in the balk of the electric insulation of the pipeline. The aerial of the emitter is connected with the aerial of the writer through the pipeline. The address emitter comprises rectifier, memory, threshold element, and decoder. The aerial is connected to the input of the rectifier whose output is connected with the bus for power supply to the emitter through the carrier and threshold element. The power supply bus of the decoder is connected with the input of the threshold element. The signal input is connected with the aerial, and signal output is connected with the input of the emitter.

EFFECT: enhanced reliability of testing.

3 cl, 3 dwg

The invention relates to systems of remote control and remote signaling

The invention relates to radio engineering, namely, aviation electronics, and can be used for continuous monitoring of the output signals of the two cursortheme at the corners of heading, roll and pitch, as well as to control synchronously rotating shaft, remote transmissions, etc

The invention relates to processing signals from sensors (D), in particular, detonation combustion

The invention relates to telecommunications systems and computer engineering and can be used for measurement errors that distort the data in the channels of transmission or reproduction of information with inserts/deposition bit

The invention relates to telecommunications, and particularly to control devices of occupied channels of communication without interruption and distortion of the transmission of information signals

The invention relates to information-measuring technique and can be used in telemetry, telecontrol

The invention relates to a digital magnetic recording and can be used to reduce the time of conversion, error correction in the external storage device micro-computers and personal computers

FIELD: automatics and computer science, possible use for controlling and correcting errors during relaying of information, and also for performing arithmetical operations by computer.

SUBSTANCE: device has two blocks for calculating error syndrome on basis of control bases, made on two-layer neuron network, register, memory block, output adder, and also due to application of polynomial residuals system, in which as system base, minimal polynomials are used, determined in extended Galois fields GF(2ν) and in terms of neuron network technologies.

EFFECT: decreased dimensions of equipment, higher speed of detection and correction of errors.

3 dwg, 2 tbl

FIELD: computer science.

SUBSTANCE: network has end ring neuron network, Hopfield neuron network, demultiplexer and multiplexer.

EFFECT: broader functional capabilities, higher efficiency, higher speed of operation.

1 dwg

The invention relates to the field of automation and computer engineering and can be used in computational structures to control the accuracy of arithmetic operations
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