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Loading/moving and copying commands for processor. RU patent 2292581.

FIELD: computer engineering.

SUBSTANCE: processor contains first logical means for preserving set of bit groups into non-adjacent groups of storage cells and second logical means for storing a copy of a set of non-adjacent bit groups. In accordance to method, set of bit groups is saved to set of non-adjacent storage cells and set of non-adjacent bit groups is copied into remaining groups of bit storage cells. System contains memory and processor for storing first bit group in first and second storage cell groups and for storing second bit group in third and fourth storage cells. Device contains execution module for storing bits [31-0] in positions [31-0] and [62-32], bits [95-64] in positions [95-64] and [127-96] of destination register bits.

EFFECT: possible use of single command for moving/loading, which provides for loading and following copying of series of bits of operand of source to register of destination.

4 cl, 5 dwg

IPC classes for russian patent Loading/moving and copying commands for processor. RU patent 2292581. (RU 2292581):

G06F9/315 -

Another patents in same IPC classes:

Method for processing with use of one commands stream and multiple data streams / 2279706
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Method and device for parallel conjunction of data with shift to the right / 2273044
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Loading/moving and copying commands for processor / 2292581
Processor contains first logical means for preserving set of bit groups into non-adjacent groups of storage cells and second logical means for storing a copy of a set of non-adjacent bit groups. In accordance to method, set of bit groups is saved to set of non-adjacent storage cells and set of non-adjacent bit groups is copied into remaining groups of bit storage cells. System contains memory and processor for storing first bit group in first and second storage cell groups and for storing second bit group in third and fourth storage cells. Device contains execution module for storing bits [31-0] in positions [31-0] and [62-32], bits [95-64] in positions [95-64] and [127-96] of destination register bits.

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