Random-length pulse generator

FIELD: pulse generators.

SUBSTANCE: proposed random-length pulse generator that can be used for signal simulation in data transfer systems and produces random-length pulses of desired statistical characteristics has frequency standard, delay line, multiplexer, pseudorandom number generator, adding unit, and flip-flop.

EFFECT: enhanced precision and stability.

1 cl, 1 dwg

 

The technical field to which the invention relates.

The present invention relates to a generator of electrical impulses and can be used to model real-world data signals in communication systems.

The level of technology

To evaluate stock health receivers of digital data signals transmitted on the real line, it is necessary to simulate signals with distortion, manifested in the form of a random deviation of the pulse duration from the average value with given statistical properties.

For generating random pulses duration is applied to the device containing the comparator, one input of which receives a periodic sawtooth pulses and the other input - voltage noise [1], which can be generated by any known source of noise [2]. In such a device is a linear transformation of the voltage noise in the pulse duration, so the duration of the generated pulses has statistical properties of the source voltage noise. The disadvantage of this analog is low accuracy and stability of the statistical characteristics of the duration of the generated pulses is due to the analog nature of the processes in it.

The same method is implemented in the generator of uniformly distributed random pulses [3], katalysator of the comparator, the inputs of which are connected to the outputs respectively of the device of the sample-hold instantaneous values of voltage and noise generator linearly varying voltage, and the control inputs of the device sample storage and generator linearly varying voltage is connected with the reference clock generator. Accurate modeling of noise rejection pulse width at the output of the comparator in the analog low due to the analog nature of the process by which the change in the statistical characteristics of the voltage noise in the care of the temperature or the supply voltage leads to a distortion of the established probabilistic moments of the pulse duration.

For modeling random processes are successfully applied the pseudo-random number generator (PRNG), which is a shift register with feedback through the EXCLUSIVE OR element, inputs connected to the outputs of the respective bits of the register [4]. The generated noise to implement with a duration less than the duration of the cycle PRNG can be considered completely random, the sum of the contents of k contiguous bits of the m-bit register in the PRNG is subject to the normal law of distribution and has a range from f0/(2m-1) to f0where f0- clocked PRNG [5, 6], and the number of levels of quantization (k+1). Specified is the principle used in the known device for simulation of jitter pulse code sequence [7].

Known analogues of the closest in technical essence to the present invention is a pulse generator with phase jitter [8], consisting of the reference oscillator, the output is connected simultaneously to the input of the PRNG and coordinated multi-tap delay line. The taps of the delay line are connected to the appropriate information inputs of the multiplexer, whose address inputs are connected to a group of adjacent outputs of the PRNG through the block digital sum, made in the form of a persistent storage device. In this analogy, is built entirely on digital blocks is noise modulation of the phase of the output pulse of the multiplexer. Due to this, the device has a high accuracy and stability while generating pulses with a random phase. The drawback of the prototype is limited functionality, not allowing you to use it to get pulses of random duration.

The invention

The aim of the present invention is to expand the functionality of the receipt of pulses of random duration with the given statistical characteristics for high accuracy and stability.

For this purpose, in the device containing the reference generator is loaded on a partitioned delay line, GRU is PA adjacent taps of which are connected to the corresponding information to the inputs of the multiplexer, PRNG, the group of adjacent outputs of which are connected with inputs of the summation block, outputs connected to corresponding address inputs of the multiplexer entered the trigger. While one input of the trigger is connected to the output of the reference oscillator, the other input of the trigger - output multiplexer, and the output of the trigger is connected to the input of the PRNG and the output terminal of the device.

The principle of the device based on the setting of the trigger pulse of the reference oscillator at fixed points in time and the reset trigger pulse from the output of the multiplexer. Since the address multiplexer is formed as the sum of adjacent bits of the register in the PRNG and the essence of a random variable, and the phase of the pulse at the output of the multiplexer is a random variable. Therefore, the moment of reset trigger and, therefore, the pulse duration at the output is also a random variable the Mean value of the duration of the generated pulses and its standard deviation specifies the delay line, and the distribution and energy spectrum - PRNG.

List of figures

The drawing shows an electrical block diagram of the pulse generator of random duration in accordance with the present invention.

Information confirming the possibility of carrying out the invention

Shown in the drawing, the circuit of the generator to them is alsow random duration contains the reference oscillator 1, loaded on a partitioned delay line 2 and one input of the trigger 3 and the multiplexer 4, PRNG 5 and block 6 summation. The other input of the trigger 3 is connected to the output of the multiplexer 4, and its output to the output terminal 7 and the input of the PRNG 5. The information inputs of the multiplexer 4 is connected to respective taps of a partitioned the delay line 2 and the digital address input - digital output block 6 summation. In turn, the digital inputs of the summation block 6 is connected to the respective digital outputs of the PRNG 5 outputs bits forming the PRNG of the shift register.

In the present embodiment uses the RS-trigger with 3 direct dynamic inputs, it is cocked and released by the fronts of the input pulses. PRNG 5 has an inverse dynamic input and it busts of output pulses of the trigger 3. Partitioned delay line 2 has a first section with a delay time t1and n the following sections with the delay time of each t2. As line 2 delay may be used consistent output tap of the electromagnetic delay line, however, it is preferable to use a serial electronic circuit elements of the delay, allowing smooth control. Reference oscillator 1 is frequency f0.

The pulse generator random deletelines and works in the following order Each pulse of the reference oscillator 1 with its front vvodit trigger 3 and simultaneously fed to the input of a partitioned line 2 delay. After time t1passing the first section of the delay line 2, the pulse begins to spread in the following sections sequentially reaching the information inputs of the multiplexer in ascending order of their numbers from 0 to (n-1). Since the address inputs of the multiplexer 4 through section 6 of the summation connected to the outputs of the PRNG 5, in each period a random address and the multiplexer 4 connects to its output taps partitioned line 2 delay is also random. Since the reset of the trigger 3 is a front output pulse multiplexer 4 at random points in time, and the duration of the pulse at the trigger output is random. At the end of the output pulse on its decline) PRNG 5 adopts a new state, specifies the duration of the pulse in the next period.

If we neglect the delay time distribution of the multiplexer 4, the average duration of the generated pulses is equal to

where t1and t2the delay times respectively the first and the following partitions of the partitioned line 2 delay, n is the number of information inputs of the multiplexer 4, respectively, and bends partitioned line 2 delay, and the variance is

The distribution of tAndclose normalname, the energy spectrum of deviations of tAndextends from f0/(2m-1) to f0where f0the frequency of the reference oscillator 1, m - bit base shift register in the PRNG, and the number of stages of the quantization of tAndis n.

Literature

1. Tufarelli CD, Shulga VG Device simulation jitter pulse code sequences. In Proc. "solid state electronics communications engineering", vol. 19. - M.: Communication, 1978, s-161, 4.

2. Bonev BTW, the Generation of random signals. - M.: Energy, 1971.

3. The generator of uniformly distributed random pulses. - RF patent №2107941, IPC G 06 F 7/58.

4. Titze U., Schenk, K. Semiconductor circuitry: a reference guide. - M.: Mir, 1982, s, RES.

5. Horowitz P., hill U. Art circuitry: 2 so Vol.2.-M.: Mir, 1986.

6. Korn, Modeling random processes analog and analog-to-digital machines. - M.: Mir, 1968.

7. Device for simulating jitter pulse code sequence. - Ed. mon. The USSR №1198533, IPC G 06 F 15/20.

8. Stockings, VA the pulse Generator with the phase jitter. - Instruments and experimental techniques, 1996, No. 2, s-74.

The pulse generator of random duration, containing reference generator loaded on a partitioned delay line, a group of adjacent taps of which are connected to the corresponding detail is rationem the inputs of the multiplexer, as well as the pseudo-random number generator, a group of adjacent outputs of which are connected with inputs of the summation block, the outputs of the summation block connected to respective address inputs of the multiplexer, characterized in that it introduced the trigger, one input connected to the output of the reference oscillator, the other input - output multiplexer, and an output connected to the input of the pseudo-random number generator and the output terminal of the pulse generator of random duration.



 

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