Device and method for sending and receiving information for detection of errors in communications system

FIELD: communications.

SUBSTANCE: device has multiple cascade registers and multiple adders. During receipt of control information series operator forms a series of check connection bits and sends it to adders. After finishing of receipt operator serially adds given input bit to output bits of last register and outputs a result. Source value controller sends to registers a value selected from two source values.

EFFECT: higher efficiency, broader functional capabilities.

8 cl, 7 dwg, 2 tbl

The technical field to which the invention relates.

The present invention relates to a communication system for transmitting packet data, in particular, to a device and method of attaching information about the detected errors to the transmitted information before its transmission and reception.

The level of technology

System mobile multiple access code division multiplexing (mdcr, CDMA) standard IS-2000, representing a typical mobile communication system supports only the transmission of speech. However, with the development of communication technologies and the desire of the subscribers of the mobile communication system in the future will support data services along with voice.

The mobile communication system supporting multimedia services, including voice and data, provides a voice communication service to multiple subscribers using the same frequency range. In this mobile communication system supports data transmission using a time division multiplexing (TDM) or time division multiplexing and code compaction (TDM/CDM). TDM is a method of assigning the same code in the time interval allocated to a specific subscriber. TDM/CDM is a method that allows multiple users to use the same time interval. These Cust the options identified are assigned to individual subscribers codes (for example, orthogonal codes such as Walsh codes).

The mobile communication system has a channel packet data (CPD, PDCH) for packet data control channel packet data (COPD, PDCCH), for example, the secondary control channel packet data transfer (WCUPD, SPDCCH) for efficient packet data. Packet data is transmitted on the channel packet data. The packet data transfer in ether is carried out in the unit of packet physical layer (PFCs PLP) and the duration of the packet physical layer changes with each transmission. The control channel transmits packet data sequence control information, necessary that the receiver be able to accept the packet data. The duration of a sequence of control information is changed in accordance with the duration of the packet data. Therefore, the receiver can determine the variable length packet data by assessing the duration of the sequence control information. The duration of a sequence of control information is evaluated by detection blind time interval (LIGHT, BSD).

Figure 1 shows the design of the transmitter control channel in a mobile communication system which employs the present invention. Figure 1 implies the tsya, the input sequence control channel packet data or a sequence of control information transmitted on the control channel packet data, has 13 bits into N time slots (where N=1, 2, or 4). It should be noted that the number of bits included in the sequence control information is not associated with the duration of a sequence of control information and is not limited by the number 13. The duration of a sequence of control information transmitted over the control channel packet data depends on the duration of the packet data. For example, if the packet data has a duration of 1 time interval 2 time intervals, 4 time intervals and/or 8 time intervals, the sequence control information has a duration selected from 1 time interval 2 time slots and 4 time intervals. For packet data, a duration of 1 time interval is transmitted to the sequence control information with a duration of 1 time interval. For packet data length 2 time interval is transmitted to the sequence control information with a duration of 2 time interval. For packet data length 4 time interval is passed posledovatelnostei information duration : 4 time intervals. For packet data, a duration of 8 time slots is transmitted to the sequence control information with a duration of 4 time intervals. The basis for the transmission sequence control information with a duration of 4 time intervals even for batch data length of 8 time intervals is the desire to avoid excessive increase of the length of the header.

Bits of error detection attach block 110 attaching bits of error detection to the sequence control information transmitted over the control channel packet data. Block 110 attaching bits of error detection attaches bits of error detection to the sequence control information to the receiver was able to detect a transmission error in the sequence control information. For example, block 110 attaching bits of error detection attaches 8 bits of error detection to the 13-bit sequence control information and generates a 21-bit sequence control data. A typical example of block 110 attaching bits of error detection is the generator of the cyclic redundancy code (CEC, CRC). Generator CEC generates a sequence of control data or a sequence of control information with the attached detail what Razia CEC by encoding an input sequence of control information with the CEC. If the number of redundant bits generated by the generator CEC increases, it increases the possibility of detecting transmission errors. However, increasing the number of redundant bits for the sequence control information reduces the effectiveness of capacity. Therefore, usually bits for error detection uses 8 bits of the CEC.

Block 120 attachment end bits attaches the final bits to the output of the sequence control data from the block 110 attaching bits of error detection. Convolutional encoder 130 encodes the output unit 120 attaching the final bits of the convolutional code and outputs the encoded symbols. For example, the block 120 attachment end bits 8 attaches the end bits (all "0") convolutional coding convolutional encoder 130 and produces a 29-bit information. Convolutional encoder 130 performs convolutional encoding of a sequence of control information with a duration of 1 time interval with the encoding speed is 1/2, the sequence control information with a duration of 2 time interval and sequence control information with a duration of 4 time intervals with encoding speed 1/4. The number of characters in the sequence control information encoded convolutional code with encoding speed 1/4, twice neighbourhood, with some what leads to a number of characters in the sequence control information, encoded convolutional code with rate coding 1/2. Block 140 characters repeat reissues the characters produced by the convolutional encoding of a sequence of control information with a duration of 4 time interval to the number of characters received convolutional encoding sequence control information with a duration of 4 time intervals, was two times more than the number of characters received convolutional encoding sequence control information with a duration of 2 time interval. As a result, the block 140 characters repeat issues 58N characters (where N=1, 2, or 4).

Block 150 punching punches 10N symbols among the symbols at the output of block 140 characters repeat in order to reduce the decrease of efficiency and to ensure appropriate coordination speed. Thus, the block 150 punching gives 48N characters. Block 160 alternation punctuates the symbols at the output of block 150 punching. In order to use block 160 alternation is to reduce the probability of packet error due to the alternation (or permutation) of the order of characters in order to solve the problem of packet errors due to convolutional encoding. As block 160 interleave the block is the inverse interleave bits (OPB), which is a type of block b is full-time alternation. Unit OPB increases the spacing between adjacent characters, so the first half of the sequence perenesennyj characters consists of the even-numbered symbols and the second half of the sequence perenesennyj characters consists of odd characters. The modulator 170 modulates the characters, peremerzanie unit 160 alternation, using a modulation method quadrature phase-shift keying (FMC) and generates modulated symbols for transmission.

Figure 2 shows the structure of a known unit 110 attaching bits of error detection, depicted in figure 1. Shows an example of the use of a generator CEC to attach the 8 bits of the CEC to the input sequence control information.

Shown in figure 2 block 110 attaching bits of error detection includes a set of registers 211-218, many adders 221-224, switches SW1-SW3, the output adder 225, and the controller 230 of the original value. The controller 230 of the original value initializes the values of the registers 211-218 to "1"when the transmitted packet data with a duration of 1, 2, and 4 time intervals. When the transmitted packet data with a duration of 8 time slots, the controller 230 of the original value initializes the values of the registers 211-218 to "0". Since the duration of a sequence of control information corresponding to the packet data is the duration of 4 time intervals, and the duration of a sequence of control information corresponding to the packet data with a duration of 8 time intervals equal to 4 time intervals, the receiver cannot distinguish between the duration of the packet data on the length of the sequence control information, although he estimates the duration of a sequence of control information. Therefore, when the block 110 attaching bits of error detection generates redundant bits (or bits of error detection) for the sequence control information corresponding to the packet data with a duration of 4 time intervals, and sequence control information corresponding to the packet data with a duration of 8 time slots, the controller 230 of the original value sets the initial values of the registers 211-218 on different values, as indicated above, so that the receiver is able to recognize when decoding, were transferred to the packet data length 4 time interval or duration of 8 time intervals. After initialization, the values of registers 211-218 output adder 225 performs the binary operation between each bit of the input sequence control information and a value obtained by right shift registers values 211-218, and the resulting d is authorized operation is outputted as the output sequence control data. During this operation, all the switches SW1-SW3 are switched to their top conclusions. After performing the above operations on all bits of the 13-bit sequence control information of the switches SW1-SW3 are switched to their lower pins, so that the switches SW1 and SW2 are set to "0". After this 8 redundant bits is attached by means of the shift register values as many times as there are redundant bits (8).

Figure 3 presents the design of the known receiver control channel packet data, and figure 4 shows the duration and position of time intervals used to detect sequence control information receiver figure 3. In particular, figure 3 shows the design of the receiver for determining the length of packet data by determining the sequence of control information transmitted over the control channel packet data, the method detection blind time interval (LIGHT). This unit corresponds to the transmitter control channel packet data, in which the block attaching bits of error detection is used, the generator of the CEC. The receiver includes blocks check the CEC, corresponding to the generator of the CEC in the transmitter.

Shown in figure 3 receiver contains 4 blocks 310-340 processing p is Yama, intended for determining the length of packet data. Block 310 processing is a processing unit sequence control information with a duration of 1 time interval corresponding to the packet data with a duration of 1 time interval; block 320 processing is a processing unit sequence control information with a duration of 2 time interval corresponding to the packet data length 2 time interval; block 330, processing is a processing unit sequence control information with a duration of 4 time intervals corresponding to the packet data with a duration of 4 time intervals, and the block 340 processing is a processing unit sequence control information with a duration of 4 time intervals corresponding to the packet data with a duration of 8 time intervals.

In blocks 310-340 reception processing units 312, 322, 332 and 342 reverse alternation performs reverse alternation depending on the duration time intervals, and blocks 314, 324, 334 and 344 reverse punch performs reverse punching depending on the duration of time intervals. In blocks 330 and 340 of the processing technique for sequence control in the information with a duration of 4 time interval blocks 335 and 345 combining characters combine two adjacent characters, what is the opposite of repetition of characters performed by block 140 characters repeat, depicted in figure 1. After you perform a reverse punch in blocks 310 and 320, the processing of receiving and combining characters in blocks 330 and 340 of the reception processing, convolutional decoders 316, 326, 336 and 346 in blocks 310-340 processing of receiving perform convolutional decoding. Convolutional decoder 316 for sequence control information with a duration of 1 time interval performs convolutional decoding output unit 314 reverse punch with the encoding speed 1/2. Convolutional decoder 326 to the sequence control information with a duration of 2 time interval performs convolutional decoding output unit 324 reverse punch with the encoding speed 1/4. Similarly, convolutional decoders 336 and 346 for the sequence control information with a duration of 4 time intervals perform convolutional decoding output signals of blocks 335 and 345 of Association of characters with encoding speed 1/4, respectively. In the last stages of the blocks 310-340 processing of reception provided by blocks 318, 328, 338 and 348 validation of the CEC. Blocks 318, 328, 338 and 348 check the CEC checks the CEC on the characters, surtace decoded convolutional decoders 316, 326, 336 and 346, respectively. Through the th test CEC blocks 318, 328, 338 and 348 check the CEC determines whether there is error CEC in the sequence control information transmitted from a transmitter. While checking the CEC blocks 318, 328, 338 and 348 check the CEC uses the original value "1" or "0", previously defined as described in connection with figure 2. That is, the block 318 checks the CEC finds a problem with the CEC by setting the initial values of the register decoder to "1"; block 328 checks CEC detects an error of the CEC by setting the initial values of the register decoder to "1"; block 338 checking the CEC finds a problem with the CEC by setting the initial values of the register decoder to "1" and block 348 check the CEC finds a problem with the CEC by setting the initial values of the register decoder to "0". The detector 350 the packet length specifies the length of packet data on the basis of the results of processing of the reception blocks 310-340 processing technique. This 4 blocks 310-340 reception processing can be implemented either in the form of physically separate processing units receive, either as a single processing unit receiving, using different reception parameters.

If the receiver is shown in figure 3, the result of decoding the CEC three processing unit receiving have errors, and one processing unit of the reception with no errors, the conclusion that was given the number of packet data equal lifespan and, the corresponding processing unit to be received without errors. However, if it is reported that two or more processing units receive no errors or all of the processing units receive no errors, it is impossible to determine the sequence of control information was transmitted, which leads to the impossibility of reception packet data.

A receiver that detects a sequence of control information by means of LIGHT, has the following problems in the discovery process sequence control information with a duration of 2 time interval and sequence control information with a duration of 4 time intervals corresponding to the packet data length 4 time interval.

Figure 1 is a sequence of control information with a duration of 2 time interval and sequence control information with a duration of 4 time intervals corresponding to the packet data with a duration of 4 time intervals have the same initial value register CEC and are encoded by a convolutional code with encoding speed 1/4. Then the sequence of control information with a duration of 4 time intervals is subjected to the operation of the repetition symbols, which doubles the number of characters, whereas the sequence control and the formation of a duration of 2 time interval is not subjected to the operation of repeating characters. After that, the encoded sequence of symbols of the sequence of control information with a duration of 2 time interval and the encoded sequence of symbols of the sequence of control information with a duration of 4 time intervals are punching operations and alternations.

When the sequence control information with a duration of 4 time interval undergoes alternation with OPB, although the sequence of control information with a duration of 2 time interval and sequence control information with a duration of 4 time intervals have different combinations of punching, much of the information with the repetition of characters is inserted separately in the first two time intervals and the last two time intervals. Therefore, if the block 320 processing technique for sequence control information with a duration of 2 time intervals is illustrated in figure 3, receives the transmitted sequence control information with a duration of 4 time intervals, it is concluded that the sequence of control information with a duration of 4 time intervals was adopted correctly without errors CEC. For example, when transmitted sequence of control information include the awn 4 time intervals, convolutional decoder 326 in block 320 processing technique for sequence control information with a duration of 2 time interval and a convolutional decoder 336 in block 330, processing technique for sequence control information with a duration of 4 time intervals generates the same number (10000) of the decoded symbols. In other words, the same results of decoding by the CEC upon successful CEC 2(1) and 4(1) shown in row 4(1) WCUPD (CEC) in table 1, obtained experimentally. Accordingly, when decoding the CEC concludes that there is no error. As a result, the duration of the packet data, it is impossible to determine.

The same problem occurs even when transmitted sequence control information with a duration of 2 time interval. When transmitted, the sequence control information with a duration of 2 time interval, the processing unit 330 for receiving a sequence of control information with a duration of 4 time intervals receives information about the sequence of control information with a duration of 2 time intervals, combined with the information in the 2 previous time intervals or interference. Because the combination of alternation and combination punching to the sequence control information about what Oliclinomel 2 time interval such combinations alternation and combination punching to the sequence control information with a duration of 4 time intervals, the conclusion about the absence of errors, even when the decoding of the CEC is performed on a sequence of control information with a duration of 2 temporary spacing unit 330 processing technique for sequence control information with a duration of 4 time intervals. For example, when transmitted sequence control information with a duration of 2 time interval, the convolutional decoder 326 in block 320 processing technique for sequence control information with a duration of 2 time interval and a convolutional decoder 336 in block 330, processing technique for sequence control information with a duration of 4 time intervals form an almost equal number (10000 and 7902) of the decoded symbols. That is, almost the same results of decoding by the CEC at 2(1) and 4(1) successful CEC in line 2(1) WCUPD (CEC) are shown in table 1. Accordingly, when decoding the CEC concludes that an error is absent. As a result, the duration of the packet data, it is impossible to determine.

In addition, since the output signals of the convolutional decoder 326 and 336 are identical (or almost identical) to each other, the information bits of the received sequence control information, for example, information bits indicating the subscriber, what sequence the control information has been transmitted, or data bits associated with re-transmission, also is accepted in block 320 processing technique for sequence control information with a duration of 2 time interval and in block 330, processing technique for sequence control information with a duration of 4 time intervals. Therefore, despite the use of information bits in the sequence control information, it is impossible to distinguish between the duration of a sequence of control information in time intervals. In the result, it is impossible to determine the duration of the packet data.

This problem is illustrated in table 1. Table 1 presents the simulation results obtained when transmitting each of the sequences of control information with a duration in the time intervals 1(1), 2(1), 4(1) and 4(0), 10,000 times in a state of interference. The "1" and "0" in parentheses indicate original values, which initializes all the registers in the generator of the CEC. The resultant values obtained by computer simulation, include the probability of successful detection Pd and false probability Pfa recognition of the wrong duration in time intervals as the correct duration, incorrect probability Pm oshibochno is making the right duration of time intervals as incorrect duration time intervals, and the error probability PE, the amount of false probability Pfa and incorrect probability Pm. Table 1 shows that the probability of error PE in the detection of frame control information consisting of 2(1) time slots and 4(1) time intervals, abnormally high.

The invention

The present of the invention is a device and method of attaching information to detect errors to the information transmitted in the communication system.

The next task of the invention is to provide a device and method of attaching the relevant information for error detection to the blocks transmitted information having different duration, in the communication system.

Ass is whose present invention is a device and method of attaching information for error detection to the control information of the packet data in a communication system for transmitting packet data.

The present invention also solves the problem of creating a device and method of reception of control information packet data and analysis adopted control information in a communication system for transmitting packet data.

Another object of the present invention is to provide a device transceiver personnel management information and effective way of estimating the duration of the frame control information transmitted on the control channel packet data, the method detection blind time interval (LIGHT) in the communication system for packet data.

According to the first aspect of the present invention, an apparatus for forming sequence information for error detection, which is designed for determining the length of the transmitted data sequence. The device used in the communication system which can transmit at least two data sequences of various lengths on the data channel and to transmit control channel data sequence control data of the same length as the sequence data. The sequence control data includes a sequence control information showing the information in respect of each series, and serial is inost information for error detection, designed to detect errors in the sequence control information. The device further comprises multiple cascaded registers, the number of which is equivalent to the number of bits in the sequence information for error detection. Many adders are provided on paths, certain predetermined generating polynomial of paths between registers. Each adder adds a sequence of bits, adopted through the input path, the sequence of bits of feedback and outputs the result of addition through the exit path. Provided the operator for forming, during the reception of a sequence of control information bit sequence feedback by sequentially adding bits of the sequence control information to the output bits of the destination register of the above-mentioned registers and supply the generated sequence of bits of feedback adders. After receiving the sequence control information, the operator sequentially adds the specified input bits to output bits of the destination register and outputs the result of addition as sequence information for error detection. The controller of the source takes the values in the registers one value selected from two initial values, opredelenijaja for two sequences of data.

According to the second aspect of the present invention, an apparatus for forming a sequence of transmitted information by attaching sequence information for error detection to the input sequence of the first sequence information or the second sequence information. The device used in the communication system, which encodes the first sequence information from the first duration at a given speed of encoding prior to transmission, or encodes the second sequence information with the second duration, which in F times (where F is a multiple of 2) the first duration, a given speed of encoding prior to transmission, repeated F times. The device includes multiple cascaded registers, the number of which is identical to the number of bits in the sequence information for error detection. Many adders are provided on paths, certain predetermined generating polynomial of paths between registers. Each adder adds a sequence of bits, adopted through the input path, the sequence of bits of feedback and outputs the result of addition through the exit path. Provided the operator for forming, during reception of the input sequence of information, you'll find the activity feedback bits by sequentially adding bits of the input sequence information to the output bits of the last register of the said registers, feed the generated sequence of bits of feedback and outputting the input sequence information as a sequence of transmitted information. After completion of reception of the input sequence information, the operator takes the specified input bit adders, sequentially adds the specified input bits to output bits of the final register, thereby forming a sequence of information to detect errors, and produces a sequence of information for detecting errors in a sequence of transmitted information. The controller of the source transmits values in registers one value selected from two source values determined separately for the first sequence information and the second sequence information.

According to a third aspect of the present invention, an apparatus for checking errors in the received sequence of control data for determining the length of the sequence of data sent on the data channel. The device is used in a communication system comprising a transmitter configured to transmit at least two data sequences of various lengths on the data channel and transmit control channel data of the sequence control data such reproduciendo, as sequence data. The sequence control data has a sequence control information showing the information for each data sequence, and the sequence information to detect errors in the sequence control information. The communication system also includes a receiver that receives the sequence of data transmitted over the data channel from a transmitter, and a sequence of control data that is transmitted via the control channel data from the transmitter. The device includes multiple cascaded registers, the number of which is identical to the number of bits in the sequence information for error detection. Many adders are located on tracts of certain predetermined generating polynomial of paths between registers. Each adder adds a sequence of bits, adopted by the input path, the sequence of bits of feedback and outputs the result of addition through the exit path. Provided the operator for forming, during the reception of a sequence of control information bit sequence feedback by sequentially adding bits of the sequence control information to the output bits of the destination register of the above-mentioned registers and filing of sformirovann the second sequence of bits of feedback adders. After receiving the sequence control information, the operator sequentially adds the specified input bits to output bits of the destination register and outputs the result of addition as the received sequence information for error detection. The controller of the source takes the values in the registers one value selected from two source values determined separately for the two sequences of data. The block decision error compares the adopted sequence information for error detection sequence information for detecting an error corresponding to the selected initial value, thus determining the presence of errors.

According to a fourth aspect of the present invention, an apparatus for checking errors in the received sequence information in a communication system comprising a transmitter, which encodes the first sequence information from the first duration at a given speed of encoding prior to transmission, or encodes the second sequence information with the second duration, which in F times (where F is a multiple of 2) the first duration, a given speed of encoding before sending repeated F times. The transmitter additionally attaches the sequence information for detecting the value of the error to the first sequence information or the second sequence information, and transmits the result as a sequence of transmitted information. The communication system also includes a receiver that receives a sequence of information from a transmitter. The device includes multiple cascaded registers, the number of which is identical to the number of bits in the sequence information for error detection. Many adders are provided on paths, certain predetermined generating polynomial of paths between registers. Each adder adds a sequence of bits, adopted by the input path, the sequence of bits of feedback and outputs the result of addition through the exit path. Provided the operator for forming, during the reception of the received sequence information, the sequence of bits of feedback by sequentially adding bits of the received sequence information to the output bits of the destination register of the above-mentioned registers and supply the generated sequence of bits of feedback adders. After completion of reception of the received sequence information, the operator takes the specified input bit adders, sequentially adds the specified input bits to output bits of the destination register and outputs the result of addition as the received sequence information for error detection. The controller of the source takes the values in the registers one value is the selected from the two original values determined separately for the first sequence information and the second sequence information. The block decision error compares the adopted sequence of data bits to detect errors with a sequence of data bits to detect errors corresponding to the selected initial value, thus determining the presence of errors.

Brief description of drawings

The above and other objectives, features and advantages of the present invention will become clear from the following detailed description with reference to the accompanying drawings, in which

figure 1 illustrates the design of the transmitter control channel packet data in a mobile communication system in which the present invention is applied,

figure 2 illustrates the design of the known block attaching bits of error detection, shown in figure 1,

figure 3 illustrates the structure of a known receiver control channel packet data,

figure 4 illustrates the duration and position of time intervals used in the detection sequence control information receiver figure 3,

figure 5 illustrates the construction of the unit of attachment information for detecting errors according to a variant implementation of the present invention,/p>

6 illustrates the construction of the receiver control channel packet data according to a variant implementation of the present invention, and

Fig.7 illustrates the design of the device for detecting errors in the received bits according to a variant implementation of the present invention.

Description of the preferred embodiments of the invention

Hereinafter will be described the preferred implementation of the present invention with reference to the accompanying drawings. This well-known functions or constructions will not be described in detail in order not to burden the description with unnecessary detail.

According to the present invention is proposed transceiver control channel packet data intended for transmission and reception of control data to control the sequence of packet data in a mobile communication system for transmitting at least two packet data sequences having different lengths. This implies that the control data includes a sequence control information (e.g., title), showing information regarding the transmitted packet data and the control channel packet data is a secondary control channel packet data (WCUPD). A transmitter according to one variant of the present invention contains a block of insertion data for error detection, designed to be attached to the sequence of data bits for error detection to the sequence control information prior to transmission to the receiver is able to correctly determine whether taken in the transmitted control data. In this embodiment of the present invention as a block of insertion data for error detection is typically used generator of the cyclic redundancy code (CEC). The receiver according to one variant of the present invention is a receiver detection blind time interval (LIGHT) for receiving control data transmitted from the transmitter and for determining the length of a packet data based on the received control data. The transmitter and receiver according to a variant of the present invention can be used not only in mobile, but also in the communication system for transmission data sequence, comprising (i) sequence control information that indicates information regarding data to be transferred, for efficient transmission of data sequences and transmission format, and (ii) the sequence of data bits for error detection designed to detect errors in the sequence control information.

To distinguish between sequences of control info is information (or frame control information) of various lengths, due to the structural problems of the conventional control channel packet data, in the preferred embodiment, the present invention provides an improved generator of the CEC and the LIGHT receiver to correct errors in the block of the flow of data received by the LIGHT receiver. In the present embodiment are different initial values of the registers generator CEC not only in personnel management information of the same duration, but also in personnel management information of various lengths to correct the error that has occurred in the frame control information accepted by the LIGHT receiver. That is, in contrast to the known analogue in which the output signals of the convolutional decoders become identical to each other in the processing blocks of the reception frame control information of various lengths, as shown, for example, in figure 3, in the present invention are set different initial values of the registers generator CEC to only one processing unit, the reception was able to determine that the decoder CEC no errors, and thus it was possible to determine the duration of the frame control information.

The concept of "frame control information", "bit errors", "control information" and "packet data"used in the description correspond to the terms of the settlement shall egovernance control information", sequence information for error detection, sequence control data and the sequence data used, respectively, for example, in the claims.

Figure 5 shows a block construction of the attachment information for detecting errors according to one variant of the present invention. Block attaching information to detect errors contains the block 110 attaching bits of error detection, depicted in figure 1, and replaces the generator CEC, shown in figure 2. Generator CEC figure 2 sets of different initial values of its registers only in the case when frames of control information are the same length, i.e. when the frame control information for packet data length 4 time interval and frame control information for packet data length 8 time intervals both have a duration of 4 time intervals. However, the generator of the CEC according to the present invention, depicted in figure 5, different sets of initial values of the registers for frame control information of the control channel packet data of varying duration regardless of the length of frame control information. For example, when 8 bits of error detection is attached to the frame of the panel is engaged in information 8 registers that make up the generator CEC, arbitrarily set at "1" or "0". When the original values are expressed as decimal numbers, these 8 registers are set on the original decimal value between 0 and 255 (=2⁸-1). That is, if the number of registers constituting the generator of the CEC (or the amount of redundant information bits to detect errors), defined as "m", then the original values of the registers in the generator of the CEC can be set to a decimal number between 0 and 2^m-1. For example, the original values of N1, N2, N3 and N4 registers in the generator of the CEC, to be used when transmitting frame control information with a duration of 1 time interval for packet data with a duration of 1 time interval, frame control information with a duration of 2 time slots for packet data length 2 time interval, frame control information with a duration of 4 time slots for packet data length 4 time interval and frame control information with a duration of 4 time slots for packet data length 8 time intervals, can be respectively set to a value between 0 and 255. N1, N2, N3 and N4 can be set to different values. Alternatively, N1 can be set to the same value as N2, N3 or N4. This is attributed to aetsa fact, that only N2 and N3, which was a problem in the conventional generator of the CEC, on different values. Of course, you can set values N1-N4 for some fixed value.

Depicted in figure 5 block attachment information for detecting errors according to one variant of the present invention contains a set of registers 211-218, many adders 221-224, switches SW1-SW3, the output adder 225, and the controller 400 of the original value. The controller 400 of the original value initializes the values of the registers 211-218 on N1 when the transmitted packet data with a duration of 1 time interval. The controller 400 of the original value initializes the values of the registers 211-218 on N2, when the transmitted packet data length 2 time interval. The controller 400 of the original value initializes the values of the registers 211-218 on N3, when the transmitted packet data with a duration of 4 time intervals. The controller 400 of the original value initializes the values of the registers 211-218 on N4, when the transmitted packet data with a duration of 8 time intervals.

After initialization, the values of registers 211-218 output adder 225 performs the binary operation (the exclusive OR operation or the operation modulo 2) between each bit of the input sequence control information and the value is, finally received from the register 218 via a right shift registers values 211-218, and generates a result value of the operation as a sequence of bits of feedback. The generated sequence of bits fed back as an input signal in the source register from the registers 211 211-218 and as input to the adders 221-224. During this operation, the switches SW1-SW3 are all switched on their upper outputs. After you perform this operation on all bits of the 13-bit sequence control information of the switches SW1-SW3 are switched to the lower outputs, so that the switches SW1 and SW2 are set to "0". After this 8 redundant bits are attached by means of shift registers values as many times as there are redundant bits (8).

Block attachment information for detecting errors according to a variant implementation of the present invention is designed to solve problems of the conventional generator of the CEC. That is, even when transmitted frame control information with a duration of 2 time interval indicating the transmission of packet data length 2 time interval, and transmitting a frame of control information with a duration of 4 time intervals, indicating that the packet data transfer duration 4 time interval, the receiver will be able to determine the length of the frame control information and the duration of the transmitted packet data through normal errors. Block attachment information for error detection will be described below with reference to figures 1 and 5.

In the communication system, which encrypts (or encodes convolutional code) first information with the first duration (e.g., packet data length 2 time intervals) with the specified encoding speed (for example, 1/4 rate coding) before it is transmitted and encodes the second information with the second duration that is at most F times greater than the first duration (e.g., packet data length 4 time intervals) with the specified encoding speed before repeated F times the transmission unit attachment information for detecting errors according to a variant of the invention attaches information to detect errors in the first information or the second information. Block attachment information for detecting errors includes a controller 400, the original values and the generator information for error detection. Generator information for error detection consists of a set of registers 211-218, many adders 221-224, the first switch SW1, second switch SW2, the third switch SW3 and the output adder 225.

The controller 400 of the original value receives information about the duration (N time intervals) of the transmitted packet data and submits to the registers 211-218 soo the relevant initial values according to the information about the duration of the transmitted packet data. For example, the controller 400 of the original value takes the first original value during transmission of the first information and delivers the second initial value during transmission of the second information. The first initial value and the second initial value is determined within the value corresponding to the number of bits of information to detect errors. If the number of bits of information to detect errors be defined as m, the first initial value and the second initial value will be different values, defined in the interval 2^m-1.

Generator information for detecting errors includes many cascading registers 211-218, the number of which is identical to the number of bits of information to detect errors. Generator information to detect errors initializes registers 211-218 on the corresponding original values submitted from the controller 400, the original values before sending the transfer information of the first information and the second information. In addition, when transmitting information on the transfer of generator information to detect errors sequentially shifts the registers 211-218. Sequentially shifted bits from the output of the last register from the registers 218 211-218 added output adder 225 to transmit information. The output bits of the output adder 225 served in the source register 211 and ammatory 211-224 as a sequence of bits of feedback through the second switch SW2. In addition, the generator information to detect errors sequentially shifts the registers 211-218 after completion of transmission of the transmitted information. At this point, the output value of the last register 218 is formed as information for detecting errors to attach to the information transmitted via the third switch SW3.

Registers 211-218 include the source register 211, the intermediate registers 212-217 and the destination register 218, each of which has a signal input, signal output, the input source values, connected to receive the initial values of the controller 400 of the original value. The source register 211, the intermediate registers 212-218 and the destination register 218 are connected in cascade through their input and output paths. The output values of the registers 211, 213, 214 and 217 that match the specified paths from the paths of registers 211-218, are added to the output value of the output adder 225 or set value (for example, "0") adders 221-224, respectively, and then served in their subsequent registers 212, 214, 215 and 218. The provisions of adders 221-224 are defined in such a way as to satisfy the specified generating polynomial to generate the information checking cyclic redundancy code (CEC). With this information, the CEC has 8 bits, and generating the polynomial represents g(x)=x⁸+x⁷+xsup> 4+x³+x+1.

When transmitted information transmission, the output adder 225 in the generator information for error detection adds each bit of information transmitted to the output value of the destination register 218 and delivers its output signal to the signal inputs of the source register 211 and the adders 221-224 as a sequence of bits of feedback. After completion of the transmission of information transmitted to the output adder 225 adds the output value of the destination register 218 to the set value "0" and outputs its output signal as information for detecting errors. For this operation is provided by the switches SW1-SW3.

The first switch SW1 has a first input for receiving the transmitted information, a second input for receiving the set value "0" and the output connected to the first input of the output adder 225. The first switch SW1 selects the transmitted information downloaded through the first entrance, or set value "0", received via a second input, and outputs the selected value through the exit. The second switch SW2 has a first input connected to the output of the output adder 225, a second input for receiving the set value "0" and the output connected to the input of the source register 211 and the adders 221-224. The second switch SW2 selects the output signal of the output adder 225, passed through the first input or the set value "0", received via the second input, and outputs the selected value through the exit. The third switch SW3 has a first input connected to the output of the first switch, a second input connected to the output of the output adder 225, and an output for outputting information transmission and information for error detection. The third switch SW3 selects the information transfer or the set value "0", received through the first input or the output signal of the output adder 225, passed through a second input, and outputs the selected value through the exit. However, the design of the case can be made different from the version shown on figure 5, and the register and the adder can be implemented without physical embodiment, as will be clear to experts in the given field of technology.

The output adder 225 and the switches SW1-SW3 form the operator to perform the following operations. Taking a sequence of input information, the operator generates a sequence of bits of feedback by sequentially adding the output adder 225 bits of the input information to the output bits of the final register 218, and supplies the generated sequence of bits of feedback adders 221-224 and produces a sequence of input information as a sequence of information transmitted via the third switch is a switch SW3. Further, after completion of reception of the input information, the operator sequentially adds via the output adder 225 set value "0" to the output bits of the final register 218 and outputs the result of addition of the output adder 225 as a sequence of bits of information to detect errors through the third switch.

6 illustrates the construction of the receiver control channel packet data according to a variant of the present invention. The design of this receiver is identical to the structure of the LIGHT receiver, is shown in figure 3, but differs from it by the fact that the original values of the registers generator CEC blocks are checking the CEC according to the invention. That is, the receiver made according to a variant of the invention, characterized in that 4 block processing technique is used different initial values of the registers generator CEC during the verification of the CEC. This receiver is built on the basis of the LIGHT. In this case, the LIGHT means the method of determining the duration of the transmitted packet data, by estimating in units of time slots of the received frame control information for packet data transmitted from the transmitter. For example, as shown in figure 4, (k+3)-th time interval to determine whether the adopted frame control information cont what lifelessly 1 time interval, and (k+2)-th time interval to determine whether there was successfully received frame control information from the previous (k+3)-th time interval. K is the time interval to determine whether there was successfully received frame control information with a duration of 4 time slots for packet data length 4 time interval, or frame control information with a duration of 4 time slots for packet data length 8 time intervals from the previous (k+3)-th time interval, (k+2)-th time interval and (k+1)-th time interval. During the operation of the detection frame control information is checked for errors (CEC), and the original values that were used to test the CEC on each frame control information, are set at N1, N2, N3 and N4, as described in connection with figure 5.

Depicted in Fig.6 receiver contains 4 blocks 510-540 processing reception intended for determining the length of the packet data transmitted from the receiver. Blocks 510-540 processing reception after reception of the input signal to determine where there is an error in a received input signal, so as to determine the duration of the packet data. While the accepted input, consisting of the demodulated values of the soft decision is with the battle frame control information, having a duration determined according to the number of bits of information in the packet data, which can transmit the transmitter. Thus a typical example of data bits is 13-bit information on WCUPD, which includes a 6-bit control identifier media access (MAC ID), 2-bit channel ID automatic query answer (ARG ID), 3-bit packet size of the encoder and 2-bit identifier of the subpackage. Block 510, the processing of the reception is a block for processing a frame of control information with a duration of 1 time interval corresponding to the packet data with a duration of 1 time interval; block 520, the processing of the reception is a block for processing a frame of control information with a duration of 2 time interval corresponding to the packet data length 2 time interval; block 530, the processing of the reception is a block for processing a frame of control information with a duration of 4 time intervals corresponding to the packet data with a duration of 4 time intervals, and block 540, the processing of the reception is a block for processing a frame of control information with a duration of 4 time intervals corresponding to the packet data with a duration of 8 time intervals.

In blocks 510-540 of obrabotkami blocks 312, 322, 332 and 342 reverse alternation performs reverse interleaving, as many times as the appropriate length of time intervals, and the blocks 314, 324, 334 and 344 reverse punch performs reverse punching in accordance with the appropriate duration of time intervals. In blocks 530 and 540, the processing of the reception frame control information with a duration of 4 time interval blocks 335 and 345 combining characters perform the join operation symbols in two adjacent characters, which is the opposite of the operation of the repeat characters, performed by the block 140 characters repeat in figure 1. After operations reverse punch in blocks 510 and 520, the processing of receiving and combining characters in blocks 530 and 540 reception processing convolutional decoders 316, 326, 336 and 346 in blocks 510-540 processing of receiving perform convolutional decoding. Convolutional decoder 316 for frame control information with a duration of 1 time interval performs convolutional decoding output unit 314 reverse punch with the encoding speed 1/2. Convolutional decoder 326 to frame control information with a duration of 2 time interval performs convolutional decoding output unit 324 reverse punch with the encoding speed 1/4. Similarly, convolutional decoders 336 and 346 on the I frame control information with a duration of 4 time intervals perform convolutional decoding output signals of blocks 335 and 345 combining characters accordingly, the encoding speed 1/4.

On the last steps of blocks 510-540 processing of reception provided by the blocks 518, 528, 538, and 548 validation of the CEC. Blocks 518, 528, 538, and 548 checking CEC checks the CEC on the characters, surtace respectively decoded convolutional decoders 316, 326, 336 and 346. By checking the CEC performed by blocks 318, 328, 338 and 348 check the CEC determines whether there is error CEC frame control information transmitted from a transmitter. Despite the fact that the processing units receiving on 6 separate blocks check the CEC, specialists in the art will understand that the processing units receive can share a single unit test CEC using different initial values of the registers, as illustrated in Fig.7. While checking the CEC blocks 518, 528, 538, and 548 checking the CEC using the specified initial value supplied from the controller 400, the original values described in connection with figure 5. That is, block 518 test CEC detects an error of the CEC by setting the initial values of the register decoder on N1; block 528 checking the CEC finds a problem with the CEC by setting the initial values of the register decoder on N2; block 538 test CEC detects an error of the CEC by setting the initial values of the register decoder on N3, and the block 548 checking CEC detects an error CEC pochemuchelki the original value of the register decoder on the N4. The detector 350 duration packet data determines the duration of the packet data based on the processing results of the reception blocks 510-540 processing technique. This four blocks 510-540 reception processing can be implemented either physically separate processing units, either as a single processing unit receiving using a variety of reception parameters.

Figure 7 presents the design of a device for detecting errors in the received bits according to one variant of the present invention. Device for the detection of errors corresponds to the generator of bits of error detection, illustrated in figure 5, and is similar to him, except that the received bits are fed to the input of the first switch SW1. Device for detecting errors according to a variant of the invention allows to solve problems of the conventional receiver. That is, even when receiving the frame control information with a duration of 2 time interval indicating the transmission of packet data length 2 time interval, and is the frame control information with a duration of 4 time intervals, indicating that the packet data transfer duration 4 time interval, the receiver can accurately determine the length of the frame control information and the duration per the data packet data by the usual error is detected.

Depicted in Fig.7. a device for detecting errors according to a variant of the invention has a capability of detecting errors in the received bits in the receiver, which receives information transmitted from the transmitter that attaches before sending information to detect errors to transfer information (for example, the frame control information of the packet data) of the first information, the first duration (e.g., frame control information with a duration of 2 time interval) or the second information, the second duration that is at most F times (for example, 2 times) exceeds the first duration (e.g., the frame control information with a duration of 4 time intervals). Device for detecting errors includes many registers 561-568, many adders 571-574, the output of the adder 575, switches SW1-SW3, the controller 550 original values and block 580 a decision error.

The controller 550 original values provides the first initial value for the first information and provides the second initial value for the second information to initialize the registers. Provide initial values are determined according to different times (N time intervals) packet data. Preferably, the first initial value and the second initial value is determined within the value, corresponding to the number of attached data bits to detect errors.

Registers 561-568, the number of which is identical to the number of attached data bits to detect errors that are connected in cascade and are initialized to the corresponding original values received from the controller 550 of the original value. Adders 571-574 are located on tracts of certain predetermined generating polynomial of paths between registers 561-568. Each adder 571-574 adds the input sequence of bits accepted by the input path, the sequence of bits of feedback and generates its output signal on the output path. Under the sequence of bits of feedback refers to the sequence of bits at the output of the output adder 575.

The output of the adder 575 and the switches SW1-SW3 form the operator to perform the following operations. The operator when receiving the received sequence information (first or second) generates a sequence of bits of feedback by sequentially adding bits of the received sequence information to the output bits of the final register 568 and delivers the generated sequence of bits of feedback adders 571-574 original register 561 through the second switch SW2. The operator then after completed the I reception of the received sequence information takes the specified input bit "0" in the adders 571-574 and the initial register 561 through the first switch SW1, sequentially adds the specified input bit "0" to the output bits of the final register 568 via the output of the adder 575 and outputs the result of addition as the received sequence information to detect errors.

The first switch SW1 selects the received sequence information or the specified input bit is "0". The first switch SW1 outputs the received sequence information during the reception and outputs the specified input bit is "0" after completion of reception of the received sequence information. The output of the adder 575 adds the output signal of the first switch SW1 to the output bits of the final register 568. The second switch SW2 selects the output signal of the output of the adder 575 or the specified input bit "0" and supplies the selected value to the adders 571-574 and the initial register 561 as a sequence of bits of feedback. The second switch SW2 supplies the output signal of the output of the adder 575 in adders 571-574 original register 561 during the reception of the received sequence information and delivers the original input bit "0" in the adders 571-574 original register 561 after completion of reception of the received sequence information. The third switch SW3 selects the received sequence information or the output sequence of bits, i.e. adopted from the output of the second adder 575 sequence information for error detection. The third switch SW3 outputs the received sequence information during its reception and outputs the accepted sequence information for detecting errors obtained from the output of the adder 575, after completion of reception of the received sequence information.

Block 580 decision error compares the adopted sequence information for error detection sequence information for detecting an error corresponding to the selected reference value to determine whether there is an error in the received bits. That is, block 580 decision error decides that the received bits no error, if the received sequence information for detecting errors is identical to the sequence information for detecting an error corresponding to the selected initial value. Otherwise, if the received sequence information to detect errors not identical sequence information for detecting an error corresponding to the selected initial value, block 580 decision error decides that the received bits are in error. On the basis of the result of the decision block 580 decision error detector 350 duration of service on 6 may determine the duration of the received bits.

As described above, in the device is for detecting errors in Fig.7. the controller 550 original values works depending on the duration of the packet data. When first taken 13 bits transmitted from the transmitter is received completely, the switches SW1-SW3 are switched to their lower outputs, so that the switches SW1 and SW2 receive a given input bit is "0". After 8 bits of error detection (or redundant bits) are formed by shift registers values as many times as there are bits of error detection (8). Block 580 error detection compares the bits of the error detection (attached transmitter)included in the received bits, with the newly-formed bits of error detection. Block 580 error detection decides that the received bits no error, if the bits of the error included in the received bits, identical to the newly formed bits of error detection. However, if the bits of the detection error included in the received bits are not identical to the newly formed bits of error detection, block 580 error detection decides that the received bits are in error. Although in this embodiment the controller 550 of the original value and unit 580 of error detection performed separately, these elements can be implemented in a single controller.

Table 2 shows the simulation results obtained by passing each of the frames of control information with a duration in time intervals 1(2), 2(4), 4(255) and 4(0), 10,000 times in the condition without interference. This is Isla in parentheses indicate original values of the generator of the CEC in the decimal numeral system. In this model, the initial value of the register is set to N1=2 frame control information with a duration of 1 time interval. The original value of the register is set to N2=4 for frame control information with a duration of 2 time interval. The original value of the register is set to N3=255 for frame control information with a duration of 4 time intervals corresponding to the packet data with a duration of 4 time intervals. The original value of the register is set to N4=0 for frame control information with a duration of 4 time intervals corresponding to the packet data with a duration of 8 time intervals. The resultant values obtained by computer simulation, include the probability of successful Pd detection, false probability Pfa, incorrect probability Pm and the error probability PE, the amount of false probability Pfa and incorrect probability Pm. Table 2 shows that the probability of error PE in the detection of frame control information containing 2(4) time interval and 4(255) time interval is very low compared with the respective errors, shown in table 1.

As described above, the mobile communication system for packet data sets of different initial values of the register generator CEC not only in personnel management information of the same duration, but also in personnel management information of varying duration during the transmission and reception of signals on the control channel packet data, which allows to solve the problem of occurrence of error during frame reception, the control information receiver LIGHT.

Although the invention has been illustrated and described with reference to its specific variant, specialists in the art will understand that various changes in form and detail, without going beyond the nature and scope of the claims of the invention described in the accompanying claims. For example, the present invention has been described with reference only to the case when the transmitter control channel packet Yes the tion in figure 1 encodes the sequence of control information with a duration of 2 time intervals for control packet data length 2 time interval bit rate R=1/4 before transmission, and another occasion when the transmitter control channel packet data sequence encodes control information with a duration of 4 time intervals for control packet data with a duration of 4 time intervals at the encoded bit rate R=1/4 and performs the repetition symbols of the encoded control information prior to transmission. However, the present invention can also be applied in the transmitter channel packet data, and the transmitter control channel packet data. That is, the present invention can be applied in the communication system, which encodes the first information with the first duration at a given speed of encoding prior to transmission, or encodes the second information with a length that exceeds at most F times the first time (where the F - number is divisible by 2) with given speed of encoding prior to transmission, repeated F times.

1. Apparatus for forming sequence information for error detection, which is designed for determining the length of the transmitted sequence of data in the communication system configured to transmit at least two data sequences of different length time intervals the data channel and the transmission channel driven the I data sequence control data of the same length, as sequence data and sequence control data includes a sequence control information indicating information regarding a format of transmission data of each sequence data and sequence information for error detection designed to detect errors in the sequence control information containing the set of cascaded registers, the number of which is equivalent to the number of bits in the sequence information to detect errors, many adders, certain specified by the transmitting polynomial and located between registers, each adder adds a sequence of bits, adopted through the input path, the sequence of bits of feedback and outputs the result of addition through the exit path, the operator for input sequence control information and outputting the sequence information to detect errors made with the possibility, during the reception sequence control information, construct a sequence of bits of feedback by sequentially adding bits of the sequence control information to the output bits of the final register of these registers supply the generated bit sequence reverse St is zi in the adders and the issuance of the sequence control information, and after receiving a sequence of control information sequentially adding the specified input bits to output bits of the destination register and the issuing of result of addition as sequence information for error detection, and the controller is intended for filing in the registers of one of the original values, the selected at least two predetermined initial values that are defined separately for at least two sequences of data.

2. The device according to claim 1, wherein the operator includes a first switch for selectively issuing a sequence of control information and the specified input bit output adder for adding the output signal of the first switch to the output bits of the destination register, the second switch to selectively supply the output signal of the output of the accumulator and the specified input bits as a sequence of bits of feedback adders and a third switch for selectively issuing a sequence of control information and sequence information to detect errors from the output of the adder.

3. The device according to claim 2, characterized in that the first switch is arranged to issue a sequence of control information during reception of the sequence yn is alausa information and issuing the specified input bits after receiving the sequence control information.

4. The device according to claim 3, characterized in that the second switch is arranged to supply the output signal of the output of the adder in the adders during the reception sequence control information and the filing of a given input bit in the adders after completion of reception of the sequence control information.

5. The device according to claim 4, characterized in that the third switch is arranged to issue a sequence of control information during reception of the sequence control information and outputting the sequence information to detect errors after completion of reception of the sequence control information.

6. The device according to claim 1, characterized in that the two data sequences have different duration time intervals.

7. The device according to claim 6, characterized in that the duration of one data sequence of the two sequences of data in time intervals two times the length of the other sequence data.

8. Apparatus for forming a sequence of transmitted information by attaching sequence information for error detection to the input sequence of the first sequence information or the second sequence in the information in the communication system, encoding the first sequence information from the first duration of time intervals at a given speed of encoding prior to transmission or encoding the second sequence information with the second duration of time intervals exceeding times in F (where F is a multiple of 2) the first duration, a given speed of encoding prior to transmission, repeated F times, contains many cascaded registers, the number of which is equivalent to the number of bits in the sequence information to detect errors, many adders, a certain predetermined generating polynomial, located between registers, each adder adds a sequence of bits, adopted through the input path, the sequence of bits of feedback and outputs the result of addition through the exit path, the operator to input an input sequence of information and issuance of sequence information for error detection, performed during reception of the input sequence information shaping bit sequence feedback by sequentially adding bits of the input sequence information to the output bits of the final register of these registers supply the generated bit sequence of clicks is Noah communication adders and outputting the input sequence information as a sequence of transmitted information, and after completion of reception of the input sequence information, the filing of a given input bit in the adders, sequentially adding the specified input bits to output bits of the destination register for the formation of sequence information for error detection and delivery sequence information for detecting errors in a sequence of transmitted information, and the controller is intended for filing in the registers of one of the original values, selected from two given initial values that are defined separately for the first sequence information and the second sequence information.

9. The device according to claim 8, characterized in that the input sequence is a sequence of control information that indicates information on the transmission format of the packet data.

10. The device according to claim 9, wherein the first sequence is a sequence of control information with a duration of 2 time interval, and the second sequence information is a sequence of control information with a duration of 4 time interval.

11. The device according to claim 8, wherein the operator includes a first switch for selectively issuing the initial sequence information and the specified input bits, an output adder for adding the output signal of the first switch to the output bits of the destination register, the second switch to selectively supply in the adders of the output signal of the output of the accumulator and the specified input bits as a sequence of bits of feedback and a third switch for selectively issuing the input sequence information and output bits of the output of the adder as a sequence of transmitted information.

12. Device for checking errors in the received sequence of control data for determining the length of a sequence of data sent on the data channel, the communication system includes a transmitter configured to transmit at least two data sequences of different length time intervals the data channel and transmit control channel data of the sequence control data of the same length as sequence data and sequence control data has a sequence control information indicating information regarding a format of transmission data of each sequence data and sequence information for detecting errors in the sequence control information, and receiver the, receiving the sequence of data transmitted over the data channel from a transmitter, and a sequence of control data that is transmitted via the control channel data from the transmitter, containing many cascaded registers, the number of which is equivalent to the number of bits in the sequence information to detect errors, many adders, a certain predetermined generating polynomial, located between registers, each adder adds a sequence of bits, adopted by the input path, the sequence of bits of feedback and outputs the result of addition through the exit path, the operator to enter a sequence of control information and outputting the sequence information to detect errors made by chance during the reception sequence control information shaping bit sequence feedback by sequentially adding bits of the sequence control information to the output bits of the destination register of the above-mentioned registers and supply the generated sequence of bits of feedback adders, and after receiving a sequence of control information sequentially adding the specified input bits to output bits of the destination register and the issuing financial p is Tata addition as the received sequence information for error detection, a controller for submission to the registers of one of the original values, the selected at least two predetermined initial values that are defined separately for at least two sequences of data, and the unit of decision-making error that is designed to compare the received sequence information for error detection sequence information for detecting an error corresponding to the selected reference value to thereby determine the presence of errors.

13. The device according to item 12, wherein the operator includes a first switch for selectively issuing a sequence of control information and the specified input bit output adder for adding the output signal of the first switch to the output bits of the destination register, the second switch to selectively supply in the adders of the output signal of the output of the accumulator and the specified input bits as a sequence of bits of feedback and a third switch for selectively issuing the received sequence control information and the received sequence information to detect errors from the output of the adder.

14. The device according to item 12, wherein the duration of one data sequence of the two sequences of data in time intervals of two times the length of the other sequence data.

15. The device according to item 12, wherein the specified input bit is set to "0".

16. Device for checking errors in the received sequence information in a communication system comprising a transmitter, encoding the first sequence information from the first duration of time intervals at a given speed of encoding prior to transmission or encoding the second sequence information with the second duration of time intervals exceeding times in F (where F is a multiple of 2) the first duration, a given speed of encoding prior to transmission, repeated F times, and anchoring sequence information for error detection to the first sequence information or the second sequence information, and transmits the result as a sequence of transmitted information, and the receiver receiving a sequence information from the transmitter that contains many cascaded registers, the number of which is equivalent to the number of bits in the sequence information to detect errors, many adders, certain predetermined generating polynomial and located between registers, each adder adds a sequence of bits, adopted by the input path, the sequence of bits of feedback which gives the result of the addition via the output path, the operator to enter the mentioned sequence information and delivery sequence information to detect errors made with the possibility at the time of reception of the received sequence information shaping bit sequence feedback by sequentially adding bits of the received sequence information to the output bits of the destination register of the above-mentioned registers and supply the generated sequence of bits of feedback adders, after completion of reception of the received sequence of information supply of the specified input bit in the adders, sequentially adding the specified input bits to output bits of the destination register and the issuing of result of addition as the received sequence information for error detection, the controller for submission to the registers of one of the original values, selected from two given initial values that are defined separately for the first sequence information and the second sequence information, block a decision error, intended for the comparison of the received sequence information for error detection sequence information for detecting an error corresponding to the selected reference value to determine the presence of errors.

17. Give the TWT on P16, characterized in that the sequence information is a sequence of control information that indicates information on the transmission format of the packet data.

18. The device according to 17, wherein the first sequence is a sequence of control information with a duration of 2 time interval, and the second sequence information is a sequence of control information with a duration of 4 time interval.

19. The method of forming the sequence information for error detection, designed to determine whether the transferred at least two data sequences with different length time intervals, in the communication system configured to transmit at least two data sequences of various lengths on the data channel and transmit control channel data of the sequence control data of the same length as the sequence data, the sequence control data includes a sequence control information indicating information regarding a format of transmission data of each sequence data and sequence information globarena errors designed to detect errors in the sequence control information, namely, that provide many of the cascaded registers, the number of which is equivalent to the number of bits in the sequence information for error detection, and many adders, certain predetermined generating polynomial and located between registers, each adder adds a sequence of bits, adopted through the input path, the sequence of bits of feedback and outputs the result of addition through the exit path, served in the registers one initial value, with the length of the sequence data, and the initial value is chosen from the two original values determined separately for the length of the two sequences of data, while receiving a sequence of control information form the sequence of bits of feedback by sequentially adding bits of the sequence control information to the output bits of the destination register of the above-mentioned registers and serves the generated sequence of bits of feedback adders, after receiving the sequence control information sequentially adds the specified input bits to output bits of the destination register and issue achiev that addition as sequence information for error detection.

20. The method according to claim 19, characterized in that the duration of one data sequence of the two sequences of data in time intervals two times the length of the other sequence data.

21. The method according to claim 19, characterized in that the specified input bit is set to "0".

22. Method of forming a sequence of transmitted information by attaching sequence information for error detection to the input sequence of the first sequence information or the second sequence information in the communication system, encoding the first sequence information from the first duration at a given speed of encoding prior to transmission or encoding the second sequence information with a second length that exceeds at most F times, where F is a multiple of 2, the first duration, a given speed of encoding prior to transmission, repeated F times, namely, that provide many of the cascaded registers, the number of which is equivalent to the number of bits in the sequence information for error detection, and many adders, certain predetermined generating polynomial and located between registers, each adder adds a sequence of bits, PR is natou through the input path, to the sequence of bits of feedback and outputs the result of addition through the exit path, served in the registers one source is selected from the two source values determined separately for the first sequence information and the second sequence information, while receiving a sequence of input information, form the sequence of bits of feedback by sequentially adding bits of the input sequence information to the output bits of the destination register of the above-mentioned registers, serves the generated sequence of bits of feedback adders and give input sequence information as a sequence of transmitted information, and after receiving the input sequence information serves the specified input bit adders, sequentially adds the specified the input bits to the output bits of the destination register for the formation of sequence information to detect errors and generate sequence information for detecting errors in a sequence of transmitted information.

23. The method according to item 22, wherein the input sequence of information is a sequence of control information packet data.

24. The method according to item 23, characterized in that Thu is the first sequence information is a sequence of control information with a duration of 2 time interval, and the second sequence information is a sequence of control information with a duration of 4 time interval.

25. The method according to item 22, wherein the specified input bit is set to "0".

26. Method for checking errors in the received sequence of control data for determining the length of a sequence of data transmitted on the data channel, the communication system includes a transmitter configured to transmit at least two data sequences of different length time intervals the data channel and transmit control channel data of the sequence control data of the same length as sequence data and sequence control data has a sequence control information indicating the data rate and transmission format for each data sequence, and the sequence information for error detection designed to detect errors in the sequence control information, and the receiver receiving the sequence of data transmitted over the data channel from a transmitter, and a sequence of control data that is transmitted via the control channel data from the transmitter, namely, the fact provide many cascaded registers, the number of which is equivalent to the number of bits in the sequence information for error detection, and many adders, certain predetermined generating polynomial and located between registers, each adder adds a sequence of bits, adopted by the input path, the sequence of bits of feedback and outputs the result of addition through the exit path, served in the registers one initial value, with the length of the sequence data, and the initial value is chosen from the two original values determined separately for the length of the two sequences of data, while receiving a sequence of control information included in the received sequence control data, form the sequence of bits of feedback via serial adding bits of the sequence control information to the output bits of the destination register of the above-mentioned registers and serves the generated sequence of bits of feedback adders, after receiving the sequence control information sequentially adds the specified input bits to output bits of the destination register and give the result of the addition as the received sequence information to detect errors is to compare the accepted sequence information for error detection sequence information for error detection, corresponding to the selected reference value to thereby determine the presence of errors.

27. The method according to p, characterized in that the duration of one data sequence of the two sequences of data in time intervals two times the length of the other sequence data.

28. The method according to p, characterized in that the specified input bit is set to "0".

29. Method for checking errors in the received sequence information in a communication system comprising a transmitter, encoding the first sequence information from the first duration of time intervals at a given speed of encoding prior to transmission or encoding the second sequence information with the second duration of time intervals exceeding in F times, where F is a multiple of 2, the first duration at a given speed encoding before sending repeated F times, and anchoring sequence information for error detection to the first sequence information or the second sequence information, and transmits the result as a sequence of transmitted information, and the receiver receiving a sequence information from the transmitter, namely, that provide many of the cascaded registers count the number equivalent to the number of bits in the sequence information for error detection, and many adders, certain predetermined generating polynomial and located between registers, each adder adds a sequence of bits, adopted by the input path, the sequence of bits of feedback and outputs the result of addition through the exit path, served in the registers one source is selected from the two source values determined separately for the first sequence information and the second sequence information, while receiving the received sequence information form the sequence of bits of feedback by sequentially adding bits of the received sequence information to the output bits of the destination register of the above-mentioned registers and serves the generated sequence of bits of feedback adders, after receiving the received sequence information serves the specified input bit adders, sequentially adds the specified input bits to output bits of the destination register and give the result of the addition as the received sequence information for detecting errors and compare the accepted sequence information for error detection sequence information for detecting an error corresponding to the selected initial value, that is s thereby to determine the presence of errors.

30. The method according to clause 29, wherein the sequence information is a sequence of control information that indicates information on the transmission format of the packet data.

31. The method according to item 30, wherein the first sequence is a sequence of control information with a duration of 2 time interval, and the second sequence information is a sequence of control information with a duration of 4 time interval.

32. The method according to clause 29, wherein the specified input bit is set to "0".