Module scaled commutator and method for distribution of frames in fast ethernet network

FIELD: data transfer networks, in particular Ethernet-based.

SUBSTANCE: device is made in form of multiple individually programmed single-port communication modules for access to common distributor bus 10, while each single-port communication module has: programmed micro-controller 1, made as access control block for transmitting environment Ethernet (MAC), containing processor with short command list (RISC CPU), and logic device 5 for distribution of data frames, including processing in real time scale and transmission to addresses frame destination ports of Ethernet data, received on said one-port communication module, transfer process is serial and is performed in save-and-send mode.

EFFECT: higher data distribution flexibility control.

2 cl, 7 dwg

 

The invention relates to a modular, scalable structure to build switches fast Ethernet accessing the shared bus data distribution, and to the method of distribution frames in Ethernet mode “save-and-forward store-and-forward).

Currently, the switches for Ethernet networks, in particular the relevant standard IEEE 802.1D, based on two different approaches to the implementation of filtering and frame transmission in an Ethernet network, a:

a) on the basis of the mode save-and-forward store-and-forward)

b) on the basis of the mode cut-off-when-forward cut-through forwarding).

Switches operating in mode “save-and-forward ”, as defined by the IEEE 802.3 standard (edition 1998), remember the incoming data frames completely before their subsequent departure. Function filtering is performed at the time when data frames are received and/or contained in the buffer. Such functions include filtering, for example,

detection of the address and the port definition of the receive (always);

filtering frames that contain errors, by checking CRC (Cycling Redundancy Check, control the cyclic redundancy code) ();

- detection of defective structures frames (always), address data field of the frame frequency frame transmission (partially or never).

The data flow in the switches, operating in dir is IU “save-and-forward (a) schematically shown in Figure 4.

The input buffer 40 is required in this structure, the switch always. Such buffering data seriously affects the operation of the corresponding switch and can lead to the lock state. Short-term congestion arising at the appropriate overload of the receiving port can be balanced in an intermediate buffering. Implementation of the distribution of foster ports depends on the appropriate architecture. One possibility is providing additional buffering data frames associated with receiving or transmitting port, as shown in the form of additional (optional) output buffer 41. The disadvantage of this strategy is that because of the intermediate buffering should be considered additional waiting time for the entire system.

Switches type “save-and-forward systems are usually based processor. The processor or hard logic filters the data set of ports, which are processed sequentially. Typically, processing is performed by copying frame data in a shared memory switch, which also has access to the processor of the receiving port.

According to the strategy of “cut-off-when-forward” (b) data frames are sent immediately after the analysis of the recipient's address, then eats the without intermediate buffering. In comparison with the above strategy (a) the waiting time is minimal, however, no complex filtering cannot be applied, since the frames of data transmitted in real time for distribution. Erroneous or distorted data frames are also transmitted, and accordingly take up expensive bandwidth in the network.

5 and 6 depict two architectures that operate according to the principle of shared memory, in which all of the ports have access to a common field memory.

According to the block structure figure 5, a Central component 50 is responsible for the processing and administration of all incoming data frames. If the number of ports and/or the rate of exchange of data increases, the Central component 50 may become a bottleneck of the whole architecture. In addition, the common data bus 51 is usually heavily loaded, since all data transfer go through the bus. First, the incoming frames are transmitted through a common data bus 51 in the shared memory 52, and then is filtered and transmitted to the Central processor in a centralized component 50. Then the data frames are allocated from the shared memory 52 via the data bus 51 to the output ports 53. Accordingly, each frame of data transmitted on the bus line 51 twice. This explains the fact that the multiplier "2" should be used in the following equation to estimate the required is not bandwidth:

Bandwidth=the number of ports ·the frequency of the input flow· 2=3.2 GB/s (for the case of 16 ports 100 Mbit/s).

This equation is valid only if one frame should be sent to one output port (unicast). For a broadcast (multicast, a single frame to multiple outputs) required bandwidth increases. A typical example of a prototype switching patterns Ethernet according to the method “save-and-forward ” to 16 full-duplex, fast Ethernet channels created by LEVEL ONE, which uses a Central network processor type HR.

6 shows another example for the above-mentioned principle of shared memory having a distributed architecture. All submodules 60 operate independently from each other, when data frames must be shipped only within the corresponding node. The combination of a large number of block elements is provided through a common data bus 61. This distributed architecture is easier to scale, because the increase in the number of ports 62 may be implemented by adding appropriate submodules.

A typical prototype of this type of architecture is a family of GALNETII company GALILEO TECHNOLOGIES, LTD. Pre-frame processing and filtering based on port-by-port (port-by-port basis by hard logic. This, however, is limited to only a few functions, which may not be modified or extended or programmed by the user. In particular, the limiting factor of this type of architecture is the bandwidth of high-speed connection (motherboard). In addition, due to limited bandwidth backplane is necessary to consider a significant reduction in the velocity distribution frames broadcast, if a greater number of ports must be maintained.

Strategy clipping when the shipment has been further developed into the so-called switches cell channel. The input data frames are divided into blocks of data (cells of equal size), thereby providing a fixed time transfer within a distribution unit switch. This gives the opportunity to ensure the independence of the bandwidth of the size of the frame data, the amount of data transferred and the number of ports. In the destination port to defragment and reorganize cells in order to restore the original data frame, usually carried out by perekopirovannye data frames in the output buffer. However, it should be noted that the distribution of data on the basis of cells is not acceptable for applications that are critical from a security perspective, such as on-Board electronics.

Finally, with regard to prototypes that differ IU the od distribution of the data frames is implemented in the switches, built on the basis of a custom LSI, as shown in Fig.7. After analyzing the destination address or address of the recipient connection point-to-point is set via a switch matrix. Compared with the concept of bus, briefly described above, the concept of the switching matrix has the advantage in that it allows the simultaneous existence of many compounds, that is, the bandwidth is increased on request. However, this advantage can be realized only when there is no need to transfer frames multiple ports simultaneously (broadcast). In this case, the full distribution of data is blocked until one of the reception ports is released to obtain the corresponding data frame.

A typical example of this type of architecture - family LS100/LS101 company l-Cube. Ltd.

Technology switching matrix has the following advantages:

- High performance data because many of the compounds can exist at the same time;

- Low latency;

- Pets sequential switching;

- Easy hardware implementation, i.e. high reliability.

The disadvantages of this technology, on the other hand, are:

- Requires a large number of outputs (number of ports *2* bus width of port interface), which means that scalability is limited

- There is no concentration of bandwidth, if frames must be sent to multiple ports recipients;

- Failure of the switching element of the matrix leads to a complete failure of the switch;

There is no programmable processing personnel at ports.

The aim of the invention is the improvement of switches fast Ethernet, as well as known methods distribution data frames Ethernet, so that greater flexibility to manage the distribution of data with a minimum of delay can be achieved based on the concept of “store-and-forward”.

In accordance with the invention, a modular and scalable structure for the development of fast Ethernet switches is achieved by using high flexibility of individual transmission or broadcast transmission with the minimum number of packets, preferably in one package, i.e. one transmission cycle, performing, in accordance with paragraph 1 of the claims, each Ethernet switch individually programmable module with one communication port.

Advantageous variants of the design, modifications, and improvements are the subject of dependent claims and are explained with references to figures in the description.

The method of distribution of data frames Ethernet, organized in the store-and-forward” characterized, in accordance with paragraph 8 claims, building modular, scalable structure, consisting of individually programmable single-port communication modules, which are organized for the internal transmit data frames so that each port after receive, save, and verify the integrity of the data frame is competing for access to high-speed bus interchange, which is the scheme of the arbitration on the basis of number and port ID. Then the corresponding data frame is transmitted to one or more receiver (output) ports, preferably within one cycle of the data frame. Output ports independently decide, in accordance with the status of the associated output buffer, you must accept or reject the corresponding transmitted data frame.

It is desirable that the data frames are received by the communication module, were filtered in real time, at least, bandwidth, frame size and address fields of the frame, in particular, the control processor with a reduced instruction set (RISC). It is advantageous if the specified control process, in accordance with the invention, can be quickly changed in volume filtration using reloadable configuration parameters.

A particularly advantageous property of the invention is that, in kr is ina least one data port interface modules can be specifically assigned, according to the special configuration tables, or prior to, or during operation, for monitoring the flow of information, in order to filter and capture some frames of data for analysis of the flow of information without the cost of additional bandwidth on the backplane.

Another advantage of the invention is that any desired maximum delay switch having a value that is less than a predetermined, is determined only by the size of the output queue single-port communication module. Some advantage may be achieved using the present invention in the case, if all, or at least one data port interface modules configured to perform one or more administrative and/or control functions, for example, by execution of the simple network management Protocol (SNMP)management database (MV), in particular for the organization structure of the Ethernet switch, providing the necessary network addresses and/or sequence level application that is available for network level through any single-port communication module.

A particular advantage of the invention is that the structure of the data received from a particular port of the communication module are processed in real-time filtered is eat, at least regarding the bandwidth, frame size and address of the frame by processing on a reduced set of commands that operate at the network level two, i.e. at the level of management access to the transmission medium (MAC).

Further, in order to avoid redundant explanations for a well-informed reader will use abbreviations, which, however, are explained in the text.

The invention is advantageous details and design options will be described below with reference to the accompanying figures, in which:

1 shows a functional diagram of the single-port communication module according to the invention;

Figure 2 shows blocks the interaction of the functional elements of the software, as an example for a typical single-port communication modules according to the invention;

Figure 3 shows the block diagram of the distribution type “save-and-forward”;

Figure 4 shows the principle strategy “save-and-forward according to the invention (already explained);

Figure 5 shows a centralized architecture for processing, and sending the incoming data frames using shared memory according to the prior art (already explained);

Figure 6 shows the distributed architecture of an Ethernet switch according to the prototype, including an independent sub-nodes (already explained);

7 shows stroenie Ethernet switch-based custom LSI for connection type to point-to-point switching matrix according to the prior art (already explained).

The hardware structure of a typical example of embodiment in accordance with the invention and its interaction with standard software elements described hereinafter with reference to figures 1, 2 and 3.

Functional block diagram Figure 1 the Ethernet signals are served, for example, via a shielded twisted pair for each direction with galvanic separation by a magnetic junction in the transformer 12. Followed as a physical device, a transceiver 13, that is, Ethernet transmitter/receiver is responsible, among other things, for the conversion of serial code to parallel and back and for managing the coding in the channel. The transceiver 13 is connected with Ethernet control block access to the transmission medium (MAC) 1, which contains a Central processing element with a reduced instruction set (RISC CPU). In this block MAC+RISC CPU 1, responsible for structuring and processing of incoming Ethernet frames, the Central processor item CPU performs step execution in each cycle commands from the reduced set. Block 14 is a serial interface according to RS-232, asynchronous start and stop bits and parity, the corresponding COM interface of a personal computer with a maximum speed of 115 kbit. MAC+RISC CPU 1 is connected via the system bus, with the standing, for example, of 32 bits, on the one hand, with a dual port random access memory device (DPRAM) 4, and on the other hand - with a dynamic random access memory device (DRAM) 3, which interacts with the functional module direct memory access (DMA) 2, carrying forward the memory of the memory independently of the CPU 1. Erasable software permanent memory (EPROM) 6 is connected through the system bus from the CPU 1, the DRAM 3 and DPRAM 4. DPRAM 4 and subsequent logic distribution frames 5, including high-speed resolver 9, service-port interface modules that make up the Ethernet switch according to the invention, figure 3, is connected, on the one hand, with high-speed data bus 10, and on the other hand, through high-speed resolver 9 - bus arbitration and control 11.

Typical functional elements of the software single-port communication modules according to the invention shown in figure 2. These functional elements of the software include:

- configuration table 20 contained in the erasable ROM (EPROM), define the function modules;

operating system real-time, 21;

loader 22 to load the configuration and tasks, checks and communication with the unit/service user.

- control function and application blocks 23, which are the module (what odusami) software for control, registration etc. of operational parameters;

- Simple network management Protocol (SNMP) in block 25, then there is a Protocol to transfer / exchange of operational parameters;

- Database management (MV) 24, including a system for the classification and coding of operational parameters;

block Protocol stack 26, are required to establish a connection and exchange data, including the transmission control Protocol (TCP)Protocol user data (UDP) and Internet Protocol (IP);

- many software modules 27 for monitoring and testing network and traffic data;

- hardware-software module 28 for switching and monitoring port, i.e. for switching Ethernet frames and to display the exchange of data on the port/channel.

In this context, the filtering flow of information means filtering the data according to certain criteria, such as frame size, locations, etc. Services of strategy management (policing services) refer to the control/monitoring of data flow with respect to a certain data rate and bandwidth.

Below is described the principle of operation.

When using a programmable one-port communication modules according to the invention for switches fast Ethernet transfer process is strictly sequential in nature, corresponds to disciplinename load (work-conserving service disciplines) and arranged to store-and-forward” mentioned above. Checks the integrity of the frame before the start of the transfer process involves a mechanism to store-and-forward. To provide maximum certainty, as required, for example, in the on-Board equipment, this project according to the invention involves the execution strictly on the specified schema.

The mechanism works in such a way that the port after receiving and processing the correct and full frame, i.e. after filtering data flow testing strategies, updates (internal) the title of this frame together with relevant information about the shipment (CAM-vector) in the frame buffer, that is, in DPRAM 4, so that this structure was marked for shipment. It is high-speed logic distribution frames switch 5, which, as shown in figure 1, has access to the DPRAM 4.

Upon completion of the competition for access to high-speed internal bus data distribution switch 10 the logic of the distribution of the data/frame 5 now passes the full frame one (unicast) or multiple (multicast) output ports of destination in one package in accordance with a specified vector ITSELF. Any output port independently decides, in accordance with the status of its output buffer, which again is the port associated with DPRAM 4, to accept or reject sent the frame in accordance with the requirements of the internal time delay is, explained below in detail.

As an example, for a switch with 16 ports, baud rate on the wire determines an internal transmission time frame of approximately 420 NS per frame (i.e. 16·148800 frame minimum size per second=2.4 million frames per second).

The speed of data transfer on the bus data distribution 10 high enough to serve all ports ("for example, up to 16 ports), continuously passing a 64-byte frames with wired speed. Due to the structure of single-port module, filtering the data flow port can easily be implemented in real-time, frame-by-frame, which implies that the required speed of the switch depends on the transmission speed on the bus 10 (patch panel).

The transfer process through the allocation logic frame 5 is as follows:

The internal mechanism of the distribution of the data is running so that the port, receiving and verifying a complete frame is stored in the DPRAM 4, competes for access to high-speed bus data distribution 10 module. Decentralized speed arbitrators 9 installed in the node logic distribution frames 5 each port of the communication module according to the scheme a fair arbitration (fair arbitration scheme) provides access to the bus 10 in accordance with the port number or identifier. Then then is passes the frame to one (unicast) or multiple (multicast) output ports in one package. Each output port, in accordance with the status of its buffer, independently decides whether to accept or reject the transmitted frame.

In accordance with the invention, the maximum waiting time can be configured, as explained below:

Waiting time is defined as the difference between the arrival time of the first bit of the frame and the departure time of the first bit of the last instance of the same frame from the switch, where the term “last instance” refers to broadcast forwarding, when the copied frames can leave the switch at different points in time.

As described below, any additional delay due to the internal data switch and functions of the shipment is equal to zero, and any desired maximum waiting time less than tbd <SIC - approx. books> milliseconds is determined by the size of the output queue of the switch are stored in DPRAM 4.

Example:

The desired maximum waiting time should be 1 msec. For frames with 64 byte MAC size data size of output queues must be designed such that they could contain 149 personnel, in strict accordance with the transmission rate in the environment 100 Mbit/s interframe interval of 96 bits. For frames that have a length greater than 64 bytes, the number of frames stored in the output queues, sootvetstvenno is reduced. This is due to the fact that the number of frames that can be transmitted at a fixed speed in the environment 100 Mbit/s, in the interval TR=1 MS decreases with increasing length frames.

In the output queue DPRAM 4 have the capacity

149*(the size of the internal message block for 64-byte frames) [bytes].

Depending on the status/level of the output queue (output queue), any port independently decides whether to accept or reject frame sent by the internal logic of the data distribution. The size of the output queue single-port communication module is configured software or to download the configuration settings in the process.

Following programmable functions:

Monitoring data flow: assuming that the number of single-port modules is n, one or more of them can perform this task. The primary goal of port control is to filter and capture some footage for flow analysis.

Port control has a special configuration table, which allows you to choose which MAC address of the destination among a group of input ports, except the port control must be rewritten texts on the output monitor port. The configuration table 20 allows a user to select one or more MAC addresses that reach the switch, and about Silat them through the monitor port.

All ports that are not assigned to monitor data flow, constantly send a copy of each received valid frame in the monitor port, without taking up more bandwidth high-speed data buses 10. It is provided with built-in broadcast properties data bus described above. The configuration table port control determines which of these frames should be selected for transmission, for example, the MAC destination address. All other frames are ignored. Therefore, changes in the configuration of the monitoring does not affect the table transfer related to all other ports.

The ability of the filter/strategy thread: Each received frame can be evaluated relative to specific application parameters specified in the configuration table in the EPROM memory 6. Since the function of filtering/strategies are implemented programmatically due to the availability of a MAC+RISC CPU 1 on each port, then any algorithm can be used depending on specific application requirements. In the on-Board equipment important services filtering expand (but are not limited to):

bandwidth and control jitter (jitter);

control the length of the frame;

control addresses block;

control data frame, and others.

For example, the bandwidth monitoring and control of jitter which may be carried out thanks to the introduction of the magnitude of the budget, associated with the frame, which is based on the following parameters:

interval bandwidth (expressed in seconds)associated with a particular MAC address,

- the maximum value of the magnitude of the budget according to the jitter value, expressed in seconds, associated with a specific MAC address.

The basic concept and purpose describes the architecture of the switch according to the invention is the provision of optimal bandwidth and performance data for all functional blocks between any pair of ports of entry and exit, so that could be achieved steady state (sustained) wired speed. This includes the performance of the functions of filtering/strategy data flow port, mainly achieved (as an example) 32-bit MAC+RISC CPU 1, is allocated to each port.

You can give an example to evaluate the performance:

The maximum load on the input port of the switch is formed by the recruitment of a minimum size, for example, 64 bytes of the data field of the MAC corresponding to 18 bytes of user data using UDP/IP, with minimum interframe gap of 12 bytes. When the speed of information transfer in the environment, for example, 100 Mbit/s, this gives 149 frames/msec. According to the structure of the MAC frame no IEEE 802.3 and no sign of title standard 802.1 p/1Q, nieuwehorne 4 bytes, full size MAC frame is 84 bytes.

Device Ethernet MAC, installed in each switch port that is capable of storing not only the data unit MAC Protocol, but also the so-called internal message block, which also includes a CRC field, the MAC addresses of the source and destination field type/length, as well as other special information, for example, timestamp, status, signs, vector ITSELF, etc. used to control the switches. In the worst case, the minimum size of the internal message block consists of 128 bytes (=32·4 bytes, i.e. a 32 bit word <SIC, approx. books>), processing power RISC processor that is required to control the bandwidth, that is, the strategy of the calculation of the budget, as well as to update the message block to reach the following values of instructions per second (IPS):

The remaining model the filtering function of the flow, i.e. the filtering of frames by the MAC destination address may be assessed in an additional ~2.25 MIPS, thus, the full load on the CPU reaches ~10 MIPS for ports operating at full wire-speed and minimum frame size. When using a single MAC+RISC processor 1 on one port at 10 MIPS, filtering frames in real-time mode, the frame-by-frame, can be provided even in full the th wire-speed.

The time required to filter the stream data of one frame will be

10 MIPS/149·103frames ≈67 IPS/frame that gives 1.34 μs when the cycle time of the processor 20 NSEC, that is, for a 50-MHz RISC processor 1; at 33 megahertz calculation time will reach 67·33 NSEC=2.2 μs.

Received frames are transmitted in 3 DRAM controller direct memory access, part of the MAC+RISC CPU 1. At full wire-speed frames with 64 bytes of data MAC have the length of the transmission frame ~5.76 μs, followed by the interval 0.96 msec to 12 octets interframe gap. This gives the minimum transmission time 6.72 microsec one frame.

Thus, it is only 1.34/6.72=20% (2.2/6.72=33%, respectively), the minimum transmission time of a frame, which effectively means that any additional delay due to the internal data switch and function of departure is equal to zero, and the desired maximum waiting time less than 1 msec is determined only by the length of the output queue of the switch.

This statement is true only if the time t0=0 for the frame has been transferred and stored in the DPRAM 4. Then immediately begins the process of filtering frame and runs in parallel with the process of obtaining the next frame in the MAC+RISC CPU 1 (step pipeline).

Next, description is s features network management:

Modular switch architecture according to the invention enables access to public information through simple network management Protocol (SNMP), to the basis of management information (MIB) by, for example, using data Protocol user/Internet Protocol (UDP/IP), and simple network management Protocol on MAC+RISC CPU 1 any port that is indicated by reference 8 in figure 2. The interface is designed so that the SNMP Protocol is used to obtain this information.

For internal SNMP traffic was not too broad bandwidth connection Board switch, which may reduce the performance, i.e. to increase the timeout, instead, can use bus shared memory direct memory interface (DMI) 2. The block DMI 2 provides separation, for example, 16-bit bus and enables the exchange of data stored in the local memory of each processor, that is, 3 DRAM, EPROM 6 and DPRAM 4.

Further, in case of failure of the port within its switching services, this approach still allows you to control MAC+RISC CPU 1, upon receiving the status information/errors on the corresponding defective port, which will not provide, for example, a mixed data flow status information on the connection Board.

1. Modular scalable architecture switch fast Ethernet, the tives such as those the Ethernet switch is made in the form of a multitude of individually programmable single-port communication modules for access to a common distribution bus (10), with each single-port communication module includes a programmable microcontroller (1), designed as a unit to control access to the transmission medium to Ethernet (MAC)containing a processor with a reduced instruction set (RISC CPU), and a logical device (5) distribution of personnel data, providing real-time processing and transmission of addressable destination ports Ethernet data frames received at the specified port of the communication module.

2. The architecture of the fast Ethernet switch according to claim 1, characterized in that each individually programmable single-port communication module contains a dual-port frame buffer (4), is designed to interact, on the one hand, to the programmable microcontroller (1) and, on the other hand, with the specified logical device (5) distribution data in such a way that accepted the right frame of data is updated, at least in part information on the transfer (the vector) in the specified frame buffer (4)to be suitable for transmission over said bus data distribution (10).

3. The architecture of the fast Ethernet switch according to claim 2, characterized in that it contains a logical device (9) of the arbitration, organizowanie so, it is made in a decentralized and contains each of these individually programmable single-port communication modules, with the specified device is interconnected with a corresponding one of the logical devices (5) distribution data frames to provide access to correct data frames to the said bus data distribution (10) according to a fair distribution of access rights and the scheme of control signals based on the numbering of ports or identification.

4. The architecture of the fast Ethernet switch according to claim 1, characterized in that the said programmable microcontroller is configured to access for individual programming via the interface block.

5. The architecture of the fast Ethernet switch according to claim 4, characterized in that the said interface unit is RS-232.

6. The architecture of the fast Ethernet switch according to claim 1, characterized in that it further comprises a direct memory interface (DMI 2)associated with DRAM (dynamic random access memory) (3) to perform direct memory operations memory and/or communication of control data and/or status information in the event of a failure in the logical device (5) distribution data frames or data bus (10).

7. A method for distributing data frames Ethernet mode store-and-send”using modular scalable architecture individually programmable single-port communication modules, includes the following operations: provision modular scalable architecture individually programmable single-port communication modules organized for the internal distribution of data frames so that each port after receive, save, and frame check data integrity compete for access to high-speed bus data distribution according to a fair arbitration scheme, based on the numbering or identification of ports, the transmission of the corresponding data frame, at least one output port for a specified number of cycles of the data frame, and the operation decision-making in such a way that each output port independently of each decides in accordance with its status output buffers to accept or reject the corresponding transmitted data frame.

8. The method according to claim 7, characterized in that the said number of cycles of the data frame is one and only one, regardless of the number of output ports of concurrent mentioned individually programmable single-port communication module.

9. The method according to claim 7, in which data frames received referred to individually programmable single-port communication module that is processed in real time by filtering at least across the width of the strip, the frame size and address the Adra through the control process, at the network level 2 (level network access - MAC) using a reduced set of commands.

10. The method according to claim 9, characterized in that the above control process is variable from the point of view of the volume filtration using reloadable configuration parameters.

11. The method according to claim 7, characterized in that at least one of these individually programmable single-port communication modules can be assigned to a special configuration tables before and/or during work time to perform flow monitoring data to provide filtering and capture some frames of data for data flow analysis.

12. The method according to any of the preceding paragraphs, characterized in that any desired value switching delay that is less than a predetermined time is determined only by the length of the output queue individually programmable single-port communication module.

13. The method according to item 12, wherein the at least one individually programmable single-port communication module configured to perform at least one function administration/management.

14. The method according to item 13, wherein the specified at least one function administration/management simple network management Protocol (SNMP) and/or database from the management (MIB) to provide access to information about the architecture of the Ethernet switch, providing the appropriate network address and the application level (consistently for network level 7), accessible through any individually programmable single-port communication module.



 

Same patents:

FIELD: data package transmission in mobile communication lines.

SUBSTANCE: device for controlling data package transmission in mobile communication line, which has base receiving-transmitting system (RTS) provided with buffer for storing data packages to be transmitted to mobile station, has base station controller (BSC) for comparing size of RTS buffer with number of non-transmitted data packages after data packages are received from common use data transmission commutated circuit (CUDTCC). Non-transmitted packages have to be packages which have been transmitted from BSC to RTS but still haven't been transmitted from BSC to RTS. Transmission of data packages is performed if size of buffer exceeds number of non-transmitted data packages.

EFFECT: prevention of overflow of internal buffer of base receiving-transmitting system; prevention of efficiency decrease caused by next cycle of data package transmission.

19 cl, 15 dwg

FIELD: telephone communication systems combined with other electronic systems.

SUBSTANCE: proposed telephone communication system that can be used for voice communications between subscribers of local telephone networks by means of public computer networks has telephone set, local telephone communication line, interface unit, analog-to-digital converter, signal distributor, voice identification device, voice-frequency dialing identification device, pulse dialing signal detector, identified number transmission device, coder, compressor, computer, public computer network, decompressor, decoder, voice recovery device (voice synthesizer), called number information converter, voice and called signal transfer queuing device, and digital-to-analog converter.

EFFECT: enhanced quality of servicing subscriber using public computer network; enlarged functional capabilities of system.

1 cl, 1 dwg

FIELD: radio communications.

SUBSTANCE: radio network controller sends value of power deviation for controlling power of transfer of high-speed dedicated physical control channel of ascending communication line, when user equipment enters service transfer zone, in cell communication system, containing radio network controller, assembly B, connected to said controller and user equipment, being in one of at least two cell nodes, occupied by assembly B. assembly B sends data to user equipment via high-speed jointly used channel of descending communication line and user equipment transfers data, notifying about data receipt state, to assembly B along ascending communication line. Controller sends to user equipment a value of deviation of power to determine transmission power adjustment for ascending communication line, if it is determined, that user equipment is within limits of service transfer zone. Controller sends to assembly B value of power deviation, to allow assembly B to determine threshold value for data determining, noting data receipt state, dependently on power deviation.

EFFECT: high-speed data delivery to user equipment.

5 cl, 31 dwg, 4 tbl

The invention relates to the transmission of data to generate codes using turbocodes in the communication system based on retransmission

The invention relates to a method of signaling between peer-to-peer (equal) levels control the medium access (MAC) packet access high speed direct lines of communication (PDSP) in the communication system, multiple access, code-division multiplexing (mdcr)

The invention relates to information transmission networks

The invention relates to communication technology, and in particular to a communication system in which a user transmits data variable speed

The invention relates to a method for network communication

The invention relates to data transmission systems

The invention relates to systems for the transmission of data lines shared tire using a variety of interfaces

The invention relates to communication technology and can be used to speed up the process of exchange of information between smart devices

The invention relates to cellular telephone systems, specifically to a system for increasing the reliability of the cellular telephone system in environments with multipath transmission of signals, or in conditions in which a large number of mobile phone units simultaneously try to access the base station

FIELD: data transfer networks, in particular Ethernet-based.

SUBSTANCE: device is made in form of multiple individually programmed single-port communication modules for access to common distributor bus 10, while each single-port communication module has: programmed micro-controller 1, made as access control block for transmitting environment Ethernet (MAC), containing processor with short command list (RISC CPU), and logic device 5 for distribution of data frames, including processing in real time scale and transmission to addresses frame destination ports of Ethernet data, received on said one-port communication module, transfer process is serial and is performed in save-and-send mode.

EFFECT: higher data distribution flexibility control.

2 cl, 7 dwg

FIELD: physics; control.

SUBSTANCE: invention relates to control for actuating safety equipment. The invention discloses a control unit and a method of actuating safety equipment, as well as a sensor for outputting an emergency signal. The control unit for actuating safety equipment includes at least one interface which outputs a digital information signal, which includes multiple simultaneously turned on current sources for acting on the front of the digital information signal.

EFFECT: providing electromagnetic compatibility of control signals.

10 cl, 6 dwg

FIELD: radio engineering, communication.

SUBSTANCE: invention relates to wireless communication systems, where access to a communication channel is restricted with periodic intervals. A system and a method involve an assessment of the first probability of collisions in a channel at the beginning of the intermittent channel interval, where the assessed probability of collision is increased at detection of a transmission error in the section of one or more preceding channel intervals; setting of the size of a competitive transmission window at the beginning of the current channel interval in compliance with the assessed first probability of collisions in the channel; assessment of the second probability of collisions for the next channel interval; and dynamic size variation of the competitive transmission window for the next channel interval in compliance with the assessed second probability of collisions in the channel.

EFFECT: reduction of data losses at transmission.

16 cl, 13 dwg

FIELD: radio engineering, communication.

SUBSTANCE: invention relates to a method of transmitting data telegrams (13a, 13b) from a transmitter (11a) to at least one receiver (11b), wherein the data telegrams (13a, 13b) to be transmitted are associated with a priority level which, during transmission of the corresponding data telegram (13a, 13b), specifies a priority to be considered. In the transmitter (11a) each priority level is associated with an intermediate storage area (17a, 17b); the data telegrams (13a, 13b) are transmitted over a physical communication medium (12) through different logical data connections (15a, 15b), wherein the number of logical data connections (15a, 15b) corresponds to the number of priority levels; data telegrams (13a) in the intermediate storage area (17a) associated with a lower priority level are transmitted through the logical data connection (15a) associated with said priority level until at least one data telegram (13b) is present in the intermediate storage area (17b) associated with a higher priority level, and the data telegram (13b) in the intermediate storage area (17b) associated with the higher priority level is transmitted through the logical data connection (15b) associated with the higher priority level.

EFFECT: transmitting data telegrams with different priority levels at a relatively low cost and therefore faster.

9 cl, 2 dwg

FIELD: physics, communications.

SUBSTANCE: invention relates to means of controlling access to a transmission medium for controlling access of a busbar user station, having first and second channels, to a second busbar channel shared by multiple user stations. The first channel is opened for exclusive access by a user station during at least one time interval for granting access, the beginning of which is defined by the user station through bitwise arbitration of the first channel, the end of which is defined once the user station frees it again after successful arbitration of the first channel. Access to the second channel shared by multiple user stations is controlled so as to open the second channel for access by the user station only during said time interval for granting access without separate arbitration to obtain access to the second channel.

EFFECT: high volume of transmitted data without deterioration of system performance in real time.

13 cl, 5 dwg

FIELD: communication.

SUBSTANCE: invention relates to network communication technologies. Disclosed is method of serial interface in bus system containing two bus subscribers, exchanging messages by bus, wherein sent messages have logic structure corresponding to ISO 11898-1 standard for CAN protocol, said logical structure includes frame starting bit, arbitration field, control field, data field, cyclic redundancy code (CRC), acknowledgement field and sequence end frame, control field includes data length code containing information on data field length, characterised by that in presence of first mark (EDL) control field in messages comprises, in contrast to ISO 11898-1 standard for CAN protocol, more than six bits, wherein first mark (EDL) is implemented by recessive bit in control field, and in presence of first mark after recessive bit of first mark (EDL) in all information messages should be at least one dominant bit (r0, r1).

EFFECT: technical result consists in improvement of data transmission speed.

21 cl, 5 dwg

FIELD: information technology.

SUBSTANCE: present invention relates to network communication technologies. In method access to bus for sending any message is provided to a bus subscriber which becomes sender of said message, according to an arbitration method of corresponding standard ISO 11898-1 on CAN protocol, messages have a logic structure corresponding to CAN protocol standard, that is, consist of a start-of-frame bit, arbitration field, control field, data field, cyclic redundancy check (CRC) field, acknowledge field, and end-of-frame field, function of data transmission is checked during transmission by comparing a sent signal sent to bus connection unit with received signal (CAN_RX) received by the bus connection unit, method is characterised in that a sent signal (CAN_TX_DEL) delayed by a delay time (T_DELAY) compared to sent signal (CAN_TX) is held in sender, and undelayed sent signal (CAN_TX) or delayed sent signal (CAN_TX_DEL) is used for checking correct function of data transmission depending on a switchover.

EFFECT: technical result is faster data transmission in network.

33 cl, 3 dwg

FIELD: radio communications.

SUBSTANCE: radio network controller sends value of power deviation for controlling power of transfer of high-speed dedicated physical control channel of ascending communication line, when user equipment enters service transfer zone, in cell communication system, containing radio network controller, assembly B, connected to said controller and user equipment, being in one of at least two cell nodes, occupied by assembly B. assembly B sends data to user equipment via high-speed jointly used channel of descending communication line and user equipment transfers data, notifying about data receipt state, to assembly B along ascending communication line. Controller sends to user equipment a value of deviation of power to determine transmission power adjustment for ascending communication line, if it is determined, that user equipment is within limits of service transfer zone. Controller sends to assembly B value of power deviation, to allow assembly B to determine threshold value for data determining, noting data receipt state, dependently on power deviation.

EFFECT: high-speed data delivery to user equipment.

5 cl, 31 dwg, 4 tbl

Up!