Message exchange module

FIELD: computers.

SUBSTANCE: device has a group of buffer blocks from first to eighth, direction correction block, direction selection block, first registers group, output register, first decoder, multiplexer, first counter, group of switchboards from first to eighth, launch trigger, first and second univibrators, OR elements from first to third, first and second AND elements, clock pulses generator. Also inserted are buffer block, second and third registers group, second decoder, a group of demultiplexers from first to eighth, second counter, third univibrator, first and second groups of OR elements and fourth and fifth elements.

EFFECT: higher efficiency.

10 dwg, 1 tbl

 

The invention relates to the field of computer engineering and can be used when building the switching means multiprocessor computing and control systems, subscriber communication systems with decentralized management and information-measuring systems.

Known matrix switch module containing three blocks Queuing messages, register the module ID, the unit of analysis message queue, multiplexer, register, demultiplexer, trigger, synchronization unit, two elements of comparison, two decoder and the element And (A.S. 1575167, USSR G 06 F 7/00, 15/16; publ. 30.06.90, BI No. 24).

The disadvantage of this module is the inability dynamic modification of the communication routes and, as a consequence, the narrow scope.

Closest to the proposed module on the technical nature of a forming device route messages in a homogeneous computing system containing a group of blocks of the buffer memory, three register, trigger, counter, block compare block direction, clock, demultiplexer, multiplexer, decoder, two elements And group elements And three elements, OR three one-shot, two delay elements (A.S. 1287172, USSR G 06 F 15/16; publ. 30.01.87, BI No. 4).

The disadvantage of this device is impossible is here dynamic modification of routes messages depending on the load queue modules, located at a distance of 2 from the current (virtual neighbors). This leads to an increase of the uneven load on the switch and possible loss of messages, narrowing the scope of application of the device.

Technical problem on which the invention is directed, is to expand the field of use of the device based on its constituent blocks, enabling dynamic modification of routes messages depending on the load queues as close neighbors, and virtual neighbors. The conditions of the virtual queues neighbors allows you to redirect messages on the best areas and to reduce the overall load on the switch.

The technical problem is solved in that module to exchange messages containing the group buffer blocks from the first to the eighth, the correction block direction, the block direction, the generator of clock pulses, the first group of registers from the first to the second output register, the first decoder, multiplexer, the first counter, a group of switches from the first to the eighth, trigger start, from the first to the third adenovirally, from first to third elements OR the first and second elements And the first information input unit of choice is the entry address of the module, the output of the correction block direction is connected with the second information which was input unit direction, the reset input module connected to the reset inputs of all the buffer blocks of the group, to the reset input of the output register to the reset inputs of all the registers of the first group, the outputs of the first decoder from the second to the ninth connected with control inputs of the buffer units of the group from the first to the eighth, respectively, the first outputs of which are connected to information inputs of the multiplexer, second, third and ninth, respectively, the output of the first counter is connected with the control input of the multiplexer and to the input of the first decoder, the output of the multiplexer is connected to information inputs of all the registers of the first group, the first one-shot is connected to the input setup trigger start, the outputs of all registers of the first group connected with the first information inputs of each switch group, the output of the second register of the first group is connected with the information input of the output register, the output of which is the first output of the receiving module, the outputs of each switch group connected to the corresponding outputs of the module, the output of the first element OR connected to the inputs of the first and second odnovorov, also includes a buffer unit, the second and the third group of registers, the second decoder group demultiplexes the second counter, the first and second group of adders, first and second trigger group, the first and the which group of elements OR the fourth and fifth elements OR, with the output of the first register of the first group is connected with the third information input unit direction, the reset input module connected to the reset input of the buffer block to the inputs of the reset all flip-flops of the first and second groups, all registers of the second and third groups, to the first inputs of the second, third, and fifth elements OR the first output of the first decoder is connected with the control input of the buffer unit, the first output buffer unit connected to the first information input of the multiplexer, the most significant bit inputs of the module from the first to the eighth connected with the first inputs of the elements OR the first and second groups the first through eighth, respectively, and inputs the synchronization registers of the third group from the first to the eighth, respectively, the low-order bits of the input module from the first to the eighth connected with the second inputs of the elements OR of the first group from the first to the eighth, respectively, and the first inputs of the synchronization buffer block group from the first to the eighth, respectively, the second bit of the input module from the first to the eighth connected with the second inputs of the elements OR the second group from the first to the eighth, respectively, the outputs of the elements OR of the first group from the first to the eighth connected to the counting inputs of the triggers of the first group from the first to the eighth, respectively, the output element is in OR the second groups from the first to the eighth connected to the inputs of the timing registers of the second group from the first to the eighth, respectively, the direct outputs of the triggers of the first group from the first to the eighth connected with control inputs of demultiplexes group from the first to the eighth, respectively, the inputs of the module from the first to the eighth connected to information inputs of demultiplexes group from the first to the eighth, respectively, the first outputs of which are connected to information inputs of the registers of the second group from the first to the eighth, respectively, and the second outputs connected to information inputs of the buffer units of the group from the first to the eighth, respectively, the outputs of all registers of the second group are connected to the input of the block correction direction, the output (i+1)-th (i=0,1,...,7) register of the second group are connected to the inputs ((i+3)mod 8+1)-th, ((i+4)mod 8+1)-th and (i+5)mod 8+1)th adders of the first group, the outputs of the adders of the first group from the first to the eighth connected with the first inputs of the adders of the second group from the first to the eighth, respectively, the outputs of which are connected to information inputs of the registers of the third group from the first to the eighth, respectively, the second outputs of the buffer units of the group from the first to the eighth connected with the second inputs adders of the second group from the first to the eighth respectively with the second information inputs of the switches of the group from the first to the eighth, respectively, the first output clock pulses through the third one-shot is outinen with synchronization input unit direction, the first generator output clock pulses is connected with the second inputs of the synchronization of all the buffer blocks with inputs synchronization of all registers of the first group and the first inputs of all elements And the output of the block direction is connected with the inputs of the installation of all triggers of the second group, the information input of the buffer block is the input of the receiving module, the first synchronization input buffer block is a synchronization input module, the ninth output of the first decoder connected to the second input of the first element And the second output buffer unit is the second output of the receiving module, the third outputs of all the buffer blocks are connected to the input of the first element OR the second one-shot is connected to the second input of the second element OR the output of which is connected to the reset input of trigger start, direct the output of which is connected to the generator input clock pulses, the second output of which is connected to the counting input of the first counter, the reset input of which is connected to the output of the fifth element OR to the second input of which is connected to the output of the first element And the second output clock pulses is connected to the counting inputs of all flip-flops of the second group, the third, fourth and fifth outputs of clock pulses connected to the first, second and third inputs of the fourth cell battery (included) is the respectively, and the outputs from the first to the eighth, the output of the fourth element OR is connected to the counting input of the second counter, the output of the third element OR is connected to the reset input of the second counter, the output of the second element And is connected to a second input of the third element OR the output of the second counter connected to the input of the second decoder, the first output of which is connected to the first control inputs of all of the switches of the group, the second output of the second decoder is connected to the second control inputs of all of the switches of the group, the third output of the second decoder is connected with the third control inputs of all of the switches of the group, and with the second input of the second element And the outputs of the registers of the third group from the first to the eighth connected with third information input switch group from the first to the eighth, respectively, the direct outputs of the triggers of the second group from the first to the eighth connected with the fourth control inputs of the switches of the group from the first to the eighth, respectively, and direct the ninth trigger the second group is connected to the synchronization input of the output register.

Figure 1 shows a functional diagram of the module for messaging, figure 2 shows the structural diagram of the switch on the basis of the proposed module; figure 3 schematically shows the process of forming the codes of congestion for one sector of directions; figen message structure; figure 5 shows the graph-scheme of algorithm processing the message; figure 6 schematically shows the path of the correction directions for the issue and formation of codes of queue lengths for one sector areas; 7-9 shows a functional diagram of the buffer block, the block select the direction and correction block directions, respectively; figure 10 shows the timing diagram of module operation in modes of delivery and reception of information.

The switch on the basis of the proposed module has the form 8-a regular lattice (matrix) with open boundaries (each module has a connection with its eight neighbors, and at modules in rows and extreme modules in the columns of the matrix do not have direct connection) (figure 2). The messaging is performed in parallel code through the transit modules. Each module has its own address, which is determined by its coordinates relative to other modules. The direction of the message at each step is determined dynamically in the sector possible directions oriented to the receiver. This takes into account the workload queues three neighbors and load queues virtual neighbors in the sector (figure 3). The message goes in the direction where less than the total load of the queues. The sector is selected from the 8 possible options, depending on the relative positions of source and receiver.

the address of each module is defined by a pair of coordinates AV, where a is the column number of the module in the matrix, and the row number of the module (A - coordinate of the module on the X-axis, and the coordinate of the module on the Y axis). The lower left corner of the matrix has coordinates 1.1 and upper right coordinates N.M (figure 2).

How to set message routing is determined by the following notation:

R - direction "right";

L - direction "left";

U - direction "up";

D - the direction of "down";

EN - "right-up";

RD - "right-down";

LU - "left-up";

LD - "left-down".

The direction the message is organized depending on the relative position of the receiver and source. Let X.Y is the address of the receiver and X1.Y1 address of the current module (in which the message resides). Then the direction of the message is displayed in the module X1.Y1 can be defined on the table.

To specify the route of transmission of messages between modules, taking into account its possible dynamic modification, the space switch (figure 2) is divided into sectors. A sector is a group of destinations in which you can transfer the message to the receiver. In each sector three directions: one primary and two secondary. Routing in the main direction is according to the table. The sector can be defined. The main direction of "right" (R), minor - right-down (RD) and "right-up" (EN). Then, if the message is before the further to the right, depending on the load of message queues, it is possible to modify the direction of RU and RD. You can also specify other sectors and areas of transmission:

RU.R.RD - sector trends EN, R (main direction), RD;

R.RD.D - sector directions R, RD (main direction), R;

RD.D.LD - sector directions in RD, D (main direction), LD;

D.LD.L - sector areas D, LD (main direction), L;

LD.L.LU - sector areas of LD, L (main direction), LU;

L.LU.U - sector directions L, LU (main direction), U;

LU.U.RU sector trends LU, U (main direction), EN;

U.RU.R sector of directions U, RU (main direction), R.

The modules receive information about the workload queues neighbors in the sector, as well as congestion of the queues of the virtual neighbors as follows. The code length of the queue is stored in a special register is a counter that is incremented by 1 with each message arrives and decrease by 1 every care messages. Send this code to your neighbors as you are sent regular messages in the form of parallel words to the heartbeat. In order not to introduce extra communication channels for the exchange of codes queue lengths, these codes are transmitted on the main channels (which are messages), but in multiplex mode. For example, in the first step of the message, and then codes the lengths of the queues. Code which must be given to all neighbors, each neighbor of the code length of the corresponding queue.

To transfer messages were not only taking into account the state of congestion of the queues three neighbors in the sector, but also virtual neighbors, the desired currency and codes of lengths of queues virtual neighbors. This can be done the same way as described above for the main communication channels in multiplexing mode. For example, in the first stage there is a message in the second time - codes of lengths neighbors, and in the third - codes of lengths virtual neighbors.

As the direction of the message is selected from three options (primary and two secondary), but it is necessary to consider load a larger number of queues, you must combine the codes of lengths of each neighbor with codes corresponding virtual neighbors, for example, by summing. Then each line will correspond to the total code of congestion, which can be arranged direction (figure 3).

Figure 3 through L1-L12the indicated length of message queues, virtual and immediate neighbors. Module 2.2 on the basis of these lengths 3 calculates the total code length of queues: for directions U (LU)to RU (LENand for the direction R (LR). Formulas for calculating these codes are as follows:

LU=L+L2L3+L10;

LEN=L4+L5+L6+L11;

LR=L7+L8+L9 +L12.

Similarly calculated total codes of lengths of the queues for other sectors.

Based on the calculated total code lengths of the queues provides dynamic modification of selected areas of message transfer in the sector. First select the main direction according to the table. Then this direction is adjusted in accordance with the ratio between the total code length of the queues. Path selection is affected by the state not only to the immediate neighbors, but also virtual neighbors. With this route you can pre-determine the most downloaded messaging fragments of the switch and to optimize the transmission of messages by means of their delivery "bypass". If we consider all traffic on the switch, it is possible to provide good load balancing queues and thereby reduce the requirements to their utmost length.

Algorithm message processing module includes the following steps:

1. Reading messages from the queue.

2. Formation code core issue of the notification.

3. Correction code direction the message is displayed.

4. The message to the desired output.

Reading messages from the queue comprises selecting one of the queues (only 9 of queues according to the number of inputs module). Code generation direction is according to the table depending on the ratio addresses the current module and receiver of the message. Correction code direction includes calculating the total code of the queue lengths (LU, LENetc) and changing codes of directions based on the results of the calculation (minimum total length). The message includes the transmission of information of part or all messages in the adjusted direction (the desired output). To ensure correct delivery of the message to the receiver, it is necessary to prohibit the correction of the direction of issuing, when the receiver has only one step of the transmission, i.e |X-X0|=1 and/|Y-Y0|=1. Otherwise, the message may "get stuck" and not reach the receiver.

Graph-scheme of algorithm processing the message shown in figure 5. The condition X=X1 and Y=Y1, the algorithm checks whether the message is delivered to the receiver or not. If it is false, then the message should be issued to the neighbor of the current module. Otherwise, the information part of the message is received by the transmission module in that they serve an operational device. The condition |X-X1|=1 or |Y-Y1|=1 indicates the need for correction of the direction of the message. If that is true, then the correction is not needed, because the message will be transferred to the module receiver. If it is false, then a correction direction by the total code length of the queue.

Module for messaging (figure 1) contains a group buffer blocks 1.1-1.8, buffer block 2, block 3 correction direction, block 4 select the direction, the generator 5 clock pulses, the first group of registers 6.1, 6.2, a second group of registers 7.1-7.8, a third group of registers 8.1-8.8, the output register 9, the first decoder 10, the second decoder 11, a multiplexer 12, a group of demultiplexes 13.1-13.8, the first counter 14, the second counter 15, the first group of adders 16.1-16.8, the second group of adders 17.1-17.8, a group of switches 18.1-18.8, the first trigger group 19.1-19.8, the second trigger group 20.1-20.9, trigger 21 start, the first 22 and second 23 and the third 24 adenovirally, the first group of elements OR 25.1-25.8, the second group of elements OR 26.1-26.8, between the first and fifth elements OR 27-31, the first 32 and second 33 elements, and the first information input unit 4 direction is input 34 address of the module, the output of block 3 correction direction is connected with the second information input unit 4 select the direction that the output of the register 6.1 is connected with the third information input unit 4 select the direction that the input 36 of the reset module is connected to the reset inputs of the buffer blocks 1.1-1.8 and 2, the output of the register 9, triggers 19.1-19.8 and 20.1-20.9, registers 6.1,6.2, 7.1-7.8 and 8.1-8.8, to the first inputs of the elements 28, 29 and 31, the outputs of the decoder 10 from the first to the ninth connected with control inputs of the buffer blocks 2 and 1.1-1.8, respectively, the first outputs of the buffer blocks 2 and 1.1-1.8 connected to information inputs of the multiplexer 12 from the first to the ninth is respectively, the output of the counter 14 is connected with the control input of the multiplexer 12 and to the input of the decoder 10, the output of multiplexer 12 is connected to information inputs of registers 6.1 and 6.2, the output of one-shot 22 is connected to the inlet of trigger 21 run, the outputs of registers 6.1 and 6.2 are connected with the first information input switches 18.1-18.8, the output of register 6.2 is connected to the information input of the output register 9, the output of the output register 9 is the first output of the reception 40.1 module, the outputs of switches 18.1-18.8 connected to the outputs 39.1-39.8 module respectively, the most significant bit inputs 35.1-35.8 module connected with the first inputs elements OR 25.1-25.8, 26.1-26.8 and inputs the synchronization registers 8.1-8.8, respectively, the low-order bits of the inputs 35.1-35.8 module connected with the second inputs of the elements OR 25.1-25.8 and the first inputs of the synchronization buffer blocks 1.1-1.8, respectively, the second bit of the input 35.1-35.8 module connected with the second inputs of the elements OR 26.1-26.8, respectively, the outputs of the elements OR 25.1-25.8 connected to the counting inputs of flip 19.1-19.8, respectively, the outputs of the elements OR 26.1-26.8 connected to the inputs of the synchronization registers 7.1-7.8, respectively, the direct outputs of the triggers 19.1-19.8 connected to control inputs of demultiplexes 13.1-13.8, respectively, the inputs 35.1-35.8 module connected to information inputs of demultiplexes 13.1-138, respectively, the first outputs of demultiplexes 13.1-13.8 connected to information inputs of registers 7.1-7.8, respectively, the second output demultiplexes 13.1-13.8 connected to information inputs of the buffer blocks 1.1-1.8, respectively, the outputs of registers 7.1-7.8 connected to the input of the correction unit 3 directions, the output of register 7.i+1 (i=0,1,...,7) are connected to the inputs 16.((i+3)mod 8)+1, 16.((i+4)mod 8)+1 and 16.((i+5)mod 8)+1 adders, the outputs of the adders 16.1-16.8 connected with the first inputs of adders 17.1-17.8, respectively, the outputs of the adders 17.1-17.8 connected to information inputs of registers 8.1-8.8, respectively, the second outputs of the buffer blocks 1.1-1.8 is connected with the second inputs of adders 17.1-17.8, respectively, and with the second information inputs of the switches 18.1-18.8, respectively, the first output of the generator 5 clock pulses through the one-shot 24 is connected to the synchronization input of the unit 4 select the direction that the first generator output 5 of clock pulses is connected with the second inputs synchronization buffer blocks 1.1-1.8 and 2, with the inputs of the synchronization registers 6.1, 6.2 and connected to the first inputs of the elements 32 and 33, the output of block 4-direction is connected to the inputs setup triggers 20.1-20.9, data input buffer unit 2 is input 37 of the receiving module, the first synchronization input buffer unit 2 is input 38 synchronization module, deviate the output of the decoder 10 is connected to the second input element And 32, the second output buffer unit 2 is the second output of the reception 40.2 module, the third outputs of the buffer blocks 2 and 1.1-1.8 is connected to the input element OR 27, the output element 27 is connected to the inputs of odnovorov 22 and 23, the output of one-shot 23 is connected with the second input of the OR element 28, the output element 28 is connected to the reset input of trigger 21 start, direct trigger 21 start is connected to the input of the generator 5 clock pulses, the second output of the generator 5 clock pulses connected to the counting input of the counter 14, the reset input of the counter 14 is connected to the output element OR 31, to the second input of which is connected to the output element 32, the second output of the generator 5 clock pulses is connected to the counting inputs of the triggers 20.1-20.9, third, fourth and fifth outputs of the generator 5 clock pulses connected to the first, second and third inputs of the element OR 30, respectively, and outputs 39.1-39.8 module, the output of the OR element 30 is connected to the counting input of the counter 15, the output of the OR element 29 is connected to the reset input of the counter 15, the output element 33 is connected with the second input element OR 29, the output of the counter 15 is connected to the input of the decoder 11, the first output the decoder 11 is connected to the first control inputs of the switches 18.1-18.8, the second output of the decoder 11 is connected to the second control inputs of the switches 18.1-18.8, the third output desire the ora 11 is connected with the third control inputs of the switches 18.1-18.8, the third output of the decoder 11 is connected with the second input element And 33, the outputs of registers 8.1-8.8 connected with the third information input switches 18.1-18.8, respectively, the direct outputs of the triggers 20.1-20.8 connected with the fourth control inputs of the switches 18.1-18.8, respectively, direct trigger 20.9 connected to the synchronization input of the output register 9.

Each buffer block 1.1-1.8 and 2 (7) corresponds to the prototype and contains a group of registers 41.1-41.n (where n is the maximum length of a message queue), the reversible counter 42 load, the first and second groups of keys 43.1-43.n and 44.1-44.n, a group of blocks of elements OR 45.1-45.n-1, the first and second groups of elements OR 46.1-46.n and 47.1-47.n, the group of items 48.1-48.n, first to fourth elements And 49-52.

Unit 4-direction (Fig) corresponds to the prototype and contains the node 53 memory constants, the first and second myCitadel 54 and 55, the first through fourth circuit 56-59 comparison, and the decoder performed on the first and second groups of elements And 60.1-and 60.9 61.1-61.8, the group of blocks of elements And 62.1-62.8, group of items OR 63.1-63.8, from first to third elements And 64-66, element OR element 67 and 68 delay.

Unit 3 correction direction (figure 9) corresponds to the prototype and contains a group schemes 69.1-69.16 comparison, the first and second groups of elements OR 70.1-70.16 and 71.1-71.8.

The process module comprises the several steps: 1) setting the initial state; 2) run the module; 3) processing message flows; 4) completion of work. In turn, the third stage consists of three phases. The first phase is the message in the selected direction. The second phase - synchronous transmission code length message queues all eight neighbors. The third phase is the issuance of a total code length of queues eight neighbors. At this stage, asynchronously with respect to the issuing messages and codes of lengths of the queues is receiving messages and codes of lengths of the queues from the neighbors. This process also includes three phases. The first is the reception of messages in the buffer blocks 1.1-1.8 and 2. The second account code lengths of the queues. And the third is receiving a total code length of the queue.

In the initial state, all the memory elements of the module registers 6.1, 6.2, 7.1-7.8 and 8.1-8.8, the output register 9, the counters 14 and 15, triggers, 19.1-19.8 and 20.1-20.9 and the trigger 21 start) are in the zero state; at all entrances 34, 35.1-35.8, 37 and 38 and the outputs 39.1-39.8 and 40.1, 40.2 module are zero signals. The conversion module in this state occurs by applying an external unit signal of sufficient duration to the input 36 of the discharge (figure 1).

The module continues to be in its original condition until such time as one of the buffer blocks 1.1-1.8 and 2 will not receive the message. In the buffer unit 2 a message is received from the operating device, which is served by this module, as in the rest of the buffer blocks 1.1-1.8 in from the LMI neighbors of the current module in the switch (figure 2). After receipt of messages in the buffer unit, it appears at the first output. While the second output is formed by a non-zero code length message queue, and the third is the unit signal of the presence of messages. Unit from the third output buffer unit 1.1-1.8 and 2 through the element OR 27 and the one-shot 22 acts on the trigger 21 start and sets it in one state. As a result, the generator 5 clock pulses starts to generate a pulse sequence τ1-τ5. The module starts processing messages (step 3).

Message processing, as noted above, is a multiphase process, in which separately includes delivery of information and its reception.

Code selection buffer blocks from the output of the counter 14 is fed to the control input of the multiplexer 12 and commutes message from the buffer unit 1.1-1.8 or 2 registers 6.1 and 6.2. Pulse τ1 from generator 5 clock pulses to the register 6.1 is written to the address part of the message, and in case 6.2 - information part (figure 4). At the same time as the momentum of τ1 shift queue of messages in the selected buffer unit. After recording the message in the registers 6.1 and 6.2, the analysis starts his address part and is determined by the direction code of its issuance under the table.

Code direction is formed in the block 4 direction under the rules of the receipt of the principal directions (see table) and its adjustment to the total code length of queues neighbors in the sector (6). The correction process is performed not just on queue lengths immediate neighbors, and the total code, taking into account the status of queues virtual neighbors in the respective sector areas (figure 3).

Code received from the output unit 4 selection of the direction is served on the triggers 20.1-20.9 and fixed them on the trailing edge of the pulse τ2 from generator 5 clock pulses. Further, this code bitwise "distributed" between the output switch and configures the desired switch on the message. For example, if the selected direction U, we will only be open switch 18.1 and the message from the registers 6.1 and 6.2 will U. If the current module is the receiver of the message, none of the switches 18.1-18.8't miss the message; it will go to the operating device via the output register 9. After a message has passed through the switch to the desired module output, the third output of the generator 5 clock pulse appears τ3. He goes to the same output, where the sent message, and synchronizes its reception in the adjacent module.

This same pulse τ3 through the OR element 29 is held at the input of the second counter 15, and switches its status to "01". As a result, the outputs of the second decoder 11 about azueta unitary code "0010", which goes to the switches 18.1-18.8 and configures them to issue codes of lengths of the queues of the buffer blocks 1.1-1.8. Current codes of lengths of the queues of the buffer blocks 1.1-1.8 immediately pass to the corresponding outputs of the module to the neighbors. Pulse τ4 generator 5 clock pulses, these codes will be accepted by all eight neighbors.

By the same impulse τ4 switch counter 15 in the next state "10". The outputs of the second decoder 11 is formed of a unitary code "0100". This code is applied to the output switches 18.1-18.8 and commutes through them into the module outputs total codes queue lengths neighbors from the registers 8.1-8.2. On the next pulse τ5 from generator 5 clock pulses, these codes are fixed adjacent modules. At the same time, this pulse switches the second counter 15 in the state of "11", the outputs of the second decoder 11 shows a code of "1000". This code locks all switches, but prepares the counter 15 is reset to the zero state, opening the item And 33. On the next pulse τ1 counter 15 is reset to its original state.

Take the information comes from the eight neighbors of inputs 35.1-35.8 module to the inputs of demultiplexes 13.1-13.8, respectively. As mentioned above, are received first message, then the codes of lengths of the queues, and then total codes (three phase).

With the communication passes through the demultiplexer 13.1-13.8 in the corresponding buffer block 1.1-1.8, where the fixed pulse τ*3coming from the generator of clock pulses neighbor who sent the message (the asterisk symbol pulse suggests that the momentum is transferred from the neighboring module). Write messages in the buffer unit is a standard algorithm, which is unchanged taken from the prototype. After recording the message, the message queue in the buffer block is incremented by 1, which immediately shows the code length message queue on the second output of the given buffer block. Impulse τ*3in addition to recording the message in the buffer unit solves another problem: he back-to-back sets the corresponding trigger 19.1-19.8 in one state. As a result, the input of the corresponding demultiplexer 13.1-13.8 switched from its first output and information from a neighbor now will not go into the buffer unit, and in the corresponding register 7.1-7.8.

Immediately after the disappearance of the pulse τ*3at the input of the corresponding demultiplexer from a neighbor fed ID length message queue. This code passes the information to the input of the corresponding register 7.1-7.8, where is fixed on the leading edge of the next pulse τ*4. After writing code in the appropriate register 7.1-7.8 starts the conversion code correction direction in block 3, the correction direction and later the some time in block 4 select the direction is issued a new code of corrections. At the same time is the summation of the code lengths of the queues in the adders of the first and second group of adders 16.1-16.8 and 17.1-17.8. The total code is derived from code from three neighbors in the sector, added to the code length of the queue of the current module and fed into the corresponding register of the third group of registers 8.1-8.8 for the subsequent issuance of a neighbor.

After that, the input module pulse appears τ*5. This impulse completes three phases of data reception module from one neighbor. Pulse simultaneously solves the following tasks. First, it records in registers 8.1-8.8 total codes queue lengths for the respective sectors of directions calculated by the adders neighbors. Secondly, it from a neighbor rewritten code total queue lengths calculated similarly to this neighbor. And third, this same pulse returns the corresponding trigger 19.1-19.8 in the original zero state, so that the next message from a neighbor will go back into the buffer block. To provide temporary approval of the above actions with the actions of neighboring modules, the first two of them are excited by leading edge pulse τ*3and the rear front of the pulse.

Similarly, the module receives data from seven other neighbors, code fixes the lengths of queues from them, recalculates its own codes, including the total. And "work" with different neighbors occurs asynchronously by impulses from these neighbors, the functioning of which are not mutually synchronized.

Since the correct operation of the module is closely linked with the correct temporal relation between various signals in the module and its neighbors, the necessary analysis. To do this, figure 10 depicts a simplified timing diagram of operation of the module in the described modes of delivery and reception of information.

From the analysis of the diagram and functional diagram in figure 1 follows the correct operation of the module in conjunction with other similar modules on the switch.

The module terminates when none of the buffer blocks 1.1-1.8 and 2 are no more messages. In this case, the third output buffer blocks 1.1-1.8 and 2 are formed zero signals. The trigger 21 start is reset to the zero state. The result is a shutdown of the generator 5 clock pulses and the module stops processing messages. For the module to have time to give the last message and update information about their queue lengths at the neighbors, the shutdown of the generator 5 clock pulses should occur only after the output pulse τ5. It's easy to do in the schema generator 5 clock pulses, using ring pulse counter.

The module will resume as soon as in one of the buffer blocks 1.1-1.8 or 2 again receives the message.

Thus, as follows from the description, inclusion of module blocks, enabling dynamic modification of routes messages depending on the load queues as close neighbors, and virtual neighbors, has greatly expanded the scope of application of the device due to the possibility of redirect messages on the best areas and reduce the overall load on the switch.

Table 1
The ratio X.Y and X1.Y1The main direction of the message
X>X1, Y>Y1EN
X>X1, Y=Y1R
X>X1, Y<Y1RD
X<X1, Y>Y1LU
X<X1, Y=Y1L
X<X1, Y<Y1LD
X=X1, Y>Y1U
X=X1, Y<Y1D
X=X1, Y=Y1welcome message

Module to exchange messages containing the group buffer blocks from the first to the eighth, the correction block direction, the block direction, the generator of clock pulses, the first gr the FPU registers from the first to the second, the output register, the first decoder, multiplexer, the first counter, a group of switches from the first to the eighth, trigger start, from the first to the third adenovirally, from first to third elements OR the first and second elements And the first information input unit of choice is the entry address of the module, the output of the correction block direction is connected with the second information input unit direction, the reset input module connected to the reset inputs of all the buffer blocks of the group, to the reset input of the output register to the reset inputs of all the registers of the first group, the outputs of the first decoder from the second to the ninth connected with control inputs of the buffer units of the group from the first to the eighth, respectively, the first outputs of which are connected to information inputs of the multiplexer, second, third and ninth, respectively, the output of the first counter is connected with the control input of the multiplexer and to the input of the first decoder, the output of the multiplexer is connected to information inputs of all the registers of the first group, the first one-shot is connected to the input setup trigger start, the outputs of all registers of the first group are connected with the first information inputs of each switch group, the output of the second register of the first group is connected with the information input of the output register, the output of cat is, which is the first output of the receiving module, the outputs of each switch group connected to the corresponding outputs of the module, the output of the first element OR connected to the inputs of the first and second odnovorov, characterized in that it also includes the buffer unit, the second and the third group of registers, the second decoder group demultiplexes the second counter, the first and second group of adders, first and second trigger group, the first and second groups of elements OR, fourth, and fifth elements OR, with the output of the first register of the first group is connected with the third information input unit direction, the reset input module connected to the reset input of the buffer block to the inputs reset all flip-flops of the first and second groups, all registers of the second and third groups, to the first inputs of the second, third, and fifth elements OR the first output of the first decoder is connected with the control input of the buffer unit, the first output buffer unit connected to the first information input of the multiplexer, the most significant bit inputs of the module from the first to the eighth connected with the first inputs of the elements OR the first and second groups from the first to the eighth, respectively, and inputs the synchronization registers of the third group from the first to the eighth, respectively, the low-order bits of the input module from the first to the eighth connected with the second inputs of the elements OR of the first group with the first is about the eighth, respectively, and the first inputs of the synchronization buffer block group from the first to the eighth, respectively, the second bit of the input module from the first to the eighth connected with the second inputs of the elements OR the second group from the first to the eighth, respectively, the outputs of the elements OR of the first group from the first to the eighth connected to the counting inputs of the triggers of the first group from the first to the eighth responsibly, the outputs of the elements OR the second group from the first to the eighth connected to the inputs of the timing registers of the second group from the first to the eighth, respectively, the direct outputs of the triggers of the first group from the first to the eighth connected with control inputs of demultiplexes group from the first to the eighth, respectively, the inputs of the module from the first to the eighth connected to information inputs of demultiplexes group from the first to the eighth, respectively, the first outputs of which are connected to information inputs of the registers of the second group from the first to the eighth, respectively, and the second outputs are excluded to the information inputs of the buffer units of the group from the first to the eighth, respectively, the outputs of all registers of the second group are connected to the input of the block correction direction, the output (i+1)-th (i=0,1,...,7) register of the second group are connected to the inputs ((i+3)mod 8+1)-th, ((i+4)mod 8+1)-th and ((i+5)mod 8+1)th adders of the first group, the outputs of the adders of the first group from the first to the eighth connected with the first inputs of the adders of the second group from the first to the eighth COO is responsible, the outputs of which are connected to information inputs of the registers of the third group from the first to the eighth, respectively, the second output buffer block group from the first to the eighth connected with the second inputs of the adders of the second group from the first to the eighth respectively with the second information inputs of the switches of the group from the first to the eighth, respectively, the first output clock pulses through the third one-shot is connected to the synchronization input of the block selecting direction, the first generator output clock pulses is connected with the second inputs of the synchronization of all the buffer blocks with inputs synchronization of all registers of the first group and the first inputs of all elements And the output of the block direction is connected I set all the triggers of the second group, the information input of the buffer block is the input of the receiving module, the first synchronization input buffer block is a synchronization input module, the ninth output of the first decoder connected to the second input of the first element And the second output buffer unit is the second output of the receiving module, the third outputs of all the buffer blocks are connected to the input of the first element OR the second one-shot is connected to the second input of the second element OR the output of which is connected to the reset input of trigger start, direct you the od which is connected to the generator input clock pulses, the second output of which is connected to the counting input of the first counter, the reset input of which is connected to the output of the fifth element OR to the second input of which is connected to the output of the first element And the second output clock pulses is connected to the counting inputs of all flip-flops of the second group, the third, fourth and fifth outputs of clock pulses connected to the first, second and third inputs of the fourth element, OR respectively to the outputs from the first to the eighth, the fourth element OR is connected to the counting input of the second counter, the output of the third element OR is connected to the reset input of the second counter, the output of the second element And connected with the second input of the third element OR the output of the second counter connected to the input of the second decoder, the first output of which is connected to the first control inputs of all of the switches of the group, the second output of the second decoder is connected to the second control inputs of all of the switches of the group, the third output of the second decoder is connected with the third control inputs of all of the switches of the group, and with the second input of the second element And the outputs of the registers of the third group from the first to the eighth connected with the third information input switch group from the first to the eighth, respectively, the direct outputs of the triggers of the second group is s from the first to the eighth connected with the fourth control the inputs of the switches of the group from the first to the eighth, respectively, and direct the ninth trigger the second group is connected to the synchronization input of the output register.



 

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