Module for transferring and broadcasting messages in matrix switchboard

FIELD: computers.

SUBSTANCE: device has three blocks for forming messages lines, block for analysis of messages line, multiplexer, decoder, broadcast control block, buffer register, launch trigger, synchronization block, AND elements block, denying element, blocks for organizing messages lines, direction selection block, OR element, AND elements.

EFFECT: higher efficiency.

3 cl, 12 dwg, 2 tbl

 

The invention relates to the field of computer engineering and can be used when building means switching multiprocessor computing and control systems, subscriber communication systems with decentralized management, systems of information gathering and information-measuring systems.

Known matrix switch module containing three blocks Queuing messages, register the module ID, the unit of analysis message queue, multiplexer, register, demultiplexer, trigger, synchronization unit, two elements of comparison, two decoder element And (as the USSR 1575167, G 06 F 7/00, 15/16; publ. 30.06.1990, BI No. 24).

The disadvantage of this module is the lack of funds to organize the broadcast messaging options, in which the same message is sent to all modules or a specific group of modules in the structure of the switch. Due to the lack of such tools in this module, the broadcast can be implemented only by repeatedly issuing the same message. This causes a sharp increase in the flow of messages within the switch, leading to a rise time of intermodule communications and thereby limits the scope of the module.

Closest to the proposed module to the technical essence is the module communication network, p is rednaznachenie to send messages, messaging and organization of broadcasting modes messaging, containing blocks of Queuing messages from the first to the third, the unit of analysis of message queues, multiplexer, decoder, synchronization unit, a register, a trigger address register, two elements of comparison, the control unit message switch, three block elements And two elements of the ban (RF patent 2178584, G 06 F 15/163, N 03 To 17/56; publ. 20.01.2002, BI No. 2).

The disadvantage of this module is the inability to broadcast on arbitrary rectangular configuration modules communication network (switch).

An object of the invention is to expand the field of use of the device based on its composition means for broadcasting messages to an arbitrary group of modules that form a rectangular configuration (rectangle broadcasting”).

The technical problem is solved in that the module for the transmission and broadcasting of messages in a matrix switch containing one to three blocks Queuing messages, the unit of analysis of message queues, multiplexer, decoder, control unit broadcast buffer register, trigger, synchronization unit, with the first through third blocks of elements And the element of the ban, and the information input module from the first to the third connected with information which include inputs blocks Queuing messages from first to third, respectively, the first outputs are connected to information inputs of the multiplexer with the first through third, respectively, the second outputs of blocks Queuing messages from the first to the third connected to the inputs of the unit of analysis of message queues from first to third, respectively, the first output of which is connected to the address input of the multiplexer and to the input of the decoder, the outputs from the first to the third of which is connected to the selection input blocks Queuing messages from first to third, respectively, the second output of the analysis block of the message queues connected to the inlet of trigger start, direct the output of which is connected to the input of the synchronization unit, the first output of which is connected to the inputs of the sync blocks Queuing messages from the first to the third, the second output of the synchronization unit is connected to the direct input element of the ban, the output of which is connected to the reset input of trigger start, the second output of the analysis block of the message queues is connected to the inverted input element of the ban, the output of the multiplexer is connected to the first information input of the buffer register, the first output of the synchronization unit connected to the first input synchronization buffer register, the first output buffer register connected to information inputs of the first, second and third blocks of elements And the second output BL is ka synchronization is connected to the information input components And the first to the third, outputs which are outputs from the first through third, respectively, entered the fourth and fifth blocks of the organization's message queue, the block direction, between the fourth and sixth blocks of elements And the element OR, from first to third elements, and the fourth information input module is connected to the information input of the fourth block queue messages, the fifth information input module is connected to the information input of the fifth unit of the organization of the message queue, the first outputs of the fourth and fifth blocks Queuing messages connected with the fourth and fifth information inputs of the multiplexer, respectively, the output of which is connected to the second to fifth information inputs buffer register, the second outputs of the fourth and fifth blocks Queuing messages connected with the fourth and fifth inputs of the unit of analysis of message queues, respectively, fourth and fifth outputs of the decoder are connected to the selection input of the fourth and fifth blocks Queuing of messages, respectively, the first output of the synchronization unit is connected to the synchronization inputs of the fourth and fifth blocks Queuing messages and second, third and fourth inputs of the synchronization buffer register, the third output of the synchronization unit connected to the first whoamiresponse and second elements, And the outputs are connected to first and second inputs decrement buffer register, respectively, the fourth output of the synchronization unit connected to the first input of the third element And whose output is connected to the reset input of the buffer register, the first output buffer register connected to information inputs of the fourth and fifth blocks of elements And the second output buffer register connected to the first input of the block selecting lines with information inputs of the first to fourth blocks of elements, And the third output buffer register connected to the second input of the block selecting lines with information inputs of the first to fourth blocks of elements, And the fourth and fifth outputs of the buffer register connected to the first and second inputs of the control unit broadcasts accordingly, the first output control unit broadcasting connected with the control input of the fifth block And the sixth and seventh outputs of the buffer register is connected to the third and fourth inputs of the block-direction, respectively, the second output control unit broadcasting connected with the first control inputs of the first to fourth blocks of elements, And from the third to the sixth outputs of the control unit broadcasts connected with the fifth to eighth input block-direction, respectively, the fourth output control unit broadcasting soy is inen with the first input element OR the fifth output control unit broadcasting is connected to a second input of the second element And the sixth output control unit broadcasting connected with the control input of the sixth block And a second input member OR the output of which is connected to the second input of the first element And the seventh output control unit broadcasting is connected to the second control inputs of blocks of elements, And first to fourth, the first output of the block direction is connected to the third input of the control unit broadcasts and a second input of the third element And the second, fourth and fifth outputs of the block direction is connected with the third control inputs of blocks of elements, And first to fourth respectively the output of the fourth block elements And is the fourth information output module, the output of the fifth block elements And is the fifth information output module, second and third outputs of the buffer register is connected to the fourth and fifth inputs of the control unit broadcasts accordingly, the fourth output buffer register connected to the information input of the sixth block elements And whose output is connected to information inputs of the second and fourth blocks of elements, And the fourth output buffer register connected to information inputs of the first and third blocks of elements, And the fifth output buffer register connected Informatsionnyi inputs of blocks of elements, And first to fourth.

The invention is illustrated by drawings, where figure 1 presents a functional diagram of the module for the transmission and broadcasting of messages in a matrix switch; figure 2 shows a functional block circuit Queuing messages; figure 3 shows a functional block circuit analysis of message queues; figure 4 shows a functional diagram of the control unit broadcasts; figure 5 shows a functional block circuit diagram of the direction; figure 6 are given the message formats for the various modes of operation of the module; figure 7 presents a graph-scheme of algorithm processing the message; Fig the structure of the switch, and also provides an illustration of the concept of the rectangle broadcasting; Fig.9 illustrates the principles of broadcasting organizations messages on various configuration modules.

General features of the invention are as follows.

The proposed module is included in the structure of the matrix switch, which consists of many identical modules that provide transmission and broadcasting of messages. The switch has the form of a matrix with open borders (each module has connections with their neighbours, and at modules in rows and columns of the matrix do not have direct connection with each other, Fig). The messaging is performed in parallel code through the transit modules.

Each module they the em your address, which is determined by its coordinates relative to other modules. The module address is set by a pair of coordinates AV, where a is the column number of the module in the matrix, and the row number of the module. The numbering goes from one. The lower left corner of the matrix has coordinates 1.1 (Fig).

The module implements pairwise (standard) mode of messaging, in which the message has a single receiver, and broadcast messages. When broadcasting a message has multiple modules, receivers, forming in the switch configuration is rectangular in shape (rectangle broadcast).

The dimensions of the rectangle broadcasting (number of elementary steps messages have values X and Y. the First width of the rectangle broadcast, and the second is his height. The values X=0 and Y=0 correspond to the pairwise exchange. If X≠0 or Y≠0, then the streaming is performed.

Mode pairwise exchange, or until the message is not received before the rectangle broadcast, the message is moved according to the standard routing algorithm: first, it goes along the line to the desired column, and then along the column to the desired line (this algorithm is used in the prototype and therefore not described in detail).

When broadcasting a message moves depending on the values of X and y When X=0 and Y≠0 message moves along a column (rectangle broadcasting has come oulevay width). When X≠0 and Y=0, the message goes only along a line (rectangle broadcasting zero height). If X≠0 and Y≠0, then the message is moved along the row, in each transit module it “duplicated” and at the same time in the column is transferred to broadcast its copy. The copy is set to X=0 (so that it travelled along a column). To determine as to whether the message border broadcasting, the values of X or Y with each new step decrease by 1. Once they both become zero, the broadcast message is terminated (the message is destroyed).

To determine as to whether the message of the rectangle broadcast (or receiver if it is only one), it includes the address of the angular module rectangle broadcasting (X0.Y0). In the case of a pairwise exchange of angular module is the receiver itself (rectangle broadcast conventionally has zero size”). To set the direction of the broadcast (to the right, then up, right, down, left, up or right, then down) are two single-bit sign (bits DH and DV). The structure and the possible message formats (F1-F5) are presented in Fig.6. In order to distinguish the mode of transmission of messages to the rectangle broadcasting and the broadcasting mode in the rectangle made the following assumption: after entering the rectangle coordinate value X0.Y0 established which are stated in null.

Illustration of the above principles is given in Fig.9, which shows four model variants broadcast. Black circles shows the modules, the relationships between them to simplify not shown (they can be easily restored on the basis of Fig). Under each option broadcast given two message format (Fig.6). The first (the one that is situated above) corresponds to the moment of delivery of the message source, and the second - moment processing of messages corner module rectangle broadcast. Fig.9 g illustrates how to implement a pairwise exchange.

Module for transmission and broadcasting of messages in a matrix switch (figure 1) contains blocks 1.1-1.5 Queuing messages, block 2 analysis of message queues, the multiplexer 3, a decoder 4, item 5 of the ban, the trigger 6 run, block 7 synchronization buffer register 8, block 9 select the direction that the block 10 control broadcasting, first 11.1, 11.2 second, third 11.3, fourth 11.4, fifth 12 and 13 sixth blocks of elements And the element OR 14, with the first to third elements And 15-17, the first through third information input 18.1-18.3 module connected to information inputs of blocks 1.1-1.3 Queuing of messages, respectively, the first outputs are connected to information inputs of the multiplexer 3 from first to third, respectively, the second outputs of blocks 1.1-1.3 organization of the message queue connected to the inputs of block 2 Ana the API message queues from first to third, respectively, the first output of which is connected to the address input of the multiplexer 3 and to the input of the decoder 4, the outputs from the first to the third of which is connected to the selection input blocks 1.1-1.3 Queuing of messages, respectively, the second output unit 2 analysis of message queues connected to the inlet of trigger 6 run, the direct output of which is connected to the input unit 7 synchronization, the first output of which is connected to the inputs of the sync blocks 1.1-1.3 organization of the message queue, the second output unit 7 synchronization is connected to the direct input unit 5 of the ban, the output of which is connected to the reset input of trigger 6 run, the second output unit 2 analysis of message queues connected to the inverted input unit 5 of the ban, the output of the multiplexer 3 is connected to the first information input buffer register 8, the first output unit 7 synchronization connected with the first synchronization input buffer register 8, the first output buffer register 8 is connected to information inputs of the components And 11.1-11.3, the second output unit 7 synchronize connected to information inputs of the components And 11.1-11.3, the outputs of which are from the first to the third information outputs 19.1-19.3 module respectively, the fourth information input 18.4 module is connected with the information input unit 1.4 organization of the message queue, the fifth information which was input 18.5 module is connected with the information input unit 1.5 Queuing messages the first outputs of blocks 1.4, 1.5 Queuing messages connected with the fourth and fifth information inputs of the multiplexer 3, respectively, the output of which is connected to the second to fifth information input buffer register 8, the second outputs of blocks 1.4, 1.5 Queuing messages connected with the fourth and fifth inputs of the unit 2 analysis of message queues, respectively, fourth and fifth outputs of the decoder 4 is connected to the selection input blocks 1.4, 1.5 Queuing of messages, respectively, the first output unit 7 synchronization connected with the inputs of the sync blocks, 1.4, 1.5 Queuing messages and second, third and fourth inputs of the synchronization buffer register 8 the third output unit 7 synchronization connected with the first inputs of the And elements 15, 16 whose outputs are connected to first and second inputs decrement buffer register 8, respectively, the fourth output unit 7 synchronization connected to the first input element And 17, the output of which is connected to the reset input buffer register 8, the first output buffer register 8 is connected to information inputs of the components And 11.4, 12, the second output buffer register 8 is connected to the first input unit 9-direction, with the information input block elements And 11.1-11.4, the third output buffer register 8 is connected to a second input of block 9 of choice is upravleniya, with the information inputs of the components And 11.1-11.4, fourth and fifth outputs of the buffer register 8 is connected with the first and second inputs of the block 10 control broadcasting, respectively, the first output unit 10 control broadcasting connected with the control input of the block elements And 12, the sixth and seventh outputs of buffer register 8 is connected to the third and fourth inputs of the block 9-direction, respectively, the second output unit 10 control broadcasting connected with the first control inputs of blocks of elements And 11.1-11.4, from the third to the sixth output unit 10 control broadcasting connected with the fifth to eighth input unit 9 direction accordingly, the fourth output unit 10 control broadcasting connected to the first input of the OR element 14, the fifth output unit 10 control broadcasting connected with the second input element And 16, the sixth output unit 10 control broadcasting connected with the control input of the block elements And 13 and the second input of the OR element 14, the output of which is connected with the second input element And 15, the seventh output unit 10 control broadcasting is connected to the second control inputs of blocks of elements And 11.1-11.4, the first output unit 9-direction is connected with the third input unit 10 control broadcasting and a second input element, And 17, second, third and fourth outputs of the block 9-direction is connected with the third control input and the components And 11.1-11.4, respectively, the output of block elements And 11.4 is the fourth information output 19.4 module, the output of block elements And 12 is the fifth information output 19.5 module, second and third outputs of the buffer register 8 is connected to the fourth and fifth inputs of the block 10 control broadcasting, respectively, the fourth output buffer register 8 is connected to the information input unit elements And 13, the output of which is connected to information inputs of the components And 11.2, 11.4, the fourth output buffer register 8 is connected to information inputs of the components And 11.1, 11.3, the fifth output buffer register 8 is connected to information inputs of the components And 11.1-11.4, the second output unit 7 synchronization is connected to the information codes of the components And 11.4 and 12.

Block queue messages 1.i, i=1,..., 5, (2) includes a group of elements And 20.1-20.k, where k is the maximum length of a message queue, a group of items OR 21.1-21.k, the And gate 22, registers 23.1-23.k, a group of items And 24.1-24.k, a group of blocks of elements OR 25.1-25.k-1, the demultiplexer 26, item 27, a delay element 28, the register 29 queue length, the element 30, and the input selection unit connected to the first input element And 22, the output of which connected with the first inputs of the elements OR 21.1-21.k, with the control input of the demultiplexer 26 and to the first input of the OR element 27, the synchronization input block connection is replaced with the second input element And 22, the information input unit is connected to the information input of the demultiplexer 26, with the first inputs of elements And 20.1-20.k and the second input of the OR element 27, the outputs of the elements And 20.1-20.k connected with the second inputs of the elements OR 21.1-21.k respectively, the outputs of the elements OR 21.1-21.k connected to inputs of the synchronization registers 23.1-23.k accordingly, the direct outputs of registers 23.2-23.k connected with the first inputs of blocks of elements OR 25.1-25.k-l, respectively, the inverted outputs of registers 23.1-23.k connected to inputs of elements And 24.1-24.k accordingly, the direct output of the register is the first 23.1 the output unit outputs the elements And 24.1-24.k connected with the first inputs of elements And 20.1-20.k respectively, to the address input of the demultiplexer 26, to the input element 30 and with the information input register 29 queue length, the first output of the demultiplexer 26 is connected to the information input of the register 23.k, the outputs from the k-th second demultiplexer 26 is connected with the second inputs of blocks of elements OR with the second inputs of blocks of elements OR 25.1-25.k-1, respectively, the outputs of blocks of elements OR 25.1-25.k-1 is connected to information inputs of registers 23.1-23.k-1, respectively the output of element 30 is connected with the second output unit, the output element 27 is connected to the input of the delay element 28, the output of which is connected to the synchronization input of the register 29 queue length, the output is vtorogo connected with the second output of the block.

Unit 2 analysis of message queues (figure 3) includes elements of comparison 31.1-R, element OR 32 site 33 permanent memory, and the input unit is connected to appropriate inputs of the elements 31.1-R comparison with the inputs of the OR element 32, the outputs of the elements 31.1-R comparison is connected to the input node 33 permanent memory whose output is the first output unit, the output of the OR element 32 is a second output of the block.

Unit 10 control broadcasting (figure 4) includes the first 34 and second 35, 38 third, fourth, 44, 39 fifth, sixth, 45, 37 seventh, eighth 36 elements OR, as well as the first 43, second 40, third 41, 42 fourth, fifth, 47, 46 sixth element, And the first (49.1) and second (49.2) unit connected to the inputs of the elements 34 and 35, respectively, the outputs of which are connected to first and second inputs of the element OR 38, respectively, the output of which is connected to the first input element And 43 whose output is connected to the first input of the OR element 44, the output of which is the first (48.1) output block, and the third (50) input of which is connected with the second input element And 43 and to the first input of the OR element 39, the output of which is connected to the first input element OR 45, the output of which is the second (48.2) output block, the fourth (51.1) and fifth (51.2) the inputs of which are connected to first and second inputs of the element OR 37, respectively, the output of which is connected to in Oromo input element OR 44, to the first inputs of the elements 40, 41, 42, 47 and to the second input of the OR element 39, the output of which is connected with the third (48.3) output unit that outputs elements 34 and 35 are connected with the second inputs of the And elements 41 and 42, respectively, the outputs of which are connected to the fourth (48.4) and fifth (48.5) outputs unit, respectively, and to first and second inputs of the element And 46, respectively, the output of which is the sixth (48.6) output unit that outputs elements 34 and 35 are connected to first and second inputs of the OR element 36 accordingly, the output of which is connected to the second input of the element 40, the output of which is connected with the second input element OR 45, the output of the OR element 36 is connected to the second input element And 47, the output of which is the seventh (48.7) output block.

Unit 9-direction (figure 5) includes 52.1 first and second 52.2 elements of comparison, the first 53.1 and second 53.2 the encoders, the register 54, the first element And 55, first to fourth elements OR 56.1-56.4, second, third and fourth elements And 57.1-57.4, first to fourth elements of the ban 58.1-58.4, and the first and the second input unit connected with the first inputs of the elements 52.1, 52.2 compare, respectively, the second inputs of which are connected to first and second outputs of the register 54, respectively, from the first to the third output element 52.1 comparison connected inputs encoder 53.1 from first to third, respectively, with whom, I can pay tithing on the third output element 52.2 comparison connected inputs of the encoder 53.1 between the fourth and sixth, respectively, the second outputs of the elements 52.1 and 52.2 of comparison is connected to the first and second inputs of the element And 55, respectively, which output is the first output unit, a fifth input connected to the first inputs of elements And 57.1-57.4 and inverted inputs of the elements of the prohibition 58.1-58.4, the outputs of which are connected with the first inputs of the elements OR 56.1-56.4, respectively, the outputs of which are second, third and fourth outputs of the block, respectively, the outputs of the encoder 53.1 first to fourth connected to the second inputs of elements And 57.1-57.4, respectively, the outputs of which are connected with the second inputs of the elements OR 56.1-56.4 accordingly, the sixth, seventh, eighth, third, and fourth inputs of the block are connected to the inputs of the encoder 53.2 between the first and fifth, respectively, the outputs from the first to the fourth which is connected to the direct inputs of the elements of the prohibition 58.1-58.4, respectively.

The purpose of the module elements for transmission and broadcasting of messages in a matrix switch (1) is as follows.

Blocks 1.1-1.5 Queuing messages (BOOS) are used for Queuing messages received from four similar modules (Fig) and own operating unit (OU) of the current module.

Unit 2 analysis of message queues (BAS) is used to analyze the load blocks Queuing messages 1.1-1.5 and organizatsiia survey depending on the length of the queue of incoming messages.

The multiplexer 3 is designed to transmit messages from the selected BOOS in the buffer register 8.

The decoder 4 selects the unit of the organization of the message queue from which to read the message.

Element 5 of the ban serves to lock the transmission signal to the reset input of the trigger 6 run.

The trigger 6 run serves to control the on / off unit 7 synchronization.

Unit 7 synchronization (BS) provides the synchronization of elements of the module.

Buffer register 8 (BR) is used for temporary storage and modification of the processed messages. BR is partitioned organization and includes five independent sections (sub-registers). The first is used to store information part I of the message. The second stores the values X0, Y0 (1, 6). The third and fourth store values X and Y, respectively. Finally, the fifth contains characteristic values of DH, DV. The second section has a reset input (R), applying a single signal which clears the digits of this section (for the other sections of this input is not available). The third and fourth sections have inputs decrement (-1), supply a negative signal front which reduces the value of these sections, i.e. actually are subtractive meters. This register 8 allows the most simple and efficient to implement the algo is ITM processing messages 7.

Blocks of elements And 11.1-11.4 serve to lock grant message to the outputs 19.1-19.4 module, respectively.

Block elements And 12 provides a block grant information part I message is output 19.5 module and then to the shelter.

Block elements And 13 serves to modify the address of the message, if necessary, generate a copy in the broadcasting mode.

Elements And 15-17 with the item OR 14 are used to form control signals buffer register 8.

Below will detail logic blocks 9 and 10.

Function block 9 direction (BVN) (5) - code generation direction message to control blocks of elements And 11.1-11.4. Direction code contains 5 bits: O, L, U, R, d Bit EM (end of transmission) defines achievement of the message receiver mode pairwise exchange or corner of the rectangle broadcasting in the broadcasting mode. Bits L, U, R, D encode the direction of the message: L - left line; U - up column; R - right on the same line; D - down the column. The direction of transmission of the message when pairwise exchange depends on the ratio of values X0.Y0 and X1.Y1. In broadcast mode the direction is determined by the signs of DH, DV, and the signals z4-z6coming from PDR 10.

The rule of formation of the bits L, U, R, D, EM when pairwise exchange is the standard matrix for commutatore the considered type. Table 1 contains a brief account.

The rule of formation of the bits L, U, R, D when broadcasting described in table 2 (behavior-bit EM in the broadcasting mode doesn't matter).

Table 1 (it is implemented by the encoder 53.1) is used only in mode pairwise exchange and when the message is delivered in a rectangle broadcast, and table 2 (it is implemented by the encoder 53.2), on the contrary, only works when broadcasting. Selecting tables, controls the signal z3coming from PDR 10.

Unit 10 control broadcasting (PDR) (figure 4) is a combinational circuit that, depending on the state of the address part of the message generates a 7-bit code control broadcasting z1z2z3z4z5z6z7. The digits of this code are generated according to the following expressions:

z1=(X0=X1∧Y0=Y1) ∧ (X.Y=0.0)v(X0.Y0≠0.0),

z2=(X.Y≠0.0∧X0.Y0=0.0) v (X0.Y0≠0.0∧X1.Y1≠X0.Y0),

z3=(X0.Y0≠0.0∧X1.Y1≠X0.Y0),

Z4=(X0.Y0=0.0)∧(X≠0),

Z5=(X0.Y0=0.0)∧Y≠0),

z6=(X0.Y0=0.0)∧(X.Y≠0.0),

z7=(X0.Y0=0.0∧X=0∧Y=0).

The category of z1takes a single value in the case when the current module should take the data portion of the first message for processing. This is possible with pairwise exchange, when the message has reached the receiver, as well as in the broadcasting mode, when the part I have to take the each module of the rectangle broadcast.

The category of z2becomes equal to the unit when the message is not received before the receiver mode pairwise exchange or to the corner of the rectangle broadcasting in the broadcasting mode, as well as in the broadcasting mode, when you want to continue broadcasting.

The category of Z3has a single value only if the message has reached the receiver or corner of the rectangle broadcast.

Discharges z4and z5be single if you want to continue broadcasting by row and column, respectively.

A single value of z6corresponds to the case when you want to create a copy of the current broadcast message.

The category of z7is equal to one if the current message completes broadcasting and should be destroyed.

To simplify the notation expressions for z1-z7next, use the following additional notation:

EM:X0=X1∧Y0=Y1

In:X0.Y0=0.0

I:X≠0

BY: Y≠0

After applying the formula for z1-z7take the form:

z4=B∧BX

z5=B∧BY

z6=B∧BX∧BY

Consider the work of the proposed module in more detail.

This process involves several steps: 1) setting the initial state; 2) the start of the module;3) processing message flows; 4) shutdown.

In the initial state, all the memory elements of the module are in the zero state, so all inputs and outputs are zero signals. The conversion module in this state occurs by applying an external signal (figure 1 circuit supply conventionally not shown).

The module continues to be in its original condition until such time as one of the BOOS 1.1-1.5 not received the message. In BOOS 1.1 message arrives with input from 18.1 OS, which is served by this module, as in the rest of BOOS from the neighbors of the current module in the switch (Fig). After receipt of the notification in block 1.i, it appears at the first output. At the second output of this block is non-zero code length message queue. Codes of queue lengths of all the BOOS are in BIOS 2 and form the signals at its outputs. The first entrance is code that BOOS, which contains a maximum of messages, and the second is a unit indicating the presence of messages in the module. This unit sets the trigger 6 in one state. As a result, the block 7 synchronization begins to produce four shifted relative to each other sequence of synchronization signals τ1-τ4. The module starts processing messages.

Message processing happens. Code selection BOOS from BIOS 2 is supplied to the address input of the multiplexer is 3 and commutes message from the selected BOOS in the buffer register 8. Pulse τ1 block : 7 it is recorded in the buffer register 8. At the same time as the momentum of τ1 shift queue of messages in the selected BOOS (this process is the same as in the prototype, and are therefore not described in detail). After recording the message in the buffer register 8 analysis begins his address part (6) according to the algorithm (7) and is determined by how it is transmitted to the module outputs. For this field messages arrive in the PDR 10 (figure 4) and BVN 9 (figure 5), where the formation of the signs of z1-z7and NO, R, U, L, D, respectively, previously described formulas and tables 1, 2. More different ways to process the message are discussed below.

The module terminates when none of the BOOS are no more messages. In this case, the second outputs of all five BOOS (figure 1) are zero codes. The second output BOS 2 appears zero signal indicates the lack of messages. This signal is applied to an inverse input element prohibition 5 and permit the passage through this element of impulse τ4 unit 7. Impulse τ4 is supplied to the reset input of the trigger 6 and resets it to zero state. The result is off the block 7 and the module stops processing messages. The module will resume as soon as one of the BOOS again receives the message.

Now consider the m ways of handling messages recorded in the buffer register 8.

If the message has the format F1 (6), then X=0 and Y=0 and is a pairwise exchange. The values X0 and Y0 come in BVN 9 and compares elements 52.1, 52.2 comparison (figure 5) with coordinates XI, Y1 of the current module (the latter is stored in the register 54). If they do not match, then a signal is generated EM=0, and the encoder 53.1 according to table 1 forms the direction code issuing messages from the signs of L, U, R, d If they match, then ET=1 (the message in the receiver), and the state of the encoder 53.1 plays no role. At the same time the values of X0, Y0 served in the PDR 10 (figure 4). PDR 10 generates a signal z3=1 (this signal means that the code direction L, U, R, D will generate the encoder 53.1) and the signals z1,z2. The value of z1=1 (it means that there will be issuing information of the message in the OS), if ET=1. While z2=0. If ET=0, on the contrary, z1=0, a z2=1 (will be issuing a message to a neighboring module, and not in the OS). The signal z3,=1 enters BVN 9 and permits the transmission code direction L, U, R, D with encoder 53.1 through the elements 57.1-57.4 and 56.1-56.4 to the corresponding outputs BVN 9.

Similarly, the PDR and BVN operating in the mode of message delivery to the rectangle broadcast (when there is only one difference in the format of the message (6):X≠0 or Y≠0).

After the formation of the signals z1-z7and NO, R, U, L, D at ET=1 is proishodit modification messages in the BR 8. The method of modification is determined by the original message format. The EM signal opens the item And 17 and provides poor impulse τ2 from block 7 to the reset input of BR 8. In the code X0.Y0 in the second section of the BD 8 is set to zero, which means the transition to the stage, broadcast or transfer completion message. The analysis of messages continues with the new values X0=0, Y0=0.

If the message has the format F2, F3, F4 or F5 (or format F1 when X0=0, Y0=0), the module implements the broadcasting mode (format F1 broadcasting is bogus and will be, because the message has already been delivered to only one receiver (illustration is given in Fig.9 g)). Message processing in format F2-F5 is almost the same, so we can consider only one of these formats. Let the message has the format F2 (6). The X and Y values that define the dimensions of the rectangle of the broadcasting act in the PDR 10 (figure 4). As a result, it outputs 48.1-48.7 signals are formed z1-z7. If X≠0 or Y≠0, z1=(The OS will take information part I of the message). This also z2=1 and z7=0, because the message you want to continue broadcasting in the neighboring unit. If X=0, Y=0, z7=1 (broadcast ends).

In the broadcasting mode z3=0, a z-z6defined values X.Y, as described in the earlier formulas. The signal z3 =0 enters the BVN 9 (figure 5), and prohibits output of information from the outputs of the encoder 53.1. At the same time it permits the delivery of information from an encoder 53.2. Encoder 53.2 depending on the signals z4-z6, as well as signs of DH, DV (they come in the third and fourth inputs BVN, respectively) in table 2 calculates the values of L, U, R, D. They determine how the message is displayed when broadcasting. At the same time signals z4-z6control the modification of the address part of the message being processed. If the signal z4=1 (is broadcast along the row of the matrix) or the signal z7=1 (is broadcast along the line-generation copy of the message for broadcast on the column), pulse τ3with unit 7 is input to decrement the third section BR 8 and subtracts from the value of X unit. Thus, a count of the remaining steps of broadcasting along the line. Similarly, if Z5=1, the impulse τ3 passes to the input of the decrement of the fourth section of BR 8 and provides the decrement field Y (has a step counter broadcasting along the column).

After modification of messages passed (after pulse τ3), is preparing messages for issuance to the desired output and issuing the pulse τ4 unit 7 synchronization. The preparation of this boils down to “bonding” (concatenation) messages from the fields of BR 8 (some of which can be modified) the way of the Assembly operations at the inputs of the components And 11.1-11.4. If you need to generate a copy of the message for output in the column, then the concatenation of the message and copy in the following order. For the message (it will go left or right) field X retains its value obtained from the BD 8 after modification. Copy (it will go up or down) field X is reset by the signal z6=1. Next, the resulting X appropriately connected with the other fields of the message and applied to the inputs of blocks 11.1-11.4.

The correctness of the concatenation of the values of field X is provided by the Association of tyres at the inputs of the components And 11.1-11.4. Up and down commuted the output of block elements And 13, and the left/right output of the third section of BR 8. The signals L, U, R, D outputs BVN 9 come into blocks of elements And 11.1-11.4 and allow passage formed messages (and possibly copies of) only to the necessary information outputs of the module.

After all the above steps, the fourth output unit 7 synchronization pulse appears T4. It passes through open blocks 11.1-11.4, 12 on the outputs of the module and synchronizes the message is received by neighbors (Fig) or in the OS. The message ends. If the signal z-y=1 will be closed blocks 11.1-11.4, the message will not go into the module outputs (thus implemented the destruction of the message upon completion of the broadcast).

Thus, as follows from the description, introduction to the module e is the elements and the resulting relationships can significantly extend the scope of its application, because it gives the opportunity pairwise messaging, and broadcast to an arbitrary group of switch modules having a rectangular configuration.

Table 1.
The ratio XO.YO and X1.Y1LURDET
HO>100100
HO<X110000
HO=X1 and Y0 > Y101000
HO-X1 and Y0 < Y100010
XO=XI and YO=Yl00001

Table 2.
z4z5z6DHDVLURD
100000010
01 0000100
001000110
100010010
010010001
001010011
100101000
010100100
001101100
100111000
0101100 01
001111001

1. Module for transmission and broadcasting of messages in a matrix switch containing one to three blocks Queuing messages, the unit of analysis of message queues, multiplexer, decoder, control unit broadcast buffer register, trigger, synchronization unit, with the first through third blocks of elements And the element of the ban, and the information input module from the first to the third connected to information inputs of the blocks Queuing messages from first to third, respectively, the first outputs are connected to information inputs of the multiplexer with the first through third, respectively, the second outputs of blocks Queuing messages from the first to the third connected to the inputs of the unit of analysis of message queues from first to third, respectively, the first output of which is connected to the address input of the multiplexer and to the input of the decoder, the outputs from the first to the third of which is connected to the selection input blocks Queuing messages from first to third, respectively, the second output of the analysis block of the message queues connected to the inlet of trigger start, direct the output of which is connected to the input of the unit is synchronized, the first output of which is connected to the inputs of the sync blocks Queuing messages from the first to the third, the second output of the synchronization unit is connected to the direct input element of the ban, the output of which is connected to the reset input of trigger start, the second output of the analysis block of the message queues is connected to the inverted input element of the ban, the output of the multiplexer is connected to the first information input of the buffer register, the first output of the synchronization unit connected to the first input synchronization buffer register, the first output buffer register connected to information inputs of the first, second and third blocks of elements And the second output of the synchronization unit connected to the information inputs of the components And the first to the third, the outputs of which are informational outputs of the module from first to third, respectively, characterized in that it additionally introduced the fourth and fifth blocks of the organization's message queue, the block direction, between the fourth and sixth blocks of elements And the element OR, from first to third elements, and the fourth information input module is connected to the information input of the fourth block queue messages, the fifth information input module is connected to the information input of the fifth unit of the organization of the message queue, the first you is ode of the fourth and fifth blocks Queuing messages connected with the fourth and fifth information the inputs of the multiplexer, respectively, the output of which is connected to the second to fifth information inputs buffer register, the second outputs of the fourth and fifth blocks Queuing messages connected with the fourth and fifth inputs of the unit of analysis of message queues, respectively, fourth and fifth outputs of the decoder are connected to the selection input of the fourth and fifth blocks Queuing of messages, respectively, the first output of the synchronization unit is connected to the synchronization inputs of the fourth and fifth blocks Queuing messages and second, third and fourth inputs of the synchronization buffer register, the third output of the synchronization unit is connected with the first inputs of the first and second elements And the outputs are connected to first and second inputs decrement buffer register, respectively, the fourth output of the synchronization unit connected to the first input of the third element And whose output is connected to the reset input of the buffer register, the first output buffer register connected to information inputs of the fourth and fifth blocks of elements And the second output buffer register connected to the first input of the block selecting lines with information inputs of the first to fourth blocks of elements, And the third output buffer register connected to the second input of the block selecting lines with information inputs from the first to the fourth the blocks of elements, And the fourth and fifth outputs of buffer register connected to the first and second inputs of the control unit broadcasts accordingly, the first output control unit broadcasting connected with the control input of the fifth block And the sixth and seventh outputs of the buffer register is connected to the third and fourth inputs of the block-direction, respectively, the second output control unit broadcasting connected with the first control inputs of the first to fourth blocks of elements, And from the third to the sixth outputs of the control unit broadcasts connected with the fifth to eighth input block-direction, respectively, the fourth output control unit broadcasting connected to the first input element OR the fifth output unit control broadcasting is connected to a second input of the second element And the sixth output control unit broadcasting connected with the control input of the sixth block And a second input member OR the output of which is connected to the second input of the first element And the seventh output control unit broadcasting is connected to the second control inputs of blocks of elements, And first to fourth, the first output of the block direction is connected to the third input of the control unit broadcasts and a second input of the third element And the second, fourth and fifth outputs of the block direction is connected with the third control inputs of the components the elements And first to fourth respectively, the output of the fourth block elements And is the fourth information output module, the output of the fifth block elements And is the fifth information output module, second and third outputs of the buffer register is connected to the fourth and fifth inputs of the control unit broadcasts accordingly, the fourth output buffer register connected to the information input of the sixth block elements And whose output is connected to information inputs of the second and fourth blocks of elements, And the fourth output buffer register connected to information inputs of the first and third blocks of elements, And the fifth output buffer register connected to information inputs of blocks of elements, And first to fourth.

2. The module according to claim 1, characterized in that the control unit includes broadcasting from first to eighth elements OR, from first to sixth elements And the first and second inputs of the block are connected to the inputs of the first and second elements OR, respectively, the outputs of which are connected to first and second inputs of the third element OR, respectively, the output of which is connected to the first input of the first element And the output of which is connected to the first input of the fourth element, OR whose output is the first output unit, a third input connected to the second input of the first element And to the first input of the fifth element And the And, the output of which is connected to the first input of the sixth element, OR whose output is the second output unit, the fourth and fifth inputs of which are connected to first and second inputs of the seventh element OR, respectively, the output of which is connected to the second input of the fourth element OR to the first inputs of elements And from the second to the fifth and to the second input of the fifth element OR the output of which is connected with the third output unit outputs the first and second elements OR connected with the second inputs of the third and fourth elements, And accordingly, the outputs are connected to the fourth and fifth outputs of the block respectively to the first and second the inputs of the sixth element, And accordingly, the output of which is the sixth output unit outputs the first and second elements OR connected to first and second inputs of the eighth element OR, respectively, the output of which is connected to the second input of the second element And whose output is connected to a second input of the sixth element OR the output of the eighth element OR is connected to the second input of the fifth element And whose output is the seventh release of the block.

3. The module according to claim 1, characterized in that the block direction includes first and second elements of comparison, the first and second encoders, the register, the first element And first to fourth elements OR from the second to the heel to the elements And, first to fourth elements of the ban, and the first and the second input unit connected with the first inputs of the first and second elements compare, respectively, the second inputs of which are connected to first and second output registers, respectively, from the first to the third outputs of the first comparison element are connected to inputs of the first encoder from first to third, respectively, from the first to the third outputs of the second comparison element are connected to inputs of the first encoder between the fourth and sixth, respectively, the second outputs of the first and second elements of comparison is connected to the first and second inputs of the first element, And accordingly, the output of which is the first output unit, the fifth input connected with the first input element And from the second to the fifth and inverted inputs of the elements of the ban from the first to the fourth, the outputs of which are connected with the first inputs of the elements OR first through fourth, respectively, the outputs of which are second, third and fourth outputs of the block, respectively, the outputs of the first encoder first to fourth connected to the second inputs of elements And the second through fifth, respectively, the outputs of which are connected with the second inputs of the elements OR first through fourth, respectively, sixth, seventh, eighth, third, and fourth inputs of the block are connected to the inputs of the second shirato the first and fifth, respectively, the outputs from the first to the fourth which is connected to the direct inputs of the elements of the ban first to fourth respectively.



 

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