Image acquisition solid-state device. RU patent 2521224.

FIELD: electricity.

SUBSTANCE: image acquisition solid-state device has the first substrate equipped with a photoelectric transducer at its primary surface, the first structure of wiring layout having the first contact area which contains a conducting material, the second substrate equipped with a part of peripheral circuit having its contact area at its primary surface and the second structure of wiring layout which contains a conducting material. Moreover the first contact area and the second contact area are connected so that the first substrate, the first structure of wiring layout, the second structure of wiring layout and the second substrate are place in the specified order. Besides, the conducting material of the first contact area and the conducting material of the second contact area are surrounded by diffusion-preventing films.

EFFECT: invention provides the image acquisition solid-state device capable to suppress generation of dark current or loss current.

14 cl, 11 dwg

The technical field to which the invention relates

[0001] the Present invention relates to contact parts are solid capture devices.

The level of technology

[0002] In solid-state capture devices CCD (charge coupled device) and amplifier type used for digital cameras, camcorders, etc, to obtain images with high resolution, pixel size should be reduced. However, as the pixel size is reduced more and more, the light-receiving area of PV inverter, catching the light, expressed in pixels decreases, and decrease the sensitivity.

[0003] In PTL 1 has been disclosed solid-state device is capturing images, and it is solid capture device CMOS-type, which represents a solid capture device image amplification type, to provide the light-receiving area of photovoltaic cell, first backing was provided photovoltaic cells and transistors migration, and the second backing was provided by other schemes, connected to each other. In PTL 1, for the implementation of this connection, for each pixel was used copper contact area.

A list of citations

Patent literature

[0004] PTL 1: Japanese lined patent application № 2006-191081

Summary of the invention

Technical problem

[0005] However, according to method of communication, opened in PTL 1, copper may in some cases to diffuse from the copper contact area first of the substrate and/or second substrate. When adulteration of this metal impurities in semiconductor, may, therefore, to begin generating dark current and/or leakage current, and consequently the resulting data images appear white spots, etc. In addition, when the adulteration of this metal impurities in semiconductor, forming a transistor, can occur generating leakage current and/or change the threshold value, and as a result, in some cases, it may fail the operation. In particular, in solid-state device for image capturing, with a few tens of thousands or more pixels, that is, tens of thousands or more contact plots with these contact plots can begin serious pollution. The phenomenon described above, can occur when used to contact plot conductive material, such as copper, with a high diffusion coefficient.

[0006] Consequently, the present invention provides a solid-state device is capturing images, the ability to suppress the generation of dark current and/or leakage.

Solution problems

[0007] Solid capture device image according to the present invention, contains first substrate, equipped with photoelectric Converter on its primary surface; first the structure of the layout, located on the primary surface first and substrate having first contact area that contains conductive material; the second substrate, provided that its primary surface, peripheral part of the scheme, including the control scheme and the scheme is read, the read signal on the basis of a charge of photovoltaic cell; and the second structure of the layout, located on the primary surface of the second substrate and having a second contact area that contains conductive material, and the first contact area and the second contact area must be connected to each other so that the first substrate, the first structure of the layout, the second the structure of the layout and the second substrate was located in the specified order, and conducting material of the first contact of the site and conducting material of the second contact area were surrounded by films prevent diffusion.

Useful effects of the invention

[0008] the Present invention can successfully provide a solid-state device is capturing images, the ability to suppress the generation of dark current and/or leakage.

Brief description of drawings

[0009] Fig. 1 is a schematic cross-section solid capture devices under Variant of realization of 1.

Fig. 2A presents a schematic view of the above solid capture devices under Variant of realization of 1.

Fig. 2B presents a schematic view of the above solid capture devices under Variant of realization of 1.

Fig. 3 is a schematic diagram of solid capture devices under Variant of realization of 1.

Fig. 4A represents a schematic cross-section, illustrating the stage of a method for the manufacture of solid-state capture devices under Variant of realization of 1.

Fig. 4B represents a schematic cross-section, illustrating the stage of a method for the manufacture of solid-state capture devices under Variant of realization of 1.

Fig. 5A represents a schematic cross-section, illustrating the stage of a method for the manufacture of solid-state capture devices under Variant of realization of 1.

Fig. 5B represents a schematic cross-section, illustrating the stage of a method for the manufacture of solid-state capture devices under Variant of realization of 1.

Fig. 6A represents a schematic cross-section, illustrating the stage of a method for the manufacture of solid-state capture devices under Variant of realization of 1.

Fig. 6B represents a schematic cross-section, illustrating the stage of a method for the manufacture of solid-state capture devices under Variant of realization of 1.

Fig. 7A represents a schematic cross-section of the contact area of solid-state capture devices under Variant of realization of 1.

Fig. 7B represents a schematic cross-section of the contact area of solid-state capture devices under Variant of realization of 1.

Fig. 7C represents a schematic cross-section of the contact area of solid-state capture devices under Variant of realization of 1.

Fig. 7D represents a schematic cross-section of the contact area of solid-state capture devices under Variant of realization of 1.

Fig. 8A represents a schematic cross-section of the contact area of solid-state capture devices under Variant of the incarnation 2.

Fig. 8B represents a schematic cross-section of the contact area of solid-state capture devices under Variant of the incarnation 2.

Fig. 8C represents a schematic cross-section of the contact area of solid-state capture devices under Variant of the incarnation 2.

Fig. 8D represents a schematic cross-section of the contact area of solid-state capture devices under Variant of the incarnation 2.

Fig. 8E represents a schematic cross-section of the contact area of solid-state capture devices under Variant of the incarnation 2.

Fig. 8F represents a schematic cross-section of the contact area of solid-state capture devices under Variant of the incarnation 2.

Fig. 8G represents a schematic cross-section of the contact area of solid-state capture devices under Variant of the incarnation 2.

Fig. 8H represents a schematic cross-section of the contact area of solid-state capture devices under Variant of the incarnation 2.

Fig. 9A represents a schematic cross-section, illustrating step of the method for making the contact area under Variant of the incarnation 2.

Fig. 9B represents a schematic cross-section, illustrating step of the method for making the contact area under Variant of the incarnation 2.

Fig. 9C represents a schematic cross-section, illustrating step of the method for making the contact area under Variant of the incarnation 2.

Fig. 10A represents a schematic cross-section of the contact area of solid-state capture devices under Variant of the incarnation 3.

Fig. 10B represents a schematic cross-section of the contact area of solid-state capture devices under Variant of the incarnation 3.

Fig. 10C represents a schematic cross-section of the contact area of solid-state capture devices under Variant of the incarnation 3.

Fig. 11A is a schematic view of the above, illustrating the contact area of solid-state capture devices under Variant of the incarnation 3.

Fig. 11B is a schematic view of the above, illustrating the contact area of solid-state capture devices under Variant of the incarnation 3.

Fig. 11C is a schematic view of the above, illustrating the contact area of solid-state capture devices under Variant of the incarnation 3.

Description of the versions of the incarnation

[0010] Solid capture device image according to the present invention is the first substrate, equipped with photovoltaic cells on its primary surface, the first structure of the layout, with the first contact sections, each containing a conducting material, the second substrate, equipped with a peripheral part of the scheme on its primary surface, and the second structure of the layout, with the latter contact sections, each containing a conducting material. In addition, the first contact area and the second contact the site connected to each other so that the first substrate, the first structure of the layout, the second the structure of the layout and the second substrate was located in the specified order. This solid-state device capture conducting material of the first contact of the site and conducting material of the second contact the plot is surrounded by films prevent diffusion relevant for conducting materials. Due to the structure described above, conductive materials surrounded by a relevant films prevent diffusion even after their compounds, and therefore can be provided solid-state device to capture images suitable to suppress the generation of the dark current and/or leakage.

[0011] Here and below, the present invention will be described in detail with reference to the drawings. In this variant of realization of the primary surface is the first of the substrate and the primary surface is the second underlay represent the surface of the substrate on which formed transistors. Opposite sides (opposite lateral surface), addressed to the appropriate primary surfaces (primary surfaces)are back (back) the first of the substrate and the back (rear) of the second substrate. In addition, the upward mean direction from the back surface of the primary surface of the substrate, and each of them, down, down, deep down, means a referral from primary surface to the rear surface of the substrate. In the following descriptions, if the first and second substrate connected to each other, back surface of the second substrate is on bottom, and rear surface of the first substrate is on the top surface.

[0012] In addition, wiring, having the structure of a single damascenone form by way of a single damascius, which insulating interlayer film form a groove for the transaction, and the groove is filled conductive material, such as metal barrier or copper, resulting in the transaction, immersed in an insulating interlayer film. The transaction, having the structure of a double damascenone form to post and through the interconnect were formed nerushenko so that they are immersed in an insulating interlayer film. That is, a transaction with the structure of dual damascenone form by way of double damascenone in which grooves used for the transaction and through interconnects, form in the interlayer insulation tape and conductive material such as metal barrier or copper, placed in a groove.

[0013] embodiment Variant 1 according to the present invention will be described with reference to Fig. 1-6B. First, the scheme solid capture devices under Variant of realization of 1 will be described with reference to Fig. 3. In this variant of the incarnation as an example, described a case in which information electric charge of an electron. Solid capture device image shown in Fig. 3, has a pixel section 301 that has a lot of photovoltaic converters, and phase peripheral circuits 302 with peripheral scheme, which includes a control circuit that controls read signal from pixel part 301, and the pattern of signal processing, signal processing reading.

[0014] In pixel section 301 are photovoltaic cells 303, transistors 304 transfer amplifier transistors 306 and transistors reset 307. Structure that includes at least one photoelectric Converter 303, defined as a pixel. One pixel according to this variant of the incarnation includes one photoelectric Converter 303, one transistor 304 transfer, one amplifier transistor 306 and one transistor reset 307. The source of the transistor 304 migration connect with photoelectric Converter 303, and stock area of the transistor 304 migration connected with the electrode shutter amplifier transistor 306. The node that is the same as the electrode shutter this amplifier transistor 306, is defined as the host 305. Transistor reset 307 connect with the host 305 and set its electrical capacity equal arbitrary electric potential (such as electrical potential reset). In such strcuture amplifier transistor 306 is part of the schema istokpoga repeater and sends a signal corresponding to the electric signal of the host 305, on the signal line RL. Site 305 in some cases can also be called floating diffusion region.

[0015] Section of the peripheral circuits 302 indicates the region, other than the pixel section 301. On the section of the peripheral circuits 302 is peripheral scheme, including a scheme of reading and control scheme. Peripheral schema contains a scheme of vertical scan, VSR, which is a control circuit that supplies the control signals to the electrodes gate transistors pixel sections 301. In addition, peripheral scheme contains the schema read RC, which supports the signals emitted from pixel section 301, and performs processing of signals, such as gain, summation and analog-to-digital conversion. In addition, peripheral schema contains a diagram of the horizontal scan HSR, which is the control scheme governing the calculation of time for the serial emission signals from the schema read RC.

[0016] In addition, solid-state device capture images under Variant of the incarnation 1 is formed by combining two elements together. Two elements are the first item 308, having first substrate 101, and the second element 309, with secondary substrate 121. Photovoltaic cells 303 and transistors 304 transfer pixel sections 301 set on the first substrate, and amplifier transistors 306 and transistors reset 307 pixel sections 301 and at least part of the peripheral schemes are set on the second substrate. The control signal from the peripheral circuits second item 309 on the electrode of the transistor 304 transfer of the first item 308 served through the contact section 310. The structure of the contact section 310 will be described later. The signal generated by photovoltaic inverter first item 303 308, read on stock field effect transistor 304 transfer, that is, on the site 305. Site 305 includes the structure formed in the first item 308, and the structure formed in the second item 309.

[0017] According to the structure described above, compared to a related case, when the pixel area is located on the same element (that is, one major substrate), the surface area of the PV inverter 303 can be increased and, therefore, may be increased sensitivity. In addition, compared to a related case, when the pixel area is located on the same element (that is, one major substrate), when the square surface of the PV inverter is not changed, the number of photovoltaic converters 303 might increase, and thus, may increase the number of pixels. In addition, compared to a related case, when the whole pixel plot and the whole plot peripheral schema is located on the same element (that is, one major substrate), it becomes easier to form the pixel section of the site and peripheral diagrams separately.

[0018] Concrete flat layout solid capture devices, as described above, will be described using schematic kinds of top-solid capture devices, shown in Fig. 2A and 2B. Fig. 2A shows the flat layout of the first item 308, that is, the first substrate 101, and Fig. 2B shows a flat layout of the second item 309, that is, the second substrate 121.

[0019] In Fig. 2A, in the first item 308 is the pixel section 301A, in which you installed photovoltaic cells, and blocks 312A pads, each fitted with a pad 313. At the pixel section 301A are photovoltaic cells 303, transistors 304 transfer, contact sections 310 and contact sections 311, shown in Fig. 3. In addition, the contact points 314A intended for connection with the second element 309, are located in the same location as the contact points of contact platforms 313, if you look along the direction perpendicular to the primary surface of the substrate 101. External output is connected with the contact area 313. Pads 313 located in a solid-state device image capture and include pads, each of which emits the signal (the signal of the image) on the basis of the charge generated in the photoelectric Converter, and pads, each of which is administered voltage, etc. supplied outside, to activation of the peripheral circuits.

[0020] Further, in Fig. 2B, pixel section 301B, plot peripheral circuits sections 302 and 312B pads are located in the second item 309. Part pixel scheme is at the pixel section 301B, and there are amplifier transistors 306, transistors reset 307 and contact sections 310 and 311, shown in Fig. 3. The peripheral part of the schema is located on the section of the peripheral circuits 302, and there are schemes of horizontal scan HSR, schemes of vertical scan VSR and schemes read RC. The contact points 314B, intended for the connection with the first element and schemes 315 protective diode, located on plots 312B pads.

[0021] In addition, the first item 308 and the second element 309, who have a flat layout shown, respectively, in Fig. 2A and Fig. 2B, connect with each other, with the formation of solid capture devices according to this variant of the incarnation. In particular, pixel section 301A and pixel section 301B are located so that they overlap. In addition, the contact points 314A and contact areas 314B connect with each other, and contact sections 310 and contact sections 311 first item connected, respectively, with contact sections 310 and contact sections 311 second element. In addition, Fig. 2A and 2B, the area for the first item 308, corresponding section of the peripheral circuits 302B second item 309, designated as the site of the peripheral circuits 302A. Part scanning schemes, that is, the peripheral part of the scheme, may be located on a plot of peripheral circuits 302A. The structure of this contact area will be described in more detail below.

[0023] First item 308 contains the first structure 149 wiring and first substrate 101. First substrate 101 is, for example, silicon semiconductor substrate and has a primary surface 102 and the back surface of 103. Transistors are installed on the primary surface 102 first substrate. The first structure 149 wiring has insulating interlayer film 104 and 105, layer 107 electrodes shutter containing electrodes shutter and wiring, layers 109 and 110 wiring containing the posting, and contact layer 108 containing contacts and/or through the interconnect. In addition, the first structure 149 wiring is the first film 111 prevent diffusion. In this variant of the incarnation, the number of interlayer insulation films, layers of wiring and contact layers included in the first structure 149 wiring can be specified arbitrarily. In addition, the layer 110 wiring the first structure 149 wiring contains contact sections 311 and 314A and integrated with the contact layer. Here and below, the contact area means the area in which conducting material of the first element and conducting material of the second element, which together form an electrical connection, connected to each other, and also means conductive material before making connections.

[0024] At the pixel section 301 of the first item 308 semiconductor region 112 n-type, forming photoelectric Converter, semiconductor region 114 n-type, functioning as a drain transistor transfer, and insulation structure 119 element are located in the first substrate 101. Transistor transfer formed from semiconductor of n-type, 112, semiconductor 114 n-type and electrode shutter 113 contained in the layer 107 electrode shutter. The charge stored in semiconductor field of n-type 112, passed semiconductor 114 n-type electrode shutter 113. The electric potential on the basis of the charge transferred semiconductor 114 n-type is passed to the second item 309 through contact contact layer 108, conductor layer 109 routing and layer 110 wiring containing contact layer. The guide contained in this layer 110 wiring, forms the contact section 311. In addition, photoelectric transducer can be a submerged photodiode, additionally with solid-state region of p-type or photo chopper and may be appropriately modified.

[0025] Planethouse layer 115, layer 116 color filter that contains many color filter, planethouse layer 117 and layer 118 microlenses, containing a number of microlenses are in the order specified at pixel section 301 on the back surface of 103 first substrate 101. In Fig. 1, although each of color filters and each of the microlenses provided for one PV inverter, that is, provided in each pixel, with one color filter and one lens can be provided for many pixels. Solid capture device image according to this variant of the incarnation is the so-called solid-state device capture type back-light, where the light falls on the part of the layer 118 microlenses and accepted by the photoelectric Converter.

[0026] On the site 312A pads first element provided 308 pads 313 and box 100, with which pads 313 connect with the external output. In addition, set the contact points 314A, each of which transmits the voltage entered pads 313 second item 309. The contact points 314A are contained in the layer 110 wiring in the form of the contact areas pixel sites. In addition, in the first item 308, as shown in Fig. 1, item 120 schema (optional) provided in the area corresponding section of the peripheral circuits 302B second item 309.

[0027] the Second element has 309 second structure 150 wiring and second substrate 121. The second substrate 121 is a substrate of silicon semiconductor and has a primary surface 122 and the back surface 123. Transistors are installed on the primary surface 102 second substrate. The second structure 150 wiring has insulating interlayer film 124 to 127, layer 128 electrode shutter containing electrodes shutter and wiring, layers, 130, 131 and 132 wiring containing the posting, and contact layer 129 containing contacts and/or through the interconnect. In addition, the second structure 150 wiring is the second film 133 prevent diffusion. In this variant of the incarnation, the number of interlayer insulation films, layers of wiring and contact layers included in the second structure 150 wiring can be specified arbitrarily. In addition, each layer 131 and 132 wiring of the second structure 150 wiring is connected to the contact layer. In addition, the layer 132 wiring contains contact sections 311 and 314B.

[0028] At the pixel section 301 of the second item 309, pocket 135 shaping amplifier transistor, which forms pixel scheme, semiconductor region 138 n-type, forming istokova/stock area amplifier transistor, and insulation structure 136 element are located in the second substrate 121. Amplifier transistor is in the pocket 135, and consists of electrode shutter 137 contained in the layer 128 electrode shutter, and semiconductor area 138 n-type, forming istokova/stock area. In this variant of realization of the first item 308 connected to the electrodes shutter 137 amplifier transistor through the contact points 311. The contact section 311 and electrode shutter 137 amplifier transistor connected to each other through wires and through the interconnection layer 132 wiring, cabling and end-to-end path layer 131 wiring, wiring layer 130 wiring and contact contact layer 129. In this case, the node 305, shown in Fig. 3, formed from semiconductor 114 n-type transactions and cross-cutting interconnect layers 109, 110, 132, 130 131 and wiring, contact layers 108 and 129 and electrode shutter 137, shown in Fig. 1. Other schemes (such as the transistor reset) pixel sections 301 not shown on the Figure.

[0029] Then, at least, part of the peripheral circuits, including management schemes, such as the scheme of horizontal scan and the scheme of the vertical scan, and schemes read placed on the site of the peripheral circuits 302B second item 309. Fig. 1 shows the transistor n-type and p-type transistor in the circuit (not mandatory)included in peripheral scheme. The n-type transistor, formed from the electrode shutter 140 contained in the layer 128 electrode shutter, and stokovij/stock areas 141 n-type, placed in the pocket of p-type 139. In addition, the p-type transistor with the electrode shutter 143 contained in the layer 128 electrode shutter, and semiconductor field of p-type 144, forming istokova/stock the field of p-type, put it in his pocket n-type 142.

[0030] In addition, the section 312B pads second item 309 diagram 315 protective diode, misleading signal to the contact area 313 first item 308, and contact plot 314B for the connection with the first element 308. Contact plot 314B contained in the layer 132 wiring as the contact region of pixel sites. Each of the two diodes 145 and 146 formed from the semiconductor area and two resistors 147 and 148, educated layer of 128 electrode shutter, contained in the scheme 315 protective diode under this option implementation. For this scheme 315 protective diode can be applied common scheme protective diode.

[0031] In addition, in solid capture device image according to this variant of the incarnation of the primary surface 102 first substrate 101 and primary surface 122 second substrate 121 are located opposite each other, with the first and second structures wiring-backed between them (external location). That is, the first substrate, the first structure of the layout, the second the structure of the layout and the second substrate are in order. In addition, you can also mention that the upper surface of the first structure 149 wiring and the top surface of the second structure 150 wiring connected to each other by plane X connections. That is, the first item 308 and the second element 309 connected to each other by plane X connections. The plane X connections formed the upper surface of the first structure 149 wiring and the top surface of the second structure 150 wiring. Contact plots located in the respective elements, connected to each other by plane X connections and provide conductivity between elements. In addition, contact Playground 313 solid capture devices intended for signal exchange with the environment, located above the primary surface 122 second item 309, and the first item 308 ensured box 100.

[0035] First provide a semiconductor substrate, and in the semiconductor substrate form elements. Provided semiconductor substrate 401 thickness D3, which has the primary surface 402 and the back surface 403. Semiconductor substrate 401 is a substrate of silicon semiconductor. In the semiconductor substrate 401 formed structure 119 insulation elements. Structure 119 insulation elements contains an insulating material, such as film silicon oxide, and has a structure, for example, LOCOS or STI. In addition, in the semiconductor substrate 401 form pocket (not shown), with any type of conductivity. Subsequently form the semiconductor area 112 and 114 n-type semiconductor field of p-type (not shown), which form photoelectric transducer and the transistor. In addition, form a layer 107 electrode shutter containing electrode shutter 113 transistor transfer. The layer of the electrode shutter form, for example, by sedimentation and formation of the figure of a layer of polysilicon, and it can contain the transaction, as well as the electrode shutter. Ways of formation of electrode shutter insulation elements and semiconductor area can be executed in compliance with the General semiconductor technology, and a detailed description can be omitted. The structure shown in Fig. 4A, get on the stages described above.

[0036] Then, on the primary surface 402 semiconductor substrate 401 form the structure of the layout. In particular, the first film produced in the form of insulating interlayer film 104'form so that it covers the layer 107 electrode shutter. After creating the pin holes in the film, formed as insulating interlayer film 104', form the films barrier of metal and tungsten, the excess part of their films are removed, forming thereby insulating interlayer film 104' and contact layer 108. In addition, insulating interlayer film 104' form a film barrier of metal and aluminum with the subsequent drawing of the picture, resulting in a layer of 109 layout. Then, the film is created in the form of insulating interlayer film 105, form so that it covers the layer 109 layout and form the film is created as the first film 111 prevent diffusion. Then, by way of double damascenone form a layer 110 wiring. Grooves for the wires and groove (holes) for through interconnections form in laminated films, of which create insulating interlayer film 105, and in films, of which create the first film 111 prevent diffusion. Film barrier of metal, which has the function of preventing the diffusion, and the film of copper is formed so that they filled grooves. Layer 110 wiring form by removing redundant barrier of metal and copper, and form an insulating interlayer film 105 and the first film 111 prevent diffusion. In this case, the first film 111 prevent diffusion has holes filled Postings. In addition, you can at the same time, removing the barrier of metal and copper, conduct planarization first film 111 prevent diffusion, by etching or chemical-mechanical polishing (HMP). The upper surface of the first planarizing film 111 prevent diffusion, planarizing this way, has sufficient flatness to then create a connection. The upper surface of the structure of the distribution form of the upper surface of the first film 111 prevent diffusion, and the upper layer of the surface of 110 conductors. Of insulating interlayer film 104' later form insulating interlayer film 104 shown in Fig. 1.

[0037] In this version of the incarnation, insulating interlayer film 104' and 105 each is a film of silicon oxide. However, it can also be formed insulating interlayer film 104' and 105, for example, film silicon nitride or organic resins. Contact 108 form, for example, from tungsten. Layer 110 wiring contains the contact section 314A and contact section 311A, and the layer 109 layout contains the contact area 313. Barrier metal has a feature to prevent diffusion of copper, which is a conductive material, and formed, for example, tantalum or tantalum nitride. The first film 111 prevent diffusion form of film, which has the function of preventing diffusion for conductive layer 110 wiring containing contact area, and it is a high-density inorganic insulating film. For example, film prevent diffusion is a film of silicon nitride or film silicon carbide. Methods for making these layers of routing, the contact layer and the interlayer insulation films can be carried out in accordance with the General semiconductor technology, and more details will be omitted. The structure shown in Fig. 4B, get on the stages described above. In Fig. 4B areas, presents a reference positions 104', 105, 106, 108, 109 and 110, will be further used for the formation of the first structure 149 distribution shown in Fig. 1. In addition, the contact section 311A further forms of contact section 311. On this Fig. 4B upper surface of the first structure 149 wiring, which then forms a plane X connections, shown in Fig. 1, formed the upper surface of the first film 111 prevent diffusion, and the upper surface of each transaction layer 110 wiring. The structure of the top surface will be further explained in detail.

[0038] Further, the production stages of the second item 309, shown in Fig. 1, will be described with reference to Fig. 5A and 5B. In Fig. 5A and 5B structure, which subsequently form the second item 309, shown in Fig. 1 displayed under the reference position 309'and sections, of which form the pixel section 301, section 302 of the peripheral circuits, section 312 of the pads and the scheme 315 protective diode is shown in Fig. 1, displayed, respectively, under the reference positions 301', 302', 312' 315'.

[0041] On this Fig. 5B upper surface of the second structure 150 wiring, which subsequently form the plane X connections, shown in Fig. 1, form-based upper surface of insulating interlayer film 127 and the upper surface of each transaction from the layer 132 wiring. Layer 132 wiring also is a conductive material used as a contact section. That is, the upper surface of the second structure 150 wiring contains the upper surface of conductive material. The structure of the top surface will be described in detail further.

[0042] First item 308' and the second element 309', as shown, respectively, in Fig. 4B and 5B, and are combined together so that the primary surface 402 and primary surface 405 respective semiconductor wafers were facing each other. That is, the upper surface structure, distribution of the first item 308' and the top surface structure, distribution of the second item 309' connect with each other. In this variant of the incarnation, as the contact points and 311A 311B and contact areas 314A and 314B form of guides, consisting mainly of copper, when they are connected to each other, you can perform welding of copper metal electrode. In addition, it is preferable that the connection was carried out in vacuum or in inert gas. In addition, before the connection is preferable to carry out the plasma radiation upper surface of each structure wiring. When this plasma exposure, compared with the case when the plasma radiation is not performed, the relationship between the interlayer insulation films, such as film silicon oxide and/or film of silicon nitride, can become stronger. In addition, instead of using plasma exposure, you can also use the activation method by chemical processing. With this method of connection, two patterns wiring United in one structure of the layout, which includes copper contact areas, surrounded by films prevent diffusion.

[0043] In addition, after connection of the first item 308' and the second item 309', the thickness of a semiconductor substrate 401 first item 308' from the back surface 403 decreases. Thickness reduction can be accomplished by GMP or etching. Therefore, from a semiconductor substrate 401 form a semiconductor substrate 407, and thickness varies from D3 to D1 (D1<D3) (Fig. 6A). As described above, since the thickness of the semiconductor substrate 401 decreases, with the formation of a semiconductor substrate 407, subsequently incident light can effectively get in the photoelectric Converter. In addition, at this stage, the thickness D1 semiconductor substrate 407 becomes less than the thickness D4 semiconductor substrate 404.

[0044] Then, planethouse layer 409, formed from the resin, the layer colour filter 410, planethouse layer 411, formed from the resin, and the layer of microlenses 412 form in the order specified on the back surface 408 semiconductor substrate 407. Methods for making these layers - planethouse layer, the layer colour filter and a layer of microlenses can be performed in compliance with the General semiconductor technology, and details will be omitted. In this case, the layer of microlenses can be formed for the area 312', which should be built in the area pads. The structure shown in Fig. 6B, get on the stages described above.

[0045] In addition, form a box 100, designed for pads 313. At this stage, the layer of microlenses 412, using technology photolithography form photoresist mask with any Windows. In addition, using the technology of dry etching, a layer of microlenses 412, planethouse layer 411, layer 410 colour filter, planethouse layer 409, semiconductor substrate 407 and insulating interlayer film 104' partially removed, with education, thus, box 100, designed to pads 313.

[0046] Thus form a layer of microlenses 118, planethouse layers and 115 117, the layer colour filter 116, first substrate 101 and insulating interlayer film 104. As a result, it turns out the structure shown in Fig. 1. Semiconductor substrate 404, the primary surface 405, the back surface of the 406, and the thickness D4 shown in Fig. 6B, with the second substrate 121, primary surface 122, back surface 123 and thickness D2, shown in Fig. 1. Although the thickness D4, in this case, does not deviate from the thickness D2, the thickness of a semiconductor substrate 404 may be reduced so that the thickness D2 was less than the thickness of D4. Although the number of stages at reducing the thickness increases, solid capture device image can be constructed with the miniature size.

[0047] Here and further on, more details in the contact section will be described with reference to Fig. 7A-7D. Each of Fig. 7A-7D represents increased a schematic cross-section of the contact section 311, shown in Fig. 1. In Fig. 7A-7D elements, which is the same as that shown in Fig. 1-6B, are denoted by the same reference positions as described above, and their details will be omitted.

[0048] first, Fig. 7A shows the status before connecting it to the first element and the second element of each other, and Fig. 7B shows a condition in which the two elements, connected to each other (Fig. 6A). The first item 308' has a layer 109 routing, layer 110 wiring, and the first film 111 prevent diffusion. Layer 109 layout contains aluminum 109a and barrier metal 109b, and the layer 110 wiring contains copper 110a and barrier metal 110b. In addition, the second element 309' has a layer 131 routing, layer 132 wiring and the second film 133 prevent diffusion. Layer 131 distribution contains copper 131a and barrier metal 131b, and the layer 132 wiring contains copper 132a and barrier metal 132b. That is, the contact section contains copper, with a higher diffusion coefficient than that of aluminium, used as a conductive material. In this case, conducting material is not limited with copper and may be selected from alloys, consisting primarily of copper, other metals, such as Au, and their alloys. In addition, the barrier metal for copper functions as a film prevent diffusion, with the ability to prevent the diffusion of copper. As such barrier of metal we can mention, for example, metals such as tantalum, manganese, niobium and chrome and their alloys, as well as film tantalum nitride also has a barrier function. In addition, as the first film prevent diffusion and the second film prevent diffusion we can mention, for example, film silicon nitride, film silicon carbide, film silicon carbonitride or film oxinitride silicon. In addition, copper 110a surrounded by barrier metal 110b, except for the section that is open in the plane X1. In addition, copper 132a surrounded by barrier metal 132b, except for the section that is open in the plane X2. In this variant of realization of the plane X1 represents the upper surface of the first structure 149 wiring, and the plane X2 represents the upper surface of the second structure 150 wiring.

[0049] As shown in Fig. 7B, plane X1 and the plane of the form X2 plane X connections, and the first item 308' and the second element 309' connected to each other. Copper 110a and copper 132a connected to each other. In this case, copper 110a and copper 132a surrounded, accordingly, the barrier metal 110b and barrier metal 132b, each of which represents a film prevent diffusion, which has the function of preventing the diffusion of copper. According to the structure, as described above, because conductive material surrounded by a film prevent diffusion on the contact area can be provided solid-state device to capture images suitable to suppress the generation of the dark current and/or leakage.

[0050] Fig. 7C represents a schematic cross-section that shows the case in which the structure shown in Fig. 7A, the position of the layer 110 wiring and layer 132 wiring, which form the contact area, the displaced. In the case shown in Fig. 7C, as provided by the first film 111 prevent diffusion and the second film 133 prevent diffusion conductive material can also be surrounded by films prevent diffusion on the contact area. In particular, as shown in Fig. 7D, copper 110a and copper 132a together surrounded by barrier metal 110b and barrier metal 132b, each of which represents a film prevent diffusion, and the first film 111 111 prevent diffusion and the second film 133 prevent diffusion. At presence of the patterns described above, even during shifted positions, for example, when changing the mode of the process, conductive materials will be surrounded by films prevent diffusion on the contact area; therefore, may be provided solid-state device to capture images suitable to suppress the generation of the dark current and/or leakage.

[0051] the Present invention is not limited to steps for a method of manufacturing according to this variant of the incarnation, and the order of these steps can also be changed. In addition, you can properly determine the procedure of manufacturing the first item 308 and the second item 309. The SOI substrate can also be printed on each of semiconductor wafers 401 and 404. In addition, it is also possible that the first item 308 and the second element 309 were obtained separately as substrates for solid capture devices, and then were joined together.

[0052] Next Version of the incarnation 2 of the present invention will be described with reference to Fig. 8A-9C. In this variant of the incarnation is described several modifications of the structure of the contact area. Fig. 8A-8H each represents a schematic cross-section, focusing on the contact area, corresponding to the areas shown in Fig. 7A-7D. In Fig. 8A-8H components, similar to those shown in Fig. 1-7D, are denoted by the same reference positions as described above, and their details will be omitted.

[0053] First is described the modification of the contact area, is shown in Fig. 8A and 8B. Fig. 8A represents a schematic cross-section that corresponds to the section, shown in Fig. 7A, and Fig. 8B represents a schematic cross-section corresponds to the section shown in Fig. 7B. In Fig. 8A differences from Fig. 7A are that layer 110 wiring has a smaller square surface area than the area of the surface layer 132 wiring, and that the second element 309' has no second film 133 prevent diffusion. Although the structure shown in Fig. 8A, represents only a partial section, the area of the surface layer 110 wiring in the plane X1 will be smaller than the area of the surface layer 132 wiring on the plane X2. In the structure described above, as shown in Fig. 8B, illustrating the condition after connection, copper 110a and copper 132a also surrounded by barrier metals 110b and 132b, each of which represents a film prevent diffusion, and the first film 111 prevent diffusion.

[0054] Further, is described the modification of the contact area, is shown in Fig. 8C and 8D. Fig. 8C represents a schematic cross-section that corresponds to the section, shown in Fig. 8A, and Fig. 8D represents a schematic cross-section that corresponds to the section, shown in Fig. 8B. In Fig. 8C contrast Fig. 8A is that the layer 110 wiring is concave section 801 in the plane X1. In particular, the first film 111 prevent diffusion is located on top of the insulating interlayer film 105 and layer 110 wiring and has a hole, the corresponding layer 110 wiring. In the structure described above, as shown in Fig. 8D, illustrating the condition after connection, copper 110a and copper 132a also surrounded by barrier metals 110b and 132b, each of which represents a film prevent diffusion, and the first film 111 prevent diffusion. In this modification, although concave section 801 is the step that corresponds to the thickness of the first film 111 prevent the diffusion step can be increased, for example, by the partial removal of copper 110a. In addition, even if the layer 110 wiring is concave section 801, because thermal expansion coefficient conductive material, such as copper, is greater than thermal expansion coefficient of dielectric material, forming a film prevent diffusion, and insulating interlayer film plane X connections can have a flat surface, as shown in Fig. 8D.

[0055] Further, is described the modification of the contact area, is shown in Fig. 8E and 8F. Fig. 8E represents a schematic cross-section that corresponds to the section, shown in Fig. 8C, and Fig. 8F represents a schematic cross-section that corresponds to the section, shown in Fig. 8D. In Fig. 8E contrast Fig. 8C is that the layer 110 wiring has a bump 802 in the plane X1. In particular, copper 110a has a bump, the speaker on the thickness D from the plane X1, formed the first film 111 prevent diffusion, etc. In the structure described above, as shown in Fig. 8F, illustrating the state after the communication, copper 110a and copper 132a also surrounded by barrier metals 110b and 132b, each of which represents a film prevent diffusion, and the first film 111 prevent diffusion. In the case described above, despite the existence of a smooth shaped, convex section 802 can have a rectangular shape. In addition, because the communication is applied pressure, even if the layer 110 wiring is convex section 802, plane X connection after the connection can have a flat surface, as shown in Fig. 8F.

[0057] As described above, also in the structures shown in Fig. 8A - 8H, copper can be surrounded by film prevent diffusion on the contact area. Consequently, it can be ensured solid-state device to capture images suitable to suppress the generation of the dark current and/or leakage.

[0058] hereinafter, the way of formation of a contact area with a bump, which is shown on each of Fig. 8E and 8G, will be described, with particular attention to the contact section 311B shown in Fig. 8G. First formed insulating interlayer film 126, layer 131 wiring and insulating interlayer film 127. Subsequently, the layer 132 wiring form in the interlayer insulation tape 127 way of double damascenone. In this case, when you remove the excess copper films and barrier metal, copper 132a, having a bump (speaker section), can be formed by adjusting the speed polishing, as well as the number of suspensions, in the case of using the method he, or by adjusting the amount of etching gas, etc., in the case of etching (Fig. 9A). Then, form the film 133', which covers a bump and which form the second film prevent diffusion (Fig. 9B), and then partially remove way etching or way he, thereby form the second film 133 prevent diffusion and convex section 803 (Fig. 9C).

[0059] In addition, Fig. 9A-9C each of the films - insulating interlayer film 126 and insulating interlayer film 127 form from a variety of insulating films, and form the film prevent diffusion 701, covering the top surface layer 131 wiring. As described above, you can properly determine the structure of the insulating interlayer film.

[0060] Above, this version of the incarnation, described the modification of the structure of the contact area. Modifications described above can appropriately be used in combination with each other, and can accordingly be applied at least for one of the first element and the second element.

[0061] Next Version of the incarnation 3 of the present invention will be described with reference to Fig. 10A-11C. In this variant of the incarnation is described several modifications of the structure of the contact area. Fig. 10A-10C are sketchy cuts contact areas described with reference to Fig. 8A-8H. In Fig. 10A-10C elements, similar elements, is shown in Fig. 1-7D, are denoted by the same reference positions, and that the constituent elements described above, and their details will be omitted.

[0062] Fig. 10A and 10B match each other, and each of them represents a schematic cross-section, which has a lot of contact plots are shown in Fig. 8B or 8D. Fig. 10C shows the modification of the structure shown in Fig. 10B.

[0063] First, as shown in Fig. 10A, form the first film 111 prevent diffusion, common to contact sections 311. As shown in Fig. 10B, the first film 111P prevent diffusion form through formation of a figure to around the periphery of the corresponding contact section and contact between sections 311 remove the first film 111 prevent diffusion. In addition, in comparison with the structure shown in Fig. 10B, Fig. 10C is additionally provided with a second film 133P avoid diffusion, and the second film 133P prevent diffusion form through the formation of the drawing so that she was surrounded by the periphery of the corresponding contact of the plot, as in the case of the first film 111P prevent diffusion.

[0064] In this case, because the first film prevent diffusion form of film of silicon nitride, and insulating interlayer film form of silicon oxide, the first film prevent diffusion has a higher dielectric constant than the insulating interlayer film. When the film with a high dielectric constant, as described above, along the periphery of the guide, its parasitic capacitance increases. Therefore, in comparison with the structure shown in Fig. 10A, parasitic capacitance between the conductors can be reduced with the structure shown in Fig. 10B. In addition, parasitic capacitance can be reduced also in the case when provided with the second film 133P prevent diffusion, as shown in Fig. 10C. Film prevent diffusion 701 also possible to create the drawing, as shown in Fig. 10B and 10C.

[0065] Each of Fig. 11A-11C is a schematic view from the top outer edge of each structure, to illustrate the relative position of the layer 110 wiring, layer 132 wiring, the first film prevent diffusion, and the second film prevent diffusion on the contact section 311. In other words, these images show the location of each structure in the plane X connections. In Fig. 11A-11C elements, similar elements, is shown in Fig. 1-10C, are denoted by the same reference positions, and that the constituent elements described above, and their details will be omitted.

[0066] Fig. 11A is a schematic view of the above, corresponding to Fig. 10B. Line XB-XB, shown in Fig. 11A, corresponds to cut conducted along the plane of the X connection Fig. 10B. As shown in Fig. 11A, the first film 111P prevent diffusion has the largest surface area and cover layer 132 wiring. That is, the surface on which the copper layer 132 wiring naked, corresponds to the first film 111P prevent diffusion layer and 110 wiring. When the ratio between the images, as described above, copper can easily cover film prevent diffusion.

[0067] Fig. 11B and Fig. 11C are schematic views from the top, corresponding to Fig. 10C. Line XC-XC shown in Fig. 11B and Fig. 11C, corresponds to the cut, taken along the plane X connections, shown in Fig. 10C. In Fig. 11B the size of the figures increased in the following order: the layer 110 wiring, layer 132 wiring, the first film 111P prevent diffusion and the second film 133P prevent diffusion. When the ratio between the images, as described above, the surface on which the copper layer 132 wiring naked, corresponds to the first film 111P prevent diffusion layer and 110 wiring, and copper can easily cover film prevent diffusion.

[0068] Fig. 11C has drawings layer 110 wiring and layer 132 wiring, other than the figures shown in Fig. 11B. Drawings layer 110 wiring and layer 132 wiring have long side oriented, respectively, in the first direction, and in the second direction, which are distinct from each other. If there are drawings, described above, acceptable the offset range of positions at connection can be upgraded.

[0069] As described in this option, the incarnation, the first film prevent diffusion, the second film prevent diffusion and contact the site can have each their own arbitrary form, and the form, you can choose a suitable way.

[0070] hereafter, as one example of the application of solid-state capture devices according to each of the above variants of the incarnation, the system of image acquisition, including solid-state device is capturing images, will be described in the form of an example. In the system of reception of images, in addition to devices such as camera, the source used for receiving images, also used for devices (such as a personal computer and personal digital assistant)with auxiliary function receive images. For example, the camera includes a solid-state device capture of the present invention, and the site of treatment, which processes the signal emitted from solid capture devices. This plot of treatment may include, for example, analog-digital Converter and processor machining derived from the digital data.

[0071] Thus, as described, according to a solid state device capture of the present invention may be provided, solid-state device to capture images suitable to suppress the generation of the dark current and/or leakage.

[0072] In addition, this invention is not limited by the structures presented in the description of the invention, and it can also be used in case, when the pixel schema changes, and only photovoltaic installed for the first item. In addition, the present invention can appropriately be applied, for example, for a structure in which the structure of conductive type and/or type of scheme replaced the structure of reversing type, where additionally provided with a layer of conductors and insulating interlayer film, and in the case when the structure with a single damascelli replaced by a structure with double damascelli. In addition, patterns according to the Options of the incarnation can also be used in combination with each other.

[0073] in Addition, the present invention is not limited to solid state device is capturing images, and it can also be used for conventional semiconductor devices such as DRAM.

[0074] whereas the present invention has been described with reference to indicative options for implementation, it should be understood that the invention is not limited open approximate variant of the incarnation. The volume of the formula of the invention is consistent with the broad interpretation of covering all such modifications and equivalent structures and functions.

[0075] This application claims the priority of Japanese patent application № 2010-156926 of 9 July 2010, which, therefore, are fully incorporated herein by reference.

The list of reference designations

[0076] 301 - pixel area,

302 - part of the peripheral circuits,

308 - the first item,

309 - the second element,

149 - the first structure of the layout,

150 - second structure wiring,

311 - pin plot,

314 - pin plot,

101 - the first substrate,

121 second substrate,

X - plane connections

111 - the first film prevent diffusion,

133 - the second film prevent diffusion.

1. Solid capture device image containing: - the first substrate, equipped with photoelectric Converter, located on its primary surface; - the first structure of the layout, which is located on the primary surface first and substrate which has the first contact area that contains conductive material; - the second substrate, provided that its primary surface, peripheral part of the scheme, including the control scheme and the scheme is read, the read signal on the basis of a charge of photovoltaic cell; and the second structure wiring, which is located on the primary surface of the second substrate, and which has the second contact area that contains conductive material, and the first contact area and the second contact the plot is connected so that the first substrate, the first structure of the layout, the second the structure of the layout and the second substrate are in order, and conducting material of the first contact of the site and conducting material of the second contact the plot is surrounded by films prevent diffusion.

2. Solid capture device image of claim 1, wherein the first contact the site contains conductive material and metal barrier, the second contact the site contains conductive material and metal barrier, and film prevent diffusion contain appropriate barrier metals.

3. Solid capture device image according to claim 2, in which the first structure of the layout has insulating interlayer film, which is the first contact section and metal barrier of the first contact the plot is located between a conducting material of first contact area and insulating interlayer film.

4. Solid capture device image according to claim 2, in which the second structure of the layout has insulating interlayer film, which is the second contact section and metal barrier of the second contact the plot is located between a conducting material of the second contact the site and insulating interlayer film.

5. Solid capture device image of claim 1, wherein each of conducting materials contains metal, with a higher diffusion coefficient than the diffusion coefficient of aluminium or alloys containing metal.

6. Solid capture device image in paragraph 5, in which each of conducting materials contain copper or alloy, mainly consisting of copper.

7. Solid capture device image of claim 1, wherein film prevent diffusion include the first film prevent diffusion, and the upper surface of the first structure wiring consists of the first contact of the plot and the first film prevent diffusion.

8. Solid capture device image in paragraph 7, in which the first film prevent diffusion is a picture surrounding the periphery of the first contact of the site.

9. Solid capture device image in paragraph 7, in which the first film prevent diffusion is a film of silicon nitride or film silicon carbide.

10. Solid capture device image of claim 1, wherein film prevent diffusion include the second film prevent diffusion, and the top surface of the second structure wiring consists of the second contact the site and the second film prevent diffusion.

11. Solid capture device image in paragraph 10, in which the second film prevent diffusion is a picture surrounding the periphery of the second contact the site.

12. Solid capture device image in paragraph 10, in which the second film prevent diffusion is a film of silicon nitride or film silicon carbide.

13. Solid capture device image of claim 1, wherein the second substrate is additionally provided with an amplifier transistor output a signal on the basis of the charge PV inverter, and a transistor reset to reset the charge PV inverter.

14. The system of formation of the image that contains: solid-state device image capture in one of claims 1 to 13; and a scheme of signal processing, signal processing, solid capture devices.