Digital function generator. RU patent 2513683.
 Method of simulating heterogeneous communication networks / 2481629In the method, initial data are given; a graph is plotted in each of the statistical experiments, in which there is or there is no route in given information directions; movement of subscribers is simulated, the initial topology and structure of heterogeneous networks is generated, wherein elements of heterogeneous communication networks are not connected to each other; a matrix of information directions between nodes of heterogeneous communication networks is formed; connection of a network node with another network node is simulated; paths of successful functioning for each information direction are fixed; carrying capacity and survival quotient values are generated; for the formed bridging line between nodes, the probability of availability of a route between subscribers is calculated. |
 Method of defining motion path of self-contained vehicle in dynamic medium / 2479015In compliance with this method, first data acquisition and processing cycle comprises generating multiple possible paths of further motion in preset time interval within duration of said cycle. Magnitude of expected utility is calculated for every said multitude using preset function of expected utility within preset time interval remained in said data acquisition and processing cycle. In next cycles, said multitude is rearranged to refine possible paths of further motion and to define new paths. |
 Method of generating regular sequences with elements composed of binary signals / 2469382Multibit devices based on the invention are characterised by stable, functionally unpredictable behaviour, exhaustively complete parallelism and easy implementation, low hardware and power costs and high efficiency. The device which realises the method has a clock pulse generator, a block of nonlinear controlled elements, consisting of configurable logic elements and D flip-flops. |
 Fast computation of products by dyadic fractions with sign-symmetric rounding errors / 2468422Given an integer variable x and rational dyadic constants which approximate the irrational fraction, a series of intermediate values which are sign-symmetric may be produced. The intermediate values may include a sequence of addition, subtraction and right shift operations then, when summed together, approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0 or shifts by 0 bits may be removed. |
 Method and apparatus for predicting nonstationary time series / 2467383Invention is related to radio engineering and can be used to predict data in systems for different purposes. The method of predicting nonstationary time series, based on an autoregressive model of a moving average with minimum mean-square error additionally involves operations for recirculating input data by one reading, oversampling the initial process in a logarithmic time scale, finding the energy spectrum of the obtained signal, determining response corresponding to entropy of the sampling energy spectrum, calculating the maximum value of entropy responses, finding a prediction for realisation, which corresponds to the maximum entropy value, oversamping the prediction result in an exponential time scale. |
 Method of generating random sequences with elements composed of binary signals / 2467378Invention relates to digital technology and can be used in generating random numbers and transforming data, processing noise-like signals, identification, authentication and authorisation, in stochastic systems and devices and systems for displaying information, information-communication and sensor devices and systems. Multibit devices based the invention are characterised by stable, functionally unpredictable behaviour, exhaustively complete parallelism and easy implementation, low hardware and power costs and high efficiency. The device which realises the method has a clock pulse generator, a block of nonlinear controlled elements, consisting of configurable logic elements and D flip-flops. |
 Elliptic curve-based electronic digital signature method / 2457625Method for electronic digital signature based on an elliptic curve in Weierstrass form, in which electronic digital signature system parameters are generated and a signature is formed and verified, wherein when forming and verifying the signature, the resultant point is found via doubling and summation of points of the elliptic curve given by projective coordinates (X, Y, Z), a bit string is found, representing the value XZ-1(modp) of the coordinates of the resultant point, wherein linear transformation of coordinates (X, Y, Z) of the point of the elliptic curve in Weierstrass form to coordinates (U, V, W) of a point of an elliptic curve in Hesse form is performed, operations for doubling and summation of the points are carried out on the elliptic curve in Hesse form, after which linear transformation of coordinates (U, V, W) of the resultant point of the elliptic curve in Hesse form to coordinates (X, Z) the point of the elliptic curve in Weierstrass form is carried out. |
 Device to search lower location score in matrix systems during bidirectional information transfer / 2447485In the known device containing shift registers, transposition forming unit (TFU), read-only memory unit, best version storage unit (BVSU), switch, ALU, arc selection decoder, reversible cell counter, random access memory unit, topology counter, distance counters, multiplier, adder, register of minimum connections length, comparison elements, subtractor, count start trigger, mode trigger, topology assignment trigger, connections length register, arc counter, arc locking decoder, arc number register, minimum weight register, electronic graph model, group of 1-st to n-th OR gates, group of 1-st to m-th AND gates, AND gates, OR gates units, univibrators, delay elements, the lower score generator is introduced. This generator contains matrix of (i,j) (i=1,2, …, m; j=1,2,…, n) adders, the first and the second row counters, the first and the second column counters, matrix of ((i,j) (i=1,2,…,m; j=1,2,…,n) registers, the first and the second decoders of horizontally fixed arcs, the first and the second decoders of vertically fixed arcs, matrix of (i,j) (i=1,2,…,m; j=1,2,…,n) OR gates, the first {(i,j) (i=1, 2,…,m; j=1,2,…,n) and the second (i,j) (i=1,2,…,m; j=1,2,…,n) matrices of AND gates, the first and the second delay elements, the first and the second incident vortex counter, the first and the second OR gates. |
 Railroad track section - connecting curve spiral / 2303284Shape of railroad track section - connecting curve spiral is determined as follows. Firstly, mathematical expression is selected, which is a function of distance along the spiral, which spiral determines the value of transverse pitching or banking angle of track, as function of distance along the spiral, and includes the length of spiral as a variable. Then a common condition is applied, stating that for a vehicle, passing through a section of track at set speed, in each point of spiral transverse components of centrifugal and gravitational accelerations in track plane are balanced. At next stage, a known differential equation is used, expressing aforementioned balance, and its integral is derived over distance along the spiral for determining angle (azimuth) of track direction relatively to track direction angle at the beginning of the spiral as a function of the distance along the spiral. Then track direction angle (azimuth), determined at previous stage, is used, and its sine and cosine are integrated over distance along the spiral to determine Cartesian spiral point coordinates relatively to spiral beginning coordinates, and, in such a way, definition of spiral is complete in accordance with mathematical function selected at the first stage. Steps from first to previous one are repeated with different variants of mathematical function until certain shape of spiral is found, which ensures connection between track sections with constant curvature on both ends of spiral. |
| Railroad track section - connecting curve spiral / 2303284 Shape of railroad track section - connecting curve spiral is determined as follows. Firstly, mathematical expression is selected, which is a function of distance along the spiral, which spiral determines the value of transverse pitching or banking angle of track, as function of distance along the spiral, and includes the length of spiral as a variable. Then a common condition is applied, stating that for a vehicle, passing through a section of track at set speed, in each point of spiral transverse components of centrifugal and gravitational accelerations in track plane are balanced. At next stage, a known differential equation is used, expressing aforementioned balance, and its integral is derived over distance along the spiral for determining angle (azimuth) of track direction relatively to track direction angle at the beginning of the spiral as a function of the distance along the spiral. Then track direction angle (azimuth), determined at previous stage, is used, and its sine and cosine are integrated over distance along the spiral to determine Cartesian spiral point coordinates relatively to spiral beginning coordinates, and, in such a way, definition of spiral is complete in accordance with mathematical function selected at the first stage. Steps from first to previous one are repeated with different variants of mathematical function until certain shape of spiral is found, which ensures connection between track sections with constant curvature on both ends of spiral. |
| Device to search lower location score in matrix systems during bidirectional information transfer / 2447485 In the known device containing shift registers, transposition forming unit (TFU), read-only memory unit, best version storage unit (BVSU), switch, ALU, arc selection decoder, reversible cell counter, random access memory unit, topology counter, distance counters, multiplier, adder, register of minimum connections length, comparison elements, subtractor, count start trigger, mode trigger, topology assignment trigger, connections length register, arc counter, arc locking decoder, arc number register, minimum weight register, electronic graph model, group of 1-st to n-th OR gates, group of 1-st to m-th AND gates, AND gates, OR gates units, univibrators, delay elements, the lower score generator is introduced. This generator contains matrix of (i,j) (i=1,2, …, m; j=1,2,…, n) adders, the first and the second row counters, the first and the second column counters, matrix of ((i,j) (i=1,2,…,m; j=1,2,…,n) registers, the first and the second decoders of horizontally fixed arcs, the first and the second decoders of vertically fixed arcs, matrix of (i,j) (i=1,2,…,m; j=1,2,…,n) OR gates, the first {(i,j) (i=1, 2,…,m; j=1,2,…,n) and the second (i,j) (i=1,2,…,m; j=1,2,…,n) matrices of AND gates, the first and the second delay elements, the first and the second incident vortex counter, the first and the second OR gates. |
| Elliptic curve-based electronic digital signature method / 2457625 Method for electronic digital signature based on an elliptic curve in Weierstrass form, in which electronic digital signature system parameters are generated and a signature is formed and verified, wherein when forming and verifying the signature, the resultant point is found via doubling and summation of points of the elliptic curve given by projective coordinates (X, Y, Z), a bit string is found, representing the value XZ-1(modp) of the coordinates of the resultant point, wherein linear transformation of coordinates (X, Y, Z) of the point of the elliptic curve in Weierstrass form to coordinates (U, V, W) of a point of an elliptic curve in Hesse form is performed, operations for doubling and summation of the points are carried out on the elliptic curve in Hesse form, after which linear transformation of coordinates (U, V, W) of the resultant point of the elliptic curve in Hesse form to coordinates (X, Z) the point of the elliptic curve in Weierstrass form is carried out. |
| Method of generating random sequences with elements composed of binary signals / 2467378 Invention relates to digital technology and can be used in generating random numbers and transforming data, processing noise-like signals, identification, authentication and authorisation, in stochastic systems and devices and systems for displaying information, information-communication and sensor devices and systems. Multibit devices based the invention are characterised by stable, functionally unpredictable behaviour, exhaustively complete parallelism and easy implementation, low hardware and power costs and high efficiency. The device which realises the method has a clock pulse generator, a block of nonlinear controlled elements, consisting of configurable logic elements and D flip-flops. |
| Method and apparatus for predicting nonstationary time series / 2467383 Invention is related to radio engineering and can be used to predict data in systems for different purposes. The method of predicting nonstationary time series, based on an autoregressive model of a moving average with minimum mean-square error additionally involves operations for recirculating input data by one reading, oversampling the initial process in a logarithmic time scale, finding the energy spectrum of the obtained signal, determining response corresponding to entropy of the sampling energy spectrum, calculating the maximum value of entropy responses, finding a prediction for realisation, which corresponds to the maximum entropy value, oversamping the prediction result in an exponential time scale. |
| Fast computation of products by dyadic fractions with sign-symmetric rounding errors / 2468422 Given an integer variable x and rational dyadic constants which approximate the irrational fraction, a series of intermediate values which are sign-symmetric may be produced. The intermediate values may include a sequence of addition, subtraction and right shift operations then, when summed together, approximate the product of the integer and irrational value. Other operations, such as additions or subtractions of 0 or shifts by 0 bits may be removed. |
| Method of generating regular sequences with elements composed of binary signals / 2469382 Multibit devices based on the invention are characterised by stable, functionally unpredictable behaviour, exhaustively complete parallelism and easy implementation, low hardware and power costs and high efficiency. The device which realises the method has a clock pulse generator, a block of nonlinear controlled elements, consisting of configurable logic elements and D flip-flops. |
| Method of defining motion path of self-contained vehicle in dynamic medium / 2479015 In compliance with this method, first data acquisition and processing cycle comprises generating multiple possible paths of further motion in preset time interval within duration of said cycle. Magnitude of expected utility is calculated for every said multitude using preset function of expected utility within preset time interval remained in said data acquisition and processing cycle. In next cycles, said multitude is rearranged to refine possible paths of further motion and to define new paths. |
| Method of simulating heterogeneous communication networks / 2481629 In the method, initial data are given; a graph is plotted in each of the statistical experiments, in which there is or there is no route in given information directions; movement of subscribers is simulated, the initial topology and structure of heterogeneous networks is generated, wherein elements of heterogeneous communication networks are not connected to each other; a matrix of information directions between nodes of heterogeneous communication networks is formed; connection of a network node with another network node is simulated; paths of successful functioning for each information direction are fixed; carrying capacity and survival quotient values are generated; for the formed bridging line between nodes, the probability of availability of a route between subscribers is calculated. |
 Digital function generator / 2513683Digital function generator consists of an adder-subtractor accumulator, first and second registers and a control unit. The digital function generator further includes a binary counter, two units of AND elements, a unit of OR elements and a unit for generating a parallel function code from a unitary code in order to realise the difference-iterative principle of monitoring the evaluation function, the value of which is defined in the adder-subtractor accumulator and is corrected in each logarithmic curve interpolation cycle via sub-summation (or subtraction) of contents of the binary counter (or register) depending on the sign of the adder-subtractor. The value of the binary counter is increased by two in each cycle. The number of unit increments of the ordinate is counted and at the end of conversion, that number is output as the output value of the logarithmic function. |
FIELD: information technology.
SUBSTANCE: digital function generator consists of an adder-subtractor accumulator, first and second registers and a control unit. The digital function generator further includes a binary counter, two units of AND elements, a unit of OR elements and a unit for generating a parallel function code from a unitary code in order to realise the difference-iterative principle of monitoring the evaluation function, the value of which is defined in the adder-subtractor accumulator and is corrected in each logarithmic curve interpolation cycle via sub-summation (or subtraction) of contents of the binary counter (or register) depending on the sign of the adder-subtractor. The value of the binary counter is increased by two in each cycle. The number of unit increments of the ordinate is counted and at the end of conversion, that number is output as the output value of the logarithmic function.
EFFECT: realising a logarithmic relationship with digital conversion of experimental data and reducing absolute error of conversion by half.
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The invention relates to digital and information technology and can be used for preliminary treatment of experimental input information in automated systems of scientific research.
Known functional digital converters [A.S. A SU G06F 15/20, A.S. 744595Al SU G06F 17/10] on the basis of differential-iterative principles of their functioning. The drawback of such functional converters is their inability functional transformation of the input data according to the law of the logarithm.
The closest to the technical nature of a functional digital Converter [A.S. 1188750 A1, SU, G06F 17/10]. It consists of accumulating adder-calculator, first and second registers, control unit, and the outputs of the control unit are connected with sinchronnogo enter data in accumulating adder-myCitadel, and inputs is accumulating adder-licitatile associated with output registers. The disadvantages of this functional digital Converter is the inability to implement them is logarithmic and large absolute error (one LSB).
The present invention is to expand the functionality of functional digital Converter in terms of opportunity functional transformation of experimental data on the law of the logarithmic function and decreased in two times the maximum absolute error.
The technical result is declared functional digital Converter allows you to implement a logarithmic dependence at digital conversion of experimental data and to halve absolute error of conversion.
The technical result is achieved by the proposed digital inverter, containing accumulating adder-myCitadel, the first and second registers, control unit, and the outputs of the control unit are connected with the state clock inputs enter data in the adder-myCitadel, and inputs is accumulating adder-licitatile associated with output registers. Also in it additionally introduced binary counter, the first and second blocks of elements And block elements OR block the formation of a parallel code of the function of the unitary code, and the binary outputs the meter through the first set of elements And block elements OR associated with the inputs of the accumulating adder-licitatile and outputs of the first case : through the second set of elements And block elements OR also associated with inputs accumulating adder-licitatile, the sign bit is connected to the control unit, the outputs of which are connected with the state clock inputs of the first and second elements And blocks, and the input and output block the formation of parallel code functions connected with control unit, the output of which is connected with the second youngest category of binary counter. Block the formation of a parallel code of the function of the unitary code contains the second counter-argument, the third counting function, the third block of logic elements And the second register functions, and counter inputs counter argument and counter functions connected with control unit, the state clock inputs of the third block of logic elements And related to the release of a second counter argument and with control unit, which also involve input reset to "0" second register functions and the third counter functions. The control unit contains the trigger, the first and the second lines of delay, the first, second and third element, And the first and the second element is NOT, and inverted output trigger is connected to the output of the control unit "the end of a conversion and through the second element is NOT next to the entrance of the third element, And the other input of which is connected to the input / clock pulses, and the output of the third element, And is associated with the inputs of the first and second elements And other inputs which are connected with direct access to the trigger, and the yield of the third element, And is associated with a counter input of the second counter-argument and with input of the second low-order binary counter, you can also sign the first element and NOT the entrance of the second item And are associated with significant discharge is accumulating adder-licitatile, and the output of the first element is NOT connected to the input of the first element And whose output through the first line of delays associated with the state clock inputs of the second unit element, And, as the output of the second element, And through a second line of delays associated with the state clock inputs of the first block element And with a counter input of the third counter options, reset to "0" which, as a second register functions, connected with the entrance Preinstallation PU, which is tied to the input reset to "0" trigger, the input set to "1" which is associated with the input of the "start" and, finally, the reset to "0" trigger associated with the release of the second counter-argument.
Distinctive features enabled implementation of functional transformation of the law of the logarithm, and the connection of the control unit with the iconic discharge is accumulating adder-licitatile and with the second youngest category of binary counter helped reduce absolute errors in two times (less than 0.5 of the unit of low-order position). This is a new technical solution in the technique of functional digital conversion, since the results of the applicant analysis analogues and prototype revealed no signs identical with all essential features of the invention.
The proposed device has inventive step, as of the published scientific data and existing technical solutions are not obvious that the stated set of units, assemblies and elements, as well as their links allows functional digital conversion on a logarithmic law.
Proposed functional digital Converter industrially applicable, since its implementation is possible with the use of standard elements of microelectronic technology (integrated logic circuits).
Figure 1 shows the functional diagram functional digital Converter.
The declared device contains (Fig 1) accumulating adder-myCitadel 1 with inlet 2 pre-setting values, the first register with 3 input 4 pre-set its value, unit elements "OR" 5, two blocks of elements "And" 6, 7, three counters 8, 9, 10, the last two 9, 10 of which are located in block 11 of the formation of a parallel code of the function Y of unitary code with input 12 input argument X. In the same block 11 of the formation of a parallel code of the function Y of unitary code is the third block elements And 22 and the second register 23. In addition, the declared device contains a control block 31, which includes the trigger 13, the first 14 and 15 second delay line, the first 16, 17 and the second third of the 19th elements And, for the first 20 and 21 second elements are NOT.
Accumulating adder-myCitadel 1, all the registers, all counters, block elements OR 5 blocks of elements And 6, 7 contain m binary bits, where m is the maximum bit depth input and output data, including mark. Moreover, the first register 3 through the block elements And 7 as binary counter 8 through the block elements And 6, are associated with a block of items OR 5, which is associated with storing the adder-licitatile 1. In addition, enabling inputs of elements And blocks 7 and 6 are connected to the outputs of the first 14 and 15 second delay lines, located in the control unit 31. In block 31 control trigger 13 has a direct and inverted outputs and inputs installation "1" and reset to "0". Element And 19 has two entrances and two members And 16, 17 have three entrances. Further, in block 11 of the counter of 9 has an input 12 input argument X, count 10 through the block "And" 22 connected to register 23 output value of the function Y. in Addition, the counter has 10 counter input 24 and entrance 25 reset to "0". Block And 22 has engraved 26, and the register has 23 entrance 27 reset to "0". Entrance 28 - signal pre-installation - marked "Poo". Entrance 29 - clock - marked "f". Entrance 30 marked the start menu. Exit 31 marked the end of a conversion". Login "PU" 28 is connected to the input reset to "0" trigger 13 and the entrance 25 reset 10 and the entrance 27 reset to "0" second register functions Y 23. Inverted output trigger 13 associated with the release of 31 finished testing". In the control unit 31 inverted output trigger 13 through the second element is NOT 21 is connected to the input of the third element And 19, at another entrance which comes heartbeats f 29, the output of which is connected to the inputs of the first 16 and 17 second elements I. Their exits through the first 14 and 15 second delay lines are linked with authorizing the inputs of elements And blocks 7 and 6, respectively. Direct access trigger 13 associated with the inputs of the first 16 and 17 second elements I. Input the first item 16 And NOT through the element of 20 is associated with a significant discharge of Zn is accumulating adder-licitatile 1. This category Mn is also connected to the input of the second item And 17. Output third element 19 And is also connected with the second youngest category of binary counter 8 and 18 entrance of the block 11. And the output of the second item 17 And is also connected to the input 24 block 11. Entrance 28 PU control unit 31 connected with inputs 25 and 27 of block 11. The output of the meter 9 in block 11 is connected to the input setup reset to "0" trigger 13 in block 31 and input 26 of block 11.
The reliability of achieving the goal of the invention is the implementation of the functional transformation by the logarithmic law is confirmed by mathematical reasoning set out in the journal "Izvestiya vuzov. The North Caucasus region, Technical Sciences, 2011, №2, p.16-18)"]. Logarithmic function has the form
y = M - log a ( 1 + x B ) ,where M and the scale of the axes X and Y, respectively,
A = M ln a ,B & GE; A,a>1, the Parameters a and b shall be rounded to the m - bit binary numbers.
Signal "0" with inverted output trigger 13 passes through the items 21 "NOT" and opens the item 19 "And". And another positive impulse frequency f (input 29) will proceed to the input of the first and second elements "And" 16 and 17 and on the second least significant bit binary counter 8, increasing its contents on the "+2", and the input of 18 meter 9 of the argument X, increasing its contents on the "+1". (Count 9 almost works as a subtractive). At the same time the positive momentum with the release of the second item 17 "And" will go to the counter input 24 10 functions Y, if the sign is accumulating adder-licitatile 1 will be "-" (a unit in landmark discharge Mn).
If the icon is accumulating adder-licitatile 1 is "+" (zero in the sign bit), entrance 24 count 10 of the function Y nothing will come (item 17 And will be closed). And the signal "1" will appear at the output of the first element is NOT 20. He will proceed to the input of the first item 16 I. After some time (less than a quarter of period f) there is a positive impetus on the first exit delay line Section 14 or second delay line Section 15 (only one), each of which posmitret or the contents of register WG 3 (through the second block elements "And" 7 and block elements "OR" 5) to running the adder-myCitadel 1, or the contents of a binary counter 8 (through the first block elements "And" 6 and block elements "OR" 5) to running the adder-myCitadel 1. On this one step input pulses f will end. The new value of the sign Mn accumulating adder-licitatile 1 will operate functional Converter in the next cycle. Each operating cycle of the input pulses f (input 29) is calculated based on the input 18 counter argument X 9 (he subtractive).
When entering exactly X (argument) pulse counter argument X 9 will give a signal to reset to "0" trigger 13. Signal "1" with its inverted output will be held on the release of " the end of a conversion, as well as through the second element is NOT 21 and will close the third element And 19 thereby interrupting the flow of impulses from the entrance f 29. At the same time the positive ("1"), the outputs of the counter argument X 9 will go to the state clock inputs 26 of the third block elements And 22, and the contents of the counter function Y 10 will be put in the second case the function Y 23, which is the output for functional digital Converter. Job functional digital Converter finished.
In the result of the conversion of the argument X is obtained logarithmic function
Y = M x log a ( x B ) .The reliability of functioning for the argument X=12 confirmed by a simple example M==7 and B=11 (a=e, where e is the base of natural algorithms (see table 1)). Small values a and b are taken for reasons of reducing the size of the table 1.
Table 1The results functional digital Converter: (with=7, B=11, and=e, X=12)
i Cm 1 MF 8 WG3 SC MF 10 7 x ln ( 1 + x 11 ) 0 -3 10 -13 -12 0 0 1 7 12 -13 -11 1 0,609 2 -6 14 -13 -10 1 1,169 3 8 16 -13 -9 2 1,688 4 -5 18 -13 -8 2 2,171 5 13 20 -13 -7 3 2,623 6 0 22 -13 -6 3 3,047 7 -13 24 -13 -5 3 3,447 8 11 26 -13 -4 4 3,826 9 -2 28 -13 -3 4 4,185 10 26 30 -13 -2 5 4,526 11 13 32 -13 -1 5 4,852 12 0 34 -13 0 5 5,163 X YY accurate
1. Digital functional Converter, containing accumulating adder-myCitadel, the first and second registers, the control unit, and the outputs of the control unit are connected with synchro-inputs enter data in the adder-myCitadel, and inputs is accumulating adder-licitatile associated with output registers, wherein it is additionally introduced a binary counter, the first and second blocks of elements And block of OR and block the formation of a parallel code of the function of the unitary code, and the binary outputs the meter through the first set of elements And block elements OR associated with the inputs of the accumulating adder-licitatile, and the outputs of the first case : through the second set of elements And block elements OR also associated with inputs accumulating adder-licitatile, the sign bit is connected to the control unit, the outputs of which are connected with the state clock inputs of the first and second elements And blocks, and the input and output block the formation of parallel code functions connected with control unit, the output of which associated with the second youngest category of binary counter.
2. The device of claim 1, characterized in that block the formation of a parallel code of the function of the unitary code contains the second counter-argument, the third counting function, the third block of logic elements And the second register functions, and counting inputs counter argument and counter functions connected with control unit, the state clock inputs of the third block of logic elements And related to the release of a second counter argument and with control unit, which also involve input reset to "0" second register functions and the third counter functions.
3. The device of claim 1, characterized in that the control unit contains the trigger, the first and the second lines of delay, the first, second and third element, And the first and the second element is NOT, and inverted output trigger is connected to the output of the control unit "the end of a conversion and through the second element is NOT next to the entrance of the third element, And the other input of which is connected with the entrance f heartbeat, and the output of the third element, And is associated with the inputs of the first and second elements And other inputs which are connected with direct access to the trigger, and the yield of the third element, And is associated with the accounts input of the second counter-argument and with input of the second low-order binary counter, you can also sign the first element and NOT the entrance of the second item And are associated with significant discharge is accumulating adder-licitatile, and the output of the first element is NOT connected to the input of the first element And whose output through the first line of delays associated with the state clock inputs of the second unit element, And, as the output of the second element, And through a second line of delays associated with the state clock inputs of the first block element And with a counter input of the third counter options, reset to "0" which, as a second register functions associated with entrance Preinstallation PU, which is tied to the input reset to "0" trigger, the input set to "1" which is associated with the input of the "start" and, finally, the reset to "0" trigger associated with the release of the second counter-argument.