Differential operational amplifier with paraphase output

FIELD: radio engineering, communication.

SUBSTANCE: amplifier includes third and fourth input transistors, emitters of which are connected to emitters of first and second input transistors, wherein the base of the third input transistor is connected to the base of the first input transistor, the base of the fourth input transistor is connected to the base of the second input transistor, collectors of the third and fourth input transistors are connected to the bus of a second power supply, emitters of the first and second input transistors are connected to emitters of the first and second additional transistors, the collector of the first additional transistor is connected to the collector of the first input transistor, the collector of the second additional transistor is connected to the collector of the second input transistor, wherein the first auxiliary output of the device is connected to bases of the first and second additional transistors through a first feedback resistor, and the second auxiliary output of the device is connected to bases of the first and second additional transistors through a second feedback resistor.

EFFECT: high stability of the output static in-phase voltage of the differential operational amplifier with a zero input in-phase signal.

2 cl, 7 dwg

The invention relates to the field of radio engineering and communication and can be used as a device for the amplification of analog signals, in the structure of the analog circuits of various functional purposes (e.g., bridge amplifiers, filters, Comparators, etc).

Known scheme of classical two-stage differential operational amplifiers (DN) [1-16] with two-rail output, which became the basis of many serial analog circuits.

Control of this class are used extensively in the structure of microwave devices based on SiGe technology. This is due to the possibility of building on the basis of their active RC-filters GHz range for modern and future communication systems, drivers, differential lines between SF-blocks, etc. greatly contributes to the ease of establishing static mode control with low-voltage power supply (1,2÷2,1), which is typical for SiGe transistors with cutoff frequencies of 120÷500 GHz.

The closest prototype (figure 1) of the claimed device is a differential amplifier according to patent US 4.600.893, fig.4, containing the first 1 and second 2-input transistors, bases of which are connected to respective inputs 3 and 4 devices, the first 5 dakotabilities dvukhpolosnykh included between the United emitters of the first 1 and Vtorov the 2 input transistors and the first bus 6 power source, the first 7 and second 8 output transistors, the emitter of the first 7 of the output transistor is connected to the collector of the first 1 of the input transistor and through the second 9 dakotabilities dvukhpolosnykh connected to the bus 10 second power source, the emitter of the second 8 output transistor connected to the collector of the second 2-input and transistor 11 through the third dakotabilities dvukhpolosnykh connected to the bus 10 second power source, a base of the first 7 and second 8 output transistors integrated and connected to a source of DC bias potential 12, the collector of the first 7 output transistor connected to the first 13 auxiliary output device and through the first 14 dvukhpolosnykh collector load connected to the bus the first 6 of the power source, the collector of the second 8 output transistor connected to the second 15 auxiliary output device and through the second 16 dvukhpolosnykh load connected to the bus of the first 6 power source.

A significant disadvantage of the known control is that it has an unstable level of the output common-mode voltage-dependent parameters of two-terminal collector load 14 and 15. This greatly complicates its coordination with subsequent functional nodes multistage front-end SF-blocks and IP modules.

The main objective of the present invention, sostoi is to create conditions, when the output of the static common-mode voltage control at zero input common-mode signal will have a high stability and a null value.

The problem is solved in that the differential operational amplifier with two-rail output, figure 1, containing the first 1 and second 2-input transistors, bases of which are connected to respective inputs 3 and 4 devices, the first 5 dakotabilities dvukhpolosnykh included between the United emitters of the first 1 and second 2 input transistors and the first bus 6 to the power source, the first 7 and second 8 output transistors, the emitter of the first 7 of the output transistor is connected to the collector of the first 1 of the input transistor and through the second 9 dakotabilities dvukhpolosnykh connected to the bus 10 second power source, the emitter of the second 8 of the output transistor is connected to the collector of the second 2-input and transistor 11 through the third dakotabilities dvukhpolosnykh connected to the bus 10 second power source, a base of the first 7 and second 8 output transistors integrated and connected to a source of DC bias potential 12, the collector of the first 7 output transistor connected to the first 13 auxiliary output device and through the first 14 dvukhpolosnykh collector load connected to the bus of the first 6 power source, the collector of the second 8 you are the one transistor is connected with the second 15 auxiliary output device and through the second 16 dvukhpolosnykh load connected to the bus of the first 6 power source, there are new elements and relationships in the scheme entered the third 17 and 18 fourth input transistors, the emitters of which are connected with the emitters of the first 1 and second 2 input transistors, the base 17 third input transistor is connected to the base of the first 1 of the input transistor, the base 18 fourth input transistor is connected to the second base 2 of the input transistor, the collectors of the third 17 and 18 fourth input transistors are connected to the bus 10 second power source, the emitters of the first 1 and second 2 input transistors connected to the emitters of the first 19 and second 20 additional transistors, the collector of the first 19 additional transistor connected to the collector of the first 1 input transistor, the collector of the second 20 additional transistor connected to the collector of the second 2-input transistor, and the first 13 auxiliary output device associated with the bases of the first 19 and second 20 additional transistors through the first 21 feedback resistor, and the second 15 auxiliary output device associated with the bases of the first 19 and second 20 additional transistors 22 through the second feedback resistor.

Figure 1 shows the control scheme of the prototype.

Figure 2 shows the diagram of the inventive device in accordance with claim 1 of the claims.

The circuit of a decoder according to claim 2 is shown in figure 3.

Figure 4 when the Eden diagram DN figure 3 with the specific implementation of the buffer amplifiers.

Figure 5 shows the diagram of the inventive control figure 4 in the environment of computer simulation Pspice models of integrated transistors FGUP NPP pulsar, and figure 6 dependence of its gain voltage from the frequency.

Figure 7 presents the dependence of the output voltage control figure 5 from the input sinusoidal voltage (u_I= 30 mV). Graphics Fig.7 show that the proposed control has two anti-phase output voltage and the zero level of the output common-mode static electricity.

Differential operational amplifier with two-rail output, figure 2, contains the first 1 and second 2-input transistors, bases of which are connected to respective inputs 3 and 4 devices, the first 5 dakotabilities dvukhpolosnykh included between the United emitters of the first 1 and second 2 input transistors and the first bus 6 to the power source, the first 7 and second 8 output transistors, the emitter of the first 7 of the output transistor is connected to the collector of the first 1 of the input transistor and through the second 9 dakotabilities dvukhpolosnykh connected to the bus 10 second power source, the emitter of the second 8 output transistor connected to the collector of the second 2-input transistor and through the third 11 dakotabilities dvukhpolosnykh connected to the bus 10 second power source, a base of the first 7 and second 8 output is ransistors combined and connected to a source of DC bias potential 12, the collector of the first 7 output transistor connected to the first 13 auxiliary output device and through the first 14 dvukhpolosnykh collector load connected to the bus of the first 6 power source, the collector of the second 8 output transistor connected to the second 15 auxiliary output device and through the second 16 dvukhpolosnykh load connected to the bus of the first 6 power source. In the scheme entered the third 17 and 18 fourth input transistors, the emitters of which are connected with the emitters of the first 1 and second 2 input transistors, the base 17 third input transistor is connected to the base of the first 1 of the input transistor, the base 18 fourth input transistor is connected to the second base 2 of the input transistor, the collectors of the third 17 and 18 fourth input transistors are connected to the bus 10 second power source, the emitters of the first 1 and second 2 input transistors connected to the emitters of the first 19 and second 20 additional transistors, the collector of the first 19 additional transistor connected to the collector of the first 1 of the input transistor, the collector of the second 20 additional transistor connected to the collector of the second 2-input transistor, and the first 13 auxiliary output device associated with the bases of the first 19 and second 20 additional transistors through the first 21 feedback resistor, and the second 15 spare Gately output device associated with the bases of the first 19 and second 20 additional transistors 22 through the second feedback resistor.

Figure 3 in accordance with claim 2, the first 13 auxiliary output device associated with the bases of the first 19 and second 20 additional transistors connected in series through the first 23 additional buffer amplifier 21 and the first feedback resistor, and the second 15 auxiliary output device is connected with the base of the first 19 and second 20 additional transistors connected in series through the second 24 additional buffer amplifier 22 and the second feedback resistor.

Figure 4 buffer amplifiers 23 and 24 are implemented respectively by transistors 25, 26, p-n junctions 27, 28, and transistors 29, 30 and p-n junctions 31, 32.

Consider the operation of the remote control 2.

Static mode current of the transistors of the proposed control is set by the two-terminal 5, 9, 11, 14, 16.

Static voltage U₁₃=U₁₅outputs VIH and VIH do with zero input signal (u_I=0) can be found from the equation:

$$\begin{array}{c}{U}_{13}=I_b{R}_{21}-U_{eb.19}+U_{eb.1}\approx I_b{R}_{21}\approx 0\\ U_{15}=I_b\end{array}$$

where U_AB= U_ABU_AB= U_AB- the voltage of the emitter-base transistors 1, 2, 19 and 20;

$$I_b\frac{I_{b.\Sigma }}{2}$$- component of the total current bases of transistors 19 and

20 in the feedback resistor 21 (22).

Thus, at typical values of the base currents of the transistors 19, 20, and when R₂₁=R₂₂=500÷1000 Ohm output common-mode voltage control 2 is almost equal to zero in a wide range of temperature and radiation effects, and changes in the supply voltage. It is highly essential to reconcile the claimed control with subsequent functional blocks of electronic equipment and its use in bridge amplifiers.

Thus, the proposed control has significant advantages in comparison with the prototype.

BIBLIOGRAPHIC LIST

1. Patent US 4.406.990, fig.3.

2. Patent US 4.600.893, fig.4.

3. Patent US 5.684.419.

4. Patent US 3.979.689.

5. Patent USRe 30.587.

6. Patent US 5.684.419.

7. Patent US 4.151.483, fig.4.

8. Patent US 4.151.484, fig.4.

9. Patent US 4.406.990.

10. Patent US 5.557.238, fig.5.

11. Patent US 6.580.325, fig.26.

12. Patent US 3.733.559.

13. Patent US 5.376.897.

14. Patent 3.079.689 15.

15. Patent EP 0144647.

16. Patent JP 60090407.

1. Differential operational amplifier with two-rail output, containing the first (1st) and second (2) input transistors, bases of which are connected to the corresponding inputs (3) and (4) of the device, the first (5) dakotabilities dvukhpolosnykh included between the United emitters of the first (1) and second (2) input transistors and a first bus (6) power source, the first (7) and second (8) output transistors, the emitter of the first (7) of the output transistor is connected to the collector of the first (1) of the input transistor and through the second (9) dakotabilities dvukhpolosnykh connected to the second bus (10) power source, the emitter of the second (8) of the output transistor is connected to the collector of the second (2) input through the third transistor and (11) dakotabilities dvukhpolosnykh connected to the second bus (10) power source, a base of the first (7) and second (8) output transistors integrated and connected to the source bias voltage potentials (12), the collector of the first (7) output transistor connected to the first (13) auxiliary output device and through the first (14) dvukhpolosnykh collector is agrusti connected to the bus of the first (6) power source, the collector of the second (8) of the output transistor is connected with the second (15) auxiliary output device and a second (16) dvukhpolosnykh load connected to the bus of the first (6) power source, characterized in that in the scheme entered the third (17) and fourth (18) input transistors, the emitters of which are connected with the emitters of the first (1) and second (2) input transistors, the base of the third (17) of the input transistor is connected to the base of the first (1) of the input transistor, the base of the fourth (18) of the input transistor is connected to the base of the second (2 the input transistor, the collectors of the third (17) and fourth (18) of the input transistors connected with the second bus (10) power source, the emitters of the first (1) and second (2) input transistors are connected to the emitters of the first (19) and second (20) additional transistors, the collector of the first (19) of the additional transistor is connected to the collector of the first (1) of the input transistor, the collector of the second (20) additional transistor connected to the collector of the second (2) input transistor, and the first (13) auxiliary output device associated with the bases of the first 19) and second (20) additional transistors through the first (21) feedback resistor, and the second (15) auxiliary output device associated with the bases of the first (19) and second (20) additional transistors through the second (22) feedback resistor.

2 Differential operational amplifier with two-rail output according to claim 1, characterized in that the first (13) auxiliary output device associated with the bases of the first (19) and second (20) additional transistors connected in series through the first (23) additional buffer amplifier and the first (21) feedback resistor, and the second (15) auxiliary output device is connected with the base of the first (19) and second (20) additional transistors connected in series through the second (24) additional buffer amplifier and the second (22) feedback resistor.