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Input stage of high-speed operational amplifier. RU patent 2509406.

Input stage of high-speed operational amplifier. RU patent 2509406.
IPC classes for russian patent Input stage of high-speed operational amplifier. RU patent 2509406. (RU 2509406):

H03F3/34 - Dc amplifiers in which all stages are dc-coupled (H03F0003450000 takes precedence);;
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Cascode differential amplifier Cascode differential amplifier / 2319292
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Cascade differential amplifier Cascade differential amplifier / 2319293
Cascade differential amplifier contains input differential cascade (1), transistors (2) and (3) of intermediate cascade, bases of which are connected to shifting voltage supply (4), and emitters are connected to outputs (5) and (6) of differential cascade (1) and through first (7) and second (8) current-stabilizing dipoles are connected to bus of first (9) power supply, where collector of transistor (3) of intermediate cascade is connected to input (10) of buffer amplifier (11) and collector of transistor (12) of intermediate cascade, emitter of which is connected to emitter of transistor (13) of intermediate cascade and to bus of second intermediate cascade (14), and base is connected to base of transistor (13) and collector of transistor (2). An additional transistor (15) is introduced to the circuit, base of which is connected to common bus of first (9) and second (14) current supplies, collector is connected to emitter of transistor (2), and emitter is connected to collector of transistor (13), resulting in reduction of zero shift EMF of cascade differential amplifier due to identical shift of input characteristics of transistors (13) and (12), caused by influence of Early effect.
Complementary differential amplifier Complementary differential amplifier / 2320078
Complementary differential amplifier contains input differential cascade (1) on p-n-p input transistors (2) and (3), second differential cascade (10) on n-p-n input transistors (11) and (12). Introduced to the circuit are first and second additional p-n-p transistors (17) and (18), collectors of which are corresponding main outputs (19) and (20) of complementary differential amplifier, matched with the bus (18) of negative power supply, and also first and second additional n-p-n transistors (21) and (22), collectors of which are main outputs (23) and (24) of complementary differential amplifier, matched with the bus (15) of positive power supply, where bases of transistors (17) and (18) are connected to second current-stabilizing dipole (16) of differential cascade (10), bases of transistors (21) and (23) are connected to first current-stabilizing dipole (9) of differential cascade (1), emitters of transistors (21) and (22) are connected to collectors of transistors (11) and (12), emitters of transistors (17) and (18) are connected to collectors of transistors (2) and (3).

FIELD: radio engineering, communication.

SUBSTANCE: input stage of the operational amplifier comprises first (1) and second (2) input transistors, first (3) and second (4) output transistors, first (5) and second (6) auxiliary transistors, first (7) and second (8) device inputs, first (9) and second (10) forward-biased p-n junctions, a first (11) current-stabilising two-terminal device, current outputs of the device (12), (13), (14), (15), first (16) power supply bus, where between the second (10) p-n junction, connected to the emitter of the second (6) transistor, and a second (17) power supply bus, there is a first (11) two-terminal device connected, between the first (9) p-n junction, connected to the emitter of the first (5) transistor, and the second (17) power supply bus, there is a second (18) two-terminal device connected, between the common node (19) of the first (9) p-n junction and the second (18) two-terminal device, as well as the common node (20) of the second (12) p-n junction and the first (11) two-terminal device, there are series-connected third (21) and fourth (22) resistors, the common node (23) of which is connected to the bases of the first (3) and second (4) input transistors.

EFFECT: wider range of active operation of the input stage of the operational amplifier for a differential signal.

18 dwg

 

The invention relates to the field of radio engineering and communication and can be used as a device to gain analog signals with a wide dynamic range, in the structure of analog chips of different functional purposes (for example, high-speed operational amplifiers (op amps)).

Known scheme of input stages of the OS, made in the form of differential amplifiers (DU) on n-p-n and p-n-p transistors with so-called «architecture of input bandwidth operational amplifier µA741» [1]. On their modifications issued more than 50 patents for the leading microelectronic companies of the world. Differential amplifiers of this class, along with the model of parallel-balanced cascade

[29-30], became the main amplifier element in many of the analog interface. This is because in such remote control input capacitance is minimized due to the lack of effect Miller. The present invention relates to this subclass devices.

The closest prototype (1) the claimed device is the input cascade high speed operational amplifier on patent US 4.901.031 containing 1 first and second input 2 transistors, emitters which are linked to the relevant emitters first 3 and 4 second output transistors with United bases, the first 5 and 6 second auxiliary transistors, the bases of which are connected with the relevant databases 1 first and second 2 input transistors and is connected to the corresponding first 7 and 8 second input device, the first and the second 10 p-n transitions included in the relevant emitters first 5 and 6 second auxiliary transistors, the first 11 , current output devices 12, 13, 14, 15, associated with collectors the first 1 and 2 second input transistors, as well as collectors of the first 3 and 4 second output transistors, and the collectors of the first 5 and 6 second auxiliary transistors connected with the first 16 bus power supply.

A significant disadvantage of remote control is that it has a relatively narrow dynamic range (U gr ) linear differential (U who <U gr ≈100-150 mV). As shown in [31], and this fact is the main cause of low performance of modern op amps, due to the nonlinear regime of work in the input stage of the OS. However for the majority of the OS with high impedance node and one correction capacitor maximum slew rate output voltage

* in s x = 2 PI f with R U g R , ( 1 )

where f cf is the unity gain frequency (cut-off frequency) adjusted OS;

U gr - voltage limits passing characteristics i o =f(u of I ) the input stage (for classic Doo gr U =50% to 100 mW). From (1) it follows that the increase u o can be done in two different ways:

1. The increase of the range of active work input DN (U, g ) without change of the slope of the conversion of the input voltage at output currents of remote control;

2. Rising f Wed by improving the frequency properties of transistors, which is primarily connected with the use of more high-technological processes (SG25VD, SG25H1, SG25RH and others). Declare input cascade OS solves the problem of increasing performance through increased (without change of the slope) by more than an order of a range of line work gr U =1-2B.

Thus, the main task of the invention consists in expanding the range of active work in the input stage of the shelter for differential signal - receiving U gr >>100 mV.

The task is reduced because input cascade high speed operational amplifier containing 1 first and second 2 input transistors, emitters which are linked to the relevant emitters first 3 and 4 second output transistors with United bases, the first 5 and 6 second auxiliary transistors, the bases of which are connected with the relevant databases 1 first and second 2 input transistors and connected to the corresponding first 7 and 8 second input device, the first and the second 10 p-n transitions included in the relevant emitters first 5 and 6 second auxiliary transistors, the first 11 , current output devices 12, 13, 14, 15, associated with the collectors of the first 1 and 2 second input transistors, as well as collectors of the first 3 and 4 second output transistors, and the collectors of the first 5 and 6 second auxiliary transistors connected with the first 16 bus power supply that differs between the second 10 p-n-transition, included in the emitter 6 second subsidiary of the transistor, and the second on 17 bus power supply included the first 11 , between the first 9 p-n transition, included in the emitter of the first 5 of the subsidiary transistor, and the second on 17 bus power supply is on the second 18 , between the General node 19 the first 9 p-n junction and the second 18 of , as well as a common node 20 second 12 p-n junction and the first 11 of consistently included third, 21 and 22 fourth additional resistors, shared node 23 which is connected with the bases of the first 3 and 4 second input transistors.

The amplifier circuit prototype presented in figure 1. Figure 2 shows the proposed device in accordance with the formula of the invention.

Figure 3 shows a possible architecture for high-speed operational amplifier to offer input stage.

Figure 4 shows a scheme DU prototype 1 in the environment of computer modeling PSpise on models of integrated transistors FGUP NPP «pulsar».

Figure 5 shows the dependence of the differential output currents (I(1)I(out2)) and (I(out3)-I(out4)) DN-prototype figure 4 the input voltage u of I .

Figure 6 shows the dependence of absolute values of output currents of I(1) and I(out2) do prototype figure 4 the input voltage u of I . The dependence of the output currents I(out3) and I(out4) do prototype figure 4 the input voltage u VH figure 7 presents.

On Fig shows the scheme of the claimed Doo 2 in the environment of computer modeling PSpise on models of integrated transistors FGUP NPP pulsar, and figure 9 - Fig - based differences output currents (I(out1)-I(out2)) and (I(out3)-I(out4)) to the input voltage u I do pig at various values of resistance additional resistors 21, 22 (R var ).

On Fig presents the dependence of absolute values of output currents of I(1) and I(out2) declare do FIH the input voltage u VH when resistance additional resistors 21, 22 var R =200 Ohms, and on Fig - dependence of the output currents I(out3) and I(out4) declare do FIH the input voltage u VH when resistance additional resistors 21, 22 var R =200 Ohms.

On Fig shows the dependence of absolute values of output currents of I(1) and I(out2) declare do FIH the input voltage u VH when resistance additional resistors 21, 22 var R =1 kOhm, and on Fig - dependence of the output currents I(1) and I(out2) declare do FIH the input voltage u VH when resistance additional resistors 21, 22 var R =1 kOhm in enlarged scale.

On Fig presents the dependence of the absolute values of output currents I(out3) and I(out4) declare do to the input voltage u when I var R =1 kOhm, and on Fig - dependence of the output currents I(out3) and I(out4) declare do to the input voltage u when I var R =1 kOhm in enlarged scale.

The input stage (DN) high-speed operational amplifier 2 1 contains the first and second 2 input transistors, emitters which are linked to the relevant emitters first 3 and 4 second output transistors with United bases, the first 5 and 6 second auxiliary transistors, base which joined with the appropriate databases of the first 1 and 2 second input transistors and is connected to the corresponding first 7 and 8 second input device, the first and the second 10 p-n transitions included in the relevant emitters first 5 and 6 second auxiliary transistors, the first 11 , current output devices 12, 13, 14, 15, associated with the collectors of the first 1 and 2 second input transistors, as well as collectors of the first 3 and 4 second output transistors, and the collectors of the first 5 and 6 second auxiliary transistors connected with the first 16 bus power supply. Between the second 10 p-n transition, included in the emitter 6 second subsidiary of the transistor, and the second on 17 bus power supply included the first 11 , between the first 9 p-n transition, included in the emitter of the first 5 of the subsidiary transistor, and the second on 17 bus power supply is on the second 18 , between the General node 19 the first 9 p-n junction and the second 18 of , as well as a common node 20 second 12 p-n junction and the first 11 of consistently included 21 third and fourth 22 additional resistors, shared node 23 which is connected with the bases of the first 3 and 4 second input transistors.

Fig.3. declare input Kaskad 2 (24) included in the structure of fast-acting OS, which contains supplementary current mirrors 25, 26, output buffer 27 and correction capacitor 28. This OS is covered 100% negative feedback.

Consider the work of the claimed device figure 2.

In connection with the fact that the voltage drop across the resistor 21, 22, generated by currents base transistors 3 and 4, a little, static currents of all transistors schemas are defined by current of of two-terminal 18 and 11. Due to increase of the areas emitter transitions transistors 1, 2 and 3, and 4 can be zero when the input voltage DN to ensure equality emitter circuit currents:

I E. 1 = I E. 2 = I E. 3 = I E. 4 = I E. 5 = I E. 6 ≈ I E. 0 , ( 1 )

where I 0 =18 I =I 11 .

If the stress on the first 7 input (WH) DN becomes more stress on the first 8 input Doo, then the collector currents transistor 1 and 3 increase and transistors 2 and 4 - reduced. The input differential voltage u I «stands out» on resistors 21 and 22, which increased the «opening» of tensions between the base of the transistor 1 and the base of the transistor 3:

u b 1 - 3 ≈ u in x 2 . ( 2 )

Thus collector (weekend) transistor currents 1 and 3 will be proportional to the input voltage within a wide range of u of I :

where r E1 , E2 r - emitter resistance transitions transistors 1 and 3;

R 21 =R 22 - the resistors 21 and 22;

β 3 - the gain on the base current of the transistor 3;

R - resistance volume of low-emitter resistor or an additional resistor R d =10-20 Ohm included in a number of cases in the emitter circuit transistor 1 and 3 (Fig).

Given that with the increase of I a resistance r E1 and E2 r diminish substantially, from (3) we can find that for large u I

i 12 = i 14 ≈ u in x 2 ( R E. + R 21 2 β 3 ) = u in x S , ( 4 ) where S = 1 2 ( R E. + R 21 2 β 3 )

- slope do.

Equation (4) is valid for the following input voltage amplitudes

U in x . m and x ≤ U g R = I 0 R 21 = I 0 R 22 . ( 5 )

Thus, the range of active work Doo 2 is determined by the product of (5) and can be chosen in accordance with the required values * to o operational amplifier (1). These conclusions are supported by graphs (figures 9-17), which suggests that the range of the active work of the claimed Doo increases in the order in comparison with gr U do prototype.

Thus, the migratory characteristics i o =f(u of I ) declare Doo «extended» in the area of large currents (Fig.9-17), significantly exceeding the static current transistors do. This is true for transistor cascades class of «AV».

When u negative I do figure 2 works similarly.

The results of computer simulation control (Fig), are presented in diagrams (figures 9-17)confirm the above theoretical conclusions.

We offer remote control can be used in the structure of high-speed operational amplifiers of various functional purposes, as well as analog chips with a wide range of line work.

THE BIBLIOGRAPHIC LIST

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30. Mhere. Analog integrated circuits. - M: Radio and communication, 1983, there were, RIS.

31. Operational amplifiers with direct connection cascades [Text] / Dionisiou, Mavlatov, Pop, Humorov. - Leningrad, 1979. - 148 S.

Input cascade high speed operational amplifier that contains the first (1) and second (2) the input transistors, emitters which are linked to the relevant emitters first (3) and 2 (4) of the output transistors with United bases, the first (5) and the second (6), the subsidiary transistors, the bases of which are connected with the relevant bases of the first (1) and second (2) input transistors and connected to the first (7) and the second (8) to inputs of the device, the first (9) and second (10) p-n transitions included in the relevant emitters of the first (5) and the second (6), the subsidiary of transistors which first (11) , the current outputs of the device(12), (13), (14), (15), associated with the collectors of the first (1) and second (2) input transistors, as well as collectors of the first (3) and 2 (4) of the output transistors, and the collectors of the first (5) and the second (6), the subsidiary of transistors connected with the first (16) bus power supply, wherein between the second (10) p-n transition, included in the emitter of the second (6), the subsidiary of the transistor, and the second (17) bus power supply included first (11) , between the first (9) p-n transition, included in the emitter of the first (5) subsidiary of the transistor, and the second (17) bus power supply is on the second (18) , between the General node (19) on the first (9) p-n junction and the second (18) of , and also shared host (20) second (12) p-n junction and the first (11) of consistently included third (21) and fourth (22) additional resistors, shared node (23) which is connected with the bases of the first (3) and 2 (4) input transistors.

 

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