IPC classes for russian patent Apparatus for synchronising control system for stand tests of space-rocket equipment. RU patent 2506621. (RU 2506621):
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FIELD: physics; control.
SUBSTANCE: invention relates to automated control systems for technological processes during ground testing of space-rocket equipment and can be used in developmental testing of aviation and transportation equipment, as well as chemical plants. The technical result is achieved through the apparatus for synchronising the control system for stand tests of space-rocket equipment and includes, in the processor of each master controller, a unit for interfacing with a local area network, connected through a control unit to a cycle counter, a cycle duration timer, a transportation delay register and a correction period counter, connected to a correction time register.
EFFECT: providing universal time and synchronisation of operating cycles of a distributed network of homogeneous master controllers irrespective of their number, arrangement and back-up version.
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The invention relates to the automated systems of control of technological processes during ground testing of rocket-and-space technology (CT) and can be used to trap practicing aviation, transport equipment and chemical installations.
Features poster ground tests rockets are high performance demands management systems of these trials and distributed nature of the construction of these systems. Cycle management of programmable controllers, which are the basis of these systems is usually 10 to 20 MS. Distributed nature of their associated with the presence at the stand number located at a great distance from each other (for security reasons), technological systems with different functions (management systems the fuel, oxidizer, water, gases; systems management products, the stand; on the implementation of regulation tasks, logic control, emergency protection). Eventually, the number of controllers with respect to the necessary (from the requirements of reliability) reserves can reach the exhibition stand 15-20 sets, implement up to 10 sub-systems of control of this stand and a product.
Information, including measuring circulating in the control controllers should be synchronized to the subsystems of the issued command with a given time accuracy and ensure correct processing of the recorded data. Also, synchronization is very important for controllers, enabled by scheme 2 from 3, for the exception of differences on various branches of the implemented algorithm management.
A device synchronization control system of stand tests CT (see article Afonina V.V. and other Synchronization channels triple PLC hard RV», journal Industrial ACS and controllers», №6, 2004), as implemented in each host controller system management and comprising a unit pairing with a local area network, connected first and second inputs / outputs respectively with a local area network and with the first exit and entrance control unit, the second input-output which is connected to the inputs or outputs of the loop counter and timer duration of the cycle.
The synchronization procedure of work of controllers is in this case in the exchange of processors controllers signals the start of the next cycle of their work and implementation, then the origin of its duration and logical functions these signals.
The disadvantage of this solution is to synchronize channels each or duplicate controller, not the entire set of controllers, forming distributed in space network with different variants of their reservation. In connection with this, there are problems with the implementation of the master controllers interrelated algorithms, tied to a single scale of time, and during the processing of the test results.
The technical problem solved by the invention consists in provision of universal time and synchronization of cycles of a distributed network of homogeneous controllers regardless of their number, location and reservations.
This is achieved by a known device synchronization control system of stand tests of rocket and space technology, as implemented in each processor controller and contains the interface unit with a local area network, connected first and second inputs / outputs respectively with a local area network and with the first exit and entrance control unit, the second input-output which is connected to the inputs or outputs of the loop counter and timer duration of the cycle, according to the invention introduced register the transport delay, the output of which is connected to the input of the control unit to counter the period of correction, connected to an input-output with the third exit and entrance control unit, and the register of the period of correction, connected to its output to the input of the counter period of correction.
The drawing shows the layout of the device.
The device contains a interface block with a local area network 1, first and second inputs / outputs connected respectively with a local area network and the first exit and entrance control unit 2, register the transport delay 3 connected output to the input of the control unit 2, counter loops 4 and duration timer cycle 5, connected to the inputs / outputs to the second entrance-exit control unit 2, the third input-output of which is connected with the entrance-exit counter the period of correction 6. Input of the latter is connected to the output register of the period of correction 7.
The device works as follows.
In the initial state, all counters are reset to zero. In the register of transport lag 3 is set to delay receipt of the information from a local area network (LAN), determined empirically. Usually it is 30-50 ISS. In the register of the period of correction 7 is set to 100+5H, expressed as the number of cycles of controller of number N in the network. When the duration of the cycle, equal to 10 MS, these values for controllers, starting from a certain first, will be 1050, 1100, 1150 MS etc. With this period of time processors controllers via the control unit 2 and unit mates on LAN 1 is sent in a LAN telegram about time correction. Telegram accompanied by the values of the States of their timer duration of cycle 5 and counter loops 4.
The device in the structure of the processor first controller works as follows. In the beginning of the next cycle of work of the management controller, which is determined in its processor control unit 2 at a signal the end of the account timer duration of cycle 5, of the value of counter, the period of correction 6 installed initially register the period of correction 7, subtracts one. Moment of the termination of the account at the counter of the period of correction 6 will come faster just the first host controller (through 1050 MS). At the same time control unit 2 reads the value of the loop counter 4 and timer duration of cycle 5 and sends to the network through the LAN interface unit 1 telegram time correction processors other controllers. This telegram, as mentioned in the previous paragraph, accompanied by the values of the States count 4 and timer duration of the cycle of 5 processor of the controller.
The device in the structure of the processor controller of another (not the first) number works as follows. While obtaining LAN another telegram (from the described above, the health of all controllers it will be a telegram from the first of them), containing the values of the state of the cycle counter 4, equal To-W1, and timer duration of cycle 5, equal T-W1, the processor first controller, the control unit 2, which got through the interface block on LAN 1 these values at a specified time, sets the timer duration of cycle 5, the value of T-W1+t, where t is calculated from the register of transport lag 3 and counter loops 4 assigns a value to To-W1. Then count the period of correction 6 at the command of the control unit 2 is written to the value set in register of the period of correction 7. As described above, this value is 1000+50N, where N - the number of the controller. Further counter the period of correction 6 reduces its value per unit by timer signal cycle time was 5. In the result of the preceding operations processors all controllers will have the same values loop counters 4 and timers cycle duration of 5.
Minor deviations may be associated with the work of the operating system processor and controller for the transfer of information over the LAN. From the described procedure for work of the device, that the refusal of the first Manager of the controller sync feature automatically takes care of the next number master controller. At power-the specified procedure provides quick entry system management in synchronism. When the system is management of the value of the loop counter 4 & alarms timer duration of the cycle of 5 are each processor and controller at realization of algorithms of control tests of rockets. On the diagram, there are no inputs in the registers of transport lag 3 and the period of correction of 7, which means a member function install codes in them the same registers, for example, by means of jumpers.
An important point in the use of the proposed technical solution is the ability to bind the work of controllers to current date and time and increase the reliability of synchronization of the distributed system of management by one or more controllers (or their processor modules) with the lowest numbers included in the LAN and receiving signals navigation systems such as GPS and GLONASS.
Device synchronization control system of stand tests of rocket and space technology, as implemented in each processor and controller and comprising a unit pairing with a local area network, connected first and second inputs / outputs respectively with a local area network and with the first exit and entrance control unit, the second input-output which is connected to the inputs or outputs of the cycle counter and timer duration of the cycle, characterized in that it introduced register the transport delay, the output of which is connected to the input of the control unit to counter the period of correction, connected to an input-output with the third exit and entrance control unit, and the register of the period of correction, connected to its output to the input of the counter the period of correction.
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