# Digital predictor

FIELD: information technology.

SUBSTANCE: device has a smoothing unit consisting of an adder, inverters, comparators, counters, AND logic elements, a deviation ratio setting unit and a dynamic characteristic control unit, and a prediction unit comprising three subtractors, two prediction subunits and a register.

EFFECT: high accuracy of prediction and simplification of the device.

7 dwg, 2 tbl

The invention relates to automation and can be used for forecasting of stationary and nonstationary random processes, improve the quality and accuracy control in digital real-time systems for the regulation, control and guidance of various objects.

A device for adaptive extrapolation on avtv No. 1246775 (USSR author's certificate No. 1246775, CL G06F 15/353, 1984)containing the block smoothing and block extrapolation, the latter comprises three serially connected vicites and the adder result. This device is functionally limited and has little time prediction (extrapolation). The closest to the technical nature of the claimed device is selected as a prototype device for the application 2010125731/20 (036606) from 23.06.2010, the containing block smoothing and block prediction, the latter contains three myCitadel, the register set a time (interval) of the forecast and two subunits: quadratic and linear projections. This device has a short response time (three beats to smooth and three on the forecast) and a small quadratic accuracy of the forecast.

The task, which is aimed by the invention, is to improve the accuracy of the quadratic prediction and simplification of the device.

Therefore, in the digital prediction device containing the block with the establish on the application 2010125733/20 (036608) from 23.06.2010,, composed of the adder, a first input of which is an information input device, the first and second blocks of the Comparators, the input of which is connected to the output of the adder, and the first comparator directly, and the second through a unit inverter unit assignments ratio deviations, containing (as a controllable frequency divider) register, a counter and a delay element, information and clock inputs of the block are the first Manager and the clock inputs of the device, respectively; the first element And the first input of which is connected to the clock input of the second and third inputs, respectively, to the outputs of the first and second blocks Comparators, the first reversible counter, a subtractive input connected to the output of unit assignments ratio of variances, the inverter, the second and third elements And the second reversible counter of the smoothing and the control unit dynamic characteristics (BUDH), the first input of which is connected to the first input of the third element And to the output of the inverter, the second input is connected to the first input of the second element And the input of the inverter and the output of the sign digit of the adder, and the first output BUDH connected to the reset input to "0" first and to the bus entry of the second reversible counter, and BUDH contains an element OR counter, the trigger, the first and second elements And the PE the first and second pulse shapers, the inputs are first and second inputs BUDH through pulse shapers connected to both inputs of the OR element, the output of which is connected to the tire reset to "0" of the counter and the trigger input set to "1" which is connected to the output of the first element And the first input of which is connected with the senior discharge counter and a second input from a clock input of the counter and the device and the second input of the second element And the first input of which is connected to the direct trigger output and inverted output of the last - to the fourth input of the first element And block smoothing, the output of which is connected with a summing input of the first reversible counter with the second inputs of the second and third elements And, moreover, the output of the second element And is connected to a subtractive input of the second reversible counter, and the output of the third element And its summing input, information output of the first reversible counter is connected with the second inputs of the first and second blocks of the Comparators, the inverse of the information output of the second reversible counter connected to the second input of the adder, and direct access to the information input unit forecast, single channel subunit smoothing containing an adder, connected in series with the register, the output of which is connected to the input of the second reversible counter of the smoothing bus register is connected to pulsing the input device, and the input of the adder is connected to the information input device; node clocking unit forecast containing a delay element, a trigger generator element And the shift register on the low-order, which has instituted a logical one ("1"), and bus write it in the shift register is connected to a pulsing input device, to which is also connected to the inputs of delay elements and tire installation in "0" trigger bus installation 1 which is connected to the output of the delay element, and a single output ("1") flip-flop connected to the first input element And a second input connected to the output of the generator, the output element And is connected to the bus shift register, the outputs of the least significant bits of which are the outputs of the node clocking block prediction;

unit forecast that contains serially connected first, second and third myCitadel, each of which contains a block of register memory for storing ordinate background predictable process, multiplexer, block inverter and adder, all vychitala outputs of serially connected registers of the memory block is pulled to the information inputs of the respective multiplexers, and outputs the latter to the inputs of respective units of inverters whose outputs are connected to inputs of the second summand corresponding adders these vychitala, information which was output block smoothing is connected to the input of the register memory of the first vicites and to the input of the first addend adder of the first myCitadel, and with mounting offset tires on one digit toward the high-order bits of the adder output multiplexer of the first vicites connected to the input of the register memory of the second vicites and inputs the first summand of the adders of the second and third vychitala, and with mounting offset tires on one digit in the direction of the senior ranks of these adders, and the output multiplexer of the second vicites connected to the input of the register memory of the third myCitadel, the address register y prehistory, specifying the time (interval) of the forecast, the entrance of which is the second managing input device and the output is connected to a bitwise combined address bus multiplexers of all three vychitala;

the first subunit of the forecast, containing a block of inverters, the first, second and third adders, the output of the third adder subunit is the first information output device for estimating a quadratic prediction of non-stationary discrete input sequence.

the second subunit of the forecast, including the adder, the output of which is wound on the second information output device for estimating a linear prediction of stationary or slowly changing input discrete sequence, to solve this problem the output of the adder of the third vicites connected to the input of the second term of the first is umutara first subunit forecast the sign of the first term of which is connected to the output of the first multiplexer myCitadel, the output of the first adder subunit is connected to the input of the unit inverters, mounting shift output buses on one digit toward the least significant bits of the adder, and the output unit of the inverter is pulled to the entrance of the second term of the third adder, the input of the first term of which is connected to the output of the second adder, a first input element connected to the output of the adder of the first myCitadel, and the sign of the second term with the output of the adder of the second myCitadel, the output of the third adder of the first subunit is pulled to the first information output device for estimating a quadratic prediction of non-stationary discrete input sequence, the input of the first addend adder of the second subunit of the forecast is connected to the output of the adder of the first myCitadel, the sign of the second term of the adder is connected to the output of the adder of the third myCitadel, and the output of the adder of the second sub routine with mounting shift its output buses on one digit toward the least significant bits of the adder to the second information output device for estimating a linear prediction of stationary or slowly varying discrete input sequence.

Figure 1 shows the block diagram of the device; figure 2 - block diagram block SGL the provision; figure 3 - block diagram single channel subunit smoothing; figure 4 - block diagram of the node clocking block prediction; figure 5 - block diagram block prediction; figures 6 and 7 shows the graphs of the results of the simulation of the modified operators forecast according to the data presented in table 1; table 2 shows the results of the evaluation of the accuracy of empirical formulas modified operator forecast on analytic functions.

Known formulas operators forecast obtained analytically using the approximating polynomials on four points ordinate the prehistory of the input discrete random process by the method of least squares (Milne VE Numerical analysis. M., "IL", 1951, str).

The operator forecast on approximarely the second order polynomial (quadratic) four-point ordinate background [KW] is

The operator forecast on approximarely the first-degree polynomial (linear) four-point ordinate background is

where y_{p}the first (current) design point (ordinate);

y_{p-1}, y_{p-2}, y_{p-3}respectively, second, third and fourth reference point (ordinate) three-level background input smoothed discrete sequence. In numerical analysis is the system of equally spaced points in increments of N,
real-time N interval between y (points), i.e. the time (depth) of the forecast.

Implementation of operators in formulas (1) and (2) possible at the computing device based on a microprocessor to perform arithmetic operations and data exchange with RAM (or ROM), which stores the coefficients for the ordinate Y_{n-i}in equations (1) and (2). For such devices are characterized by a large volume of equipment, complex circuit switching units and relatively low speed (arithmetic operations are performed, usually in mode floating point).

The basis of the synthesis of the proposed prediction device based on the requirements of the technical simplicity of implementation and high performance. One way of solving this problem is the modification operators forecast equations (1) and (2) so that arithmetic operations with floating-point were replaced by integer arithmetic operations with coefficients in y that are multiples of degree two. For example, multiplication by 2 is replaced by a shift of the operand to the left by one digit, multiplying by 1/2 (divide in half) - one digit to the right, etc. it is Obvious that this procedure may result in some loss of accuracy of the forecast, but (as will be shown below) in a quite acceptable range.

Now based arithmeticerror the device calculations will be only one structural element - the adder, and the operation of the shift in the latter, in turn, can replace the mounting offset tires operand before it is entered into the adder (or when the output of the summation of it), in particular:

(a) multiplying the operand by 2 - mounting the shift input of tyres summand on one digit toward the high-order bits of the adder;

b) multiplying the operand by 1/2 - mounting shift input tyres summand on one digit toward the least significant bits of the adder.

On the block diagram of the proposed device (see figure 5) such installation operations indicated by the circle.

Based on the obtained analytically operator quadratic

forecast [T], (equation (1)) will make the following empirical equation modified operators [KW]:

Continue the modification operators [M1], [M2], [M3] and [LN]:

Empirical equations (6) and (9) modified operators forecast [M1] and [LN] implemented in the prototype.

By analogy with the methods of the calculus of finite differences for numerical differentiation, interpolation and extrapolation denote

Δy_{1}=(2y_{p}-y_{p-1}) - as birdnote the first level is registrie discrete input sequence,
i.e. the difference between twice the current and previous ordinate process;

Δy_{2}=(2y_{p-1}-y_{p-2}- birdnest second level background;

Δy_{3}=(2y_{n-1}-y_{p-3}- birdnest third level background.

Given the above notation, the empirical equation(6), (7), (8) and (9) modified quadratic operators [KW] and linear [LN] predictions can be written as follows:

Analysis of the simulation results (see table 1) operation of the modified operators quadratic prediction [M1], [M2] and [M3] on empirical formulas (10), (11) and (12) and evaluate the accuracy of these formulas according to the forecast of analytic functions in table 2 allow one to choose the optimal variant of implementation of the operators forecast that meets the task, namely to improve forecast accuracy and simplification of the device in comparison with analogues and prototype. This statement quadratic prediction [M3] empirical formula (12) and the linear operator forecast [LN] empirical formula (13). If the accuracy (reliability) of the prediction operator [T] (formula 1)is conventionally taken as 100%, the accuracy of the prediction of the modified operator [M3] will be (see table 1 on average (96-98)%. This indicator can be considered quite acceptable for most technical applications, for example for anticipation and tracking of ballistic objects for monitoring and control of technological processes in DCS and others, and some loss in the accuracy of prediction is more than compensated by the simplicity and high performance of a prediction device.

The device comprises (see figure 1) digital block smoothing 1 and unit forecast 2. Block smoothing 1 contains (see figure 2), the adder 3, the inverter 4, the first and second blocks Comparators 5.1 and 5.2, the first item And 6, the first reversible counter 7; unit 8 set the ratio of the variances, which contains the register 9, the counter 10 and the delay element 11; the second and third elements 12.1 and 12.2, the second reversible counter 13, an inverter 14; unit 15 to control the dynamic characteristics containing the first and second pulse shapers 16.1 and 16.2, the element OR 17, the counter 18, the first item 19.1, the second element And 19.2 and the trigger 20; an information input unit 21 and smoothing device, a first control 22 and pulsing 23 inputs the device and block smoothing; single subunit smoothing 24 (see figure 3), containing the adder 25 and a register 26; information output 27. Node clocking 28 unit forecast contains (see figure 4) delay element 29, the trigger 30, the generator 31, the And gate 32 and the register ndwiga. The block prediction 2 (see figure 5) contains the first 34 and second 35 and third 36 myCitadel, each of which contains a block of register memory 37 of the (A) series-connected registers 38, multiplexer 39, the unit inverters 40 (assuming that the multiplexer does not have inverted outputs) and the adder 41, the first subunit 42 forecast, containing a block of inverters 43, the first 44 and second 45 and third adders 46, the output 47 of the third adder subunit is the first information output device; a second subunit 48 containing the adder 49, the output of which is connected to the second information output device 50; case 51 address (A) ordinate reference points prehistory predictable process, the input 52 which is the second managing input device that specifies the time of the forecast H=AT

(T - cycle operation, And the maximum address register (cell) block register memory 37).

Block smoothing 1 (see figure 2) implements the following modification of the operator's signature exponential smoothing:

where x_{p}and y_{p}- input and output samples;

α=1/K - constant smoothing;

For parameter adaptation.

As a criterion of effectiveness (accuracy) smoothing the selected ratio d between zero and the actual deviations Δx_{p}=(x_{p}-y_{p-1}). Latter Ormerod current single increment output graduated increments in (14):

sign[Δx_{p}/K]=1 if [Δ_{p}-To]>0,

sign[Δx_{p}/K]=0 if [Δ_{p}-To]<0.

Block smoothing works in two modes: fixed and dynamic (transient), and all operations are performed in a single cycle. In the first mode, the device smoothes the input random sequence increments to the level specified by the value d, which is filled in before you begin with the first control input 22 in register 9 block 8. The latter is a controlled frequency divider, for example, for d=7 the output direct transfer counter 10 appears every seventh clock pulse (entry 23), through which the delay element 11 rewrites the code d from the register 9 in the counter 10 (for the next cycle of operation of the divider), and subtracts "1" from the first reversible counter 7, containing the code of the parameter adaptation K.

The process of adaptive smoothing is as follows. Let (at a certain code To the meter 7) increased the variance of the input digital signal, i.e., increased the number of valid deviations Δx_{p}(both characters). After comparing them with the option of adapting To output blocks of the Comparators are set to logical "1" (mode Comparators: [Δ_{p}>]="1", [Δ_{p}<K]="0"). As in the stationary mode, the trigger 20 is in the state "0", with its inverted output to perveived the first item And 6 also receives a logical "1".
The high level signal on all inputs of the first item And 6 permit the passage of clock signals from the input 23 of the summing input of the first reversible counter 7 (code To increases in the last) and second input elements And 12.1 and 12.2. The output signal from one of them (depending on the sign of the deviation) is fed to a summing (or subtractive) the input of the second reversible counter 13, ie signature function (14). The growth process will continue until, until dynamic equilibrium, i.e. the number of pulses received from block 6 to the subtractive input of the reversible counter 7 will be equal to the number of pulses received at its summing input element And 6, and the output variance of the smoothed discrete sequence will remain unchanged (for d=7: one valid deviation should be seven zero).

Unit 15 controls the dynamic response (BUDH) automatically switches the device from the stationary mode of smoothing the transition (dynamic) and back. The transition mode can be caused by the acceleration curve, the transition from one mode to another (for some groups of objects of control or management, for example, ballistic, stationary mode may be a special case of dynamic). For a stationary random process likely is any of a series,
for example, of the eight deviations (from the mean) one sign the contract (in accordance with a geometric probability distribution) is very small. Therefore, this series due to the beginning of the transition mode. BUDH 15 records this series and works as follows. As for the stationary mode, the most probable deviation of different signs, then the sign changes in the adder 3 with plus to minus and Vice versa appropriate driver 16.1 or 16.2 produces a pulse through the OR element 17 resets to "0" the counter 18 and the trigger 20. In dynamic mode (the formers 16 do not work) on the counter 18 (for example, 4-bit) will receive eight consecutive pulses from clock input 23. Output high-order bit of the counter 18 will set the logic "1", a high level which will ensure passing through the first element And 19.1 pulsing pulse, which will set the trigger 20 to "1". The last signal from the inverted output will not allow the device is in the stationary mode (logical "0" at the first input of the first element And 6), and a high level of direct access will be allowed through the second element And 19.2 overwrite discretes single subunit smoothing 24 in the second reversible counter 13, i.e. at the output 27 of the block 1 with a minimum degree of smoothing (α=^{1}/_{2}). At the end of the transitional regime summator 3 will inevitably arise deviations of different signs,
that will lead to the triggering of the formers 16 and, respectively, to the switching of the trigger 20 in the state "0" (fixed smoothing mode). The subunit 24 works on both modes in accordance with equation Y_{p}=^{1}/_{2}X_{p}+^{1}/_{2}The_{p-1}and is triggered by clock pulses from input 23 in register 26, but is used only for transient (dynamic) mode, by recording the output of minimally smoothed discretes from the register 26 in the second reversible counter 13 is also a clock signal input 23, but through the second element And 19.2 block BUDH 15.

Introduced in the proposed prediction unit smoothing 1 has less equipment than in the prototype, performs a smoothing operation in a single cycle (prototype - three), provides smooth smoothing (α=1K, K=2, 3, 4, 5, ...; α=12, 13, 14, 15, ...), in the prototype smoothing - speed (0=1/2^{K}To=2, 3, 4, 5, ...; α=14, 18, 116, 132, ...) and, finally, has a greater degree of reliability: working with the token and not with the magnitude of the deviation, i.e. not sensitive to failures in the input data.

The operation of the forecasting is performed in three steps, respectively, of the 2nd, 3rd and 4th. They are formed by a series of three pulsing pulses from node clocking 28 (see figure 4). Pulsing the pulse from input 23 clears the trigger 30, and writes "1" in the low-order DM is igopogo register 33.
The same pulsing pulse, delayed by the delay element 29 is set to "1" trigger 30, thus allowing the passage of pulses from the oscillator 31 through the element 32 in the shift register 33, tires younger categories ("a", "b", "C", and so on) and appears consistently above series. In the 2nd step of recording the output current (first) design points y_{p}in the first register block 38 37 registered memory first vicites 34. At the same time overwrites (shift) all the preceding y in adjacent registers 38. The address input of the multiplexer 39 is supplied address code (A), the ordinate of prehistory and the register 51, recorded from the second control input 52 before you begin the device and specifying the time (interval) prediction N=AT. In accordance with this address, the y output of multiplexer 39 (as the second design point y_{p-1}) through the power inverter 40 is fed to the input of the second term of the adder 41, at the entrance of the first term of which is a double ordinate of the previous design point y_{p}. At the output of the adder of the first vicites 34 is set birdnest 1 level prehistory discrete input sequence.

In the 3rd and 4th beats are produced by operations similar to those described above, but for the second 35 and third 36 vychitala, outputs to the x set, accordingly, birdnote the 2nd and 3rd levels of prehistory. All the adders in the device - Raman. Upon completion of the 4th beat of the output 47 subunit 42 in accordance with the empirical formula (12) code set evaluation quadratic (non-linear) prediction for nonstationary discrete input sequence and the output is 50 48 sub in accordance with formula (13) code of estimating linear prediction for stationary or slowly varying discrete input sequence.

The use of both operators forecast for monitoring, tracking, or management options in technical systems is based on fundamental physical laws: the laws of inertia, the laws of conservation of energy and motion, the inertia of the heating/cooling and other that allows you to count on a high degree of reliability prediction. About the accuracy of the forecast can only be judged at the completion of the event and if in the time period (interval) of the forecast was not of force majeure: strike, jump, blast, etc.

Digital prediction device containing the block smoothing, which consists of an adder, a first input of which is an information input device, the first and second blocks of the Comparators, the input of which is connected to the output of the sum of the ora,
with the first comparator directly, and the second through a unit inverter unit assignments ratio deviations, containing (as a controllable frequency divider) register, a counter and a delay element, information and clock inputs of the block are the first Manager and the clock inputs of the device, respectively; the first element And the first input of which is connected to the clock input of the second and third inputs respectively to the outputs of the first and second blocks of the Comparators, the first reversible counter, a subtractive input connected to the output of unit assignments ratio of variances, the inverter, the second and third elements And the second reversible counter of the smoothing and control unit dynamic characteristics (BUDH), the first input of which is connected to the first input of the third element And to the output of the inverter, the second input is connected to the first input of the second element And the input of the inverter and the output of the sign digit of the adder, and the first output BUDH connected to the reset input to "0" first and to the bus entry of the second reversible counter, and BUDH contains an element OR counter, the trigger, the first and second elements And the first and second pulse shapers, the inputs of which are the first and second inputs BUDH through pulse shapers connected to both inputs of the OR element, the output of which soy is inen tires reset to "0" of the counter and trigger
the input set to "1" which is connected to the output of the first element And the first input of which is connected with the senior discharge counter and a second input from a clock input of the counter and the device and the second input of the second element And the first input of which is connected to the direct trigger output and inverted output of the last - to the fourth input of the first element And block smoothing, the output of which is connected to a summing input of the first reversible counter with the second inputs of the second and third elements And, moreover, the output of the second element And is connected to a subtractive input of the second reversible counter, and the output of the third element And its a summing input, information output of the first reversible counter is connected to the second inputs of the first and second blocks of the Comparators, the inverse of the information output of the second reversible counter connected to the second input of the adder, and direct access to the information input unit forecast, single channel subunit smoothing containing an adder, connected in series with the register, the output of which is connected to the input of the second reversible counter of the smoothing bus register is connected to pulsing the input device and the input of the adder is connected to the information input device;

node clocking unit forecast containing a delay element, three is ger,
the generator element And the shift register on the low-order, which has instituted a logical one ("1"), and bus write it in the shift register is connected to a pulsing input device, to which is also connected to the inputs of delay elements and tire installation in "0" trigger bus installation 1 which is connected to the output of the delay element, and a single output ("1") flip-flop connected to the first input element And a second input connected to the output of the generator, the output element And is connected to the bus shift register, the outputs of the least significant bits which are the outputs of the node clocking block prediction;

unit forecast that contains serially connected first, second and third myCitadel, each of which contains a block of register memory for storing ordinate background predictable process, multiplexer, block inverter and adder, all vychitala outputs of serially connected registers of the memory block is pulled to the information inputs of the respective multiplexers, and outputs the latter to the inputs of respective units of inverters whose outputs are connected to inputs of the second summand corresponding adders these vychitala, information output block smoothing is connected to the input of the register memory of the first vicites and to the input of the first addend adder lane is on myCitadel,
and with mounting offset tires on one digit toward the high-order bits of the adder output multiplexer of the first vicites connected to the input of the register memory of the second vicites and inputs the first summand of the adders of the second and third vychitala, and with mounting offset tires on one digit in the direction of the senior ranks of these adders, and the output multiplexer of the second vicites connected to the input of the register memory of the third myCitadel, the address register y prehistory, specifying the time (interval) of the forecast, the entrance of which is the second managing input device and the output is connected to a bitwise combined address bus multiplexers of all three vychitala;

the first subunit of the forecast, containing a block of inverters, the first, second and third adders, the output of the third adder subunit is the first information output device for estimating a quadratic prediction of non-stationary discrete input sequence;

the second subunit of the forecast, including the adder, the output of which is wound on the second information output device for estimating a linear prediction of stationary or slowly changing input discrete sequence, characterized in that the output of the adder of the third vicites connected to the input of the second term of the first adder p is pout subunit forecast
the sign of the first term of which is connected to the output of the first multiplexer myCitadel, the output of the first adder subunit is connected to the input of the inverter with the mounting shift output buses on one digit toward the least significant bits of the adder, and the output unit of the inverter is pulled to the entrance of the second term of the third adder, the input of the first term of which is connected to the output of the second adder, a first input element connected to the output of the adder of the first myCitadel, and the sign of the second term with the output of the adder of the second myCitadel, the output of the third adder of the first subunit is pulled to the first information output device for estimating a quadratic prediction of non-stationary discrete input sequence, the input of the first addend adder of the second subunit of the forecast is connected to the output of the adder of the first myCitadel, the sign of the second term of the adder is connected to the output of the adder of the third myCitadel, and the output of the adder of the second sub routine with mounting shift its output buses on one digit toward the least significant bits of the adder to the second information output device for estimating a linear prediction of stationary or slowly changing input discrete sequence.

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FIELD: physics; computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in control and signal processing systems. Technical outcome is achieved due to that, the device contains a unit for storing measurement results, commutators, interval division unit, random number generator, unit for eliminating associated values, ranking unit, storage register for random number samples, approximation units, subtracting units, remainder storage units, units for obtaining an ordered series on intervals, truncated sampling units, units for calculating mean-square deviation, multiplier units, coefficient storage register, coefficient evaluator, unit for setting false alarm probability, comparators, penalty storage units, arithmetic adder, threshold evaluator, comparator, penalty storage register, unit for eliminating anomalous measurements, storage register, delay unit and a clock pulse generator.

EFFECT: detection and elimination of anomalous measurements with a fixed value of false alarm probability.

1 dwg

FIELD: information technology.

SUBSTANCE: present invention relates to digital computer technology and can be used in systems for digital processing radio signals for optimum non-linear filtration. The device has blocks for generating matrix functions (4, 6, 10, 12), corrector units (2, 8), differential generating units (1, 7), summing units (3, 9), delay line (5, 11), unit for generating and output of priori data (13). The device also has a unit for calculating regularisation parametre (14), which is linked to the rest of the units.

EFFECT: more accurate evaluation of the information process in measuring systems.

8 dwg

FIELD: computer science.

SUBSTANCE: device has sum forming blocks, matrix functions forming block, difference forming block, delay lines, apriori data output block.

EFFECT: higher precision.

6 dwg

FIELD: information technology.

SUBSTANCE: present invention relates to digital computer technology and can be used in systems for digital processing radio signals for optimum non-linear filtration. The device has blocks for generating matrix functions (4, 6, 10, 12), corrector units (2, 8), differential generating units (1, 7), summing units (3, 9), delay line (5, 11), unit for generating and output of priori data (13). The device also has a unit for calculating regularisation parametre (14), which is linked to the rest of the units.

EFFECT: more accurate evaluation of the information process in measuring systems.

8 dwg

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in control and signal processing systems. Technical outcome is achieved due to that, the device contains a unit for storing measurement results, commutators, interval division unit, random number generator, unit for eliminating associated values, ranking unit, storage register for random number samples, approximation units, subtracting units, remainder storage units, units for obtaining an ordered series on intervals, truncated sampling units, units for calculating mean-square deviation, multiplier units, coefficient storage register, coefficient evaluator, unit for setting false alarm probability, comparators, penalty storage units, arithmetic adder, threshold evaluator, comparator, penalty storage register, unit for eliminating anomalous measurements, storage register, delay unit and a clock pulse generator.

EFFECT: detection and elimination of anomalous measurements with a fixed value of false alarm probability.

1 dwg

FIELD: computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in systems for controlling and processing multi-dimensional signals. The device comprises a unit for storing input realisation 1, unit for calculating first coefficient 2, unit for calculating second coefficient 3, unit for calculating third coefficient 4, approximation unit 5, unit for evaluating useful component 6 and clock generator 7. Approximation of values of initial discrete realisation of the measured process is done through minimisation of the objective function, which is a sum of mean square deviations of two-dimensional evaluation of useful component from the initial two-dimensional realisation of measurement results.

EFFECT: separate two-dimensional evaluation of useful component given a single realisation of the measured process.

1 dwg

FIELD: computer engineering.

SUBSTANCE: invention relates to digital computer engineering and can be used in digital signal processing systems for optimum nonlinear filtering. The device contains six units for generating matrix functions, three correctors, three units for generating difference, three units for generating sum, three delay lines, unit for generating and outputting prior data, and two units for calculating regularisation parametre.

EFFECT: increased accuracy of evaluating information process parametres in measuring systems.

8 dwg

FIELD: information technology.

SUBSTANCE: proposed invention relates to information measuring devices and can be used in computer engineering, in signal control and processing systems. The devices has a register for storing measurement results (1), delay unit (2), approximation unit (3), register for storing estimations (4), averaging unit (5), control unit (6), clock generator (7), and a comparator unit (8).

EFFECT: pickup of useful signal against a background of noise with minimisation of end effects, in conditions of insufficient prior information on statistical characteristics of adaptive noise and useful signal function given a single realisation of the measuring process.

4 dwg

FIELD: information technologies.

SUBSTANCE: device comprises unit of input realization storage, clock oscillator, control unit, unit of useful signal extraction, unit of storage of five last values of useful component assessment, unit of approximation with polynom of the first degree, unit of approximation with polynom of the second degree, unit of output realization storage. In device end values of assessment are approximated with the help of method of least squares with polynom of the first or second degree, then produced equation of assessment is used to calculate values in forecast points.

EFFECT: forecasting measurement results on the basis of useful signal extraction without end effects, under conditions of limited a priori information about useful and accidental component.

1 dwg

FIELD: information technologies.

SUBSTANCE: device comprises serially connected frequency filter, digitiser and unit of reduction to perfect instrument (RPI), intended for interpolation of counts supplied to its inlet, detection of weight of basic final duration of signals in inlet signal on the basis of interpolated counts decomposition into Fourier series by orthogonalised reactions of frequency filter into basic signals and for formation of outlet signal as a superposition of basic signals with account of their weight in inlet signal, besides versions of device include connection of noise suppression unit or serialy connected unit of signal growth speed assessment and normalisation unit between digitiser and RPI unit.

EFFECT: improved resolution and sensitivity to elements of signal, increased efficiency and simplification of device for signals processing.

4 cl, 12 dwg

FIELD: information technology.

SUBSTANCE: device has a unit for storing input realisation, switches, approximation units, estimation storage units, arithmetic adder, a unit for storing useful component estimates, a control unit, a delay unit, a clock-pulse generator, two units for breaking down into intervals, each having a random number generator, a unit for averaging related values, a ranging unit and a register for storing random number samples. The control unit has a shift register for sampling column random numbers, a shift register for sampling row random numbers, a delay unit for sampling column random numbers, a delay unit for sampling row random numbers, a counter and a unit for checking conditions.

EFFECT: two dimensional estimation of the useful component in conditions with insufficient prior information on statistical characteristics of additive noise and useful component function.

2 dwg

FIELD: physics.

SUBSTANCE: function codes are rounded-off to the nearest level and the obtained codes are stored. The optimality criterion code is calculated and stored. Starting with a certain initial number L of the function code, the direction of rounding-off this code is changed and the optimality criterion code is calculated. If the optimality criterion code falls, the changed value of the code is stored and a new value of the optimality criterion code is calculated and stored, otherwise the initial L-th function code and the initial optimality criterion code are stored, and calculation is moved on to the next number of the function code L+1, where it is checked whether the optimality criterion code falls in the same way as that when the L-th function code was changed. Further, the process is continued until the optimality criterion code does not fall in a sequence of n function codes, read from the code value in which the last fall in the optimality criterion code took place.

EFFECT: reduced absolute error in the amplitude of the reproduced sinusoidal signal.