Start-stop communication system with signal frequency keying

FIELD: information technology.

SUBSTANCE: proposed start-stop communication system pertains to wireless communication and can be used in different communication lines. The start-stop communication system with signal frequency keying has on the transmission side an information source, first shift register, OR circuit, carrier frequency generator, transmitter, first trigger flip-flop, first AND circuit and a pseudorandom sequence generator. On the receiving side, the system has a receiver, frequency discrimination circuit, interrupter switch, matched filter, decision device, pulse former, non-linear element, first adder, delay line, second adder, threshold device, RS-trigger, first key, comparator, second shift register, second key, minimum signal selection circuit, N switches, second trigger flip-flop and a second AND circuit.

EFFECT: increased noise immunity of communication.

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The invention relates to electro - and radio and can be used in wired radio, radio-relay and meteor scatter communication lines.

Known communication system for continuous transmission of discrete information, which before each message is sent "sounding key. If you receive this signal, the receiver opens for registration messages and after administration sends a receipt on the backward channel. Otherwise, the receiver remains closed and the transmitter repeats the message, continuing efforts to obtain the necessary receipts [1]. However, this communication system has a low immunity, and in start-stop mode - an unacceptably high probability of false alarm.

Closest to the technical nature of the proposed communication system is start-stop communication system with frequency shift keying communication [2], adopted for the prototype.

Diagram of the prototype system presented in figure 1, where indicated

on the transmission side:

1 - source of information;

2 - first shift register (PC);

3 - scheme, OR;

4 - generator carrier frequencies (GNC);

5 transmitter;

8 is a pseudo - random sequence generator (gpsa);

at the receiving side:

9 receiver;

10 - frequency discriminator (BH);

11 - breaker;

12 - coherent filter (SF);

13 - solver (RU);

14. the user pulses (PHI);

15 - nonlinear element (ne);

16 - the first adder;

17 - delay line (LPA) with n taps;

18 - the second adder;

19 - threshold unit (PU);

20 - RS-trigger;

21 - the first key;

22 comparator;

23 - the second PC;

24 - the second key;

29 - line.

The system prototype contains on the transmission side, the United information source 1, the first PC 2, scheme, OR 3, GN 4 and the transmitter 5, and gpsa 8, the output of which is connected with the second input of the differential OR 3, and the second output of the information source 1 is connected to a clock input of the first PC 2 and the first input of the gpsa 8, a second input connected to the third output of the information source 1 and the second input of the transmitter 5, and at the receiving side contains, United receiver 9, BH 10, the circuit breaker 11, SF 12, RU 13 and PHI 14, connected in series ne 15, the first adder 16 and LPA 17, connected in series, a second adder 18, the first n inputs of which are connected via the bus to the outputs of 17, and (n+1)-th input is connected to its input; PU 19 and RS-trigger 20; the second key 21 and connected in series to the comparator 22, the second PC 23 and the second key 24, the output of which is the system output, the first output PHI 14 is connected to the clock inputs of the comparator 22 and the second PC 23, and its second output is connected with the second inputs of the circuit breaker 11 and PU 19, BH output 10 is connected to galinou the input of the comparator 22 and the entrance ne 15, the output SF 12 is connected to the first input of the first key 21, the second input of the first key 21 is combined with the output of RU 13 and the second input of the RS flip-flop 20, and its output connected to the second input of the first adder 16, the output of the RS flip-flop 20 is connected with the second input of the second key 24; reception and transmission sides of the system are connected through the communication line 29. The system prototype is as follows.

Information source 1 at a random point in time creates the first output message consisting of n binary symbols of the same duration τ, and the second and third outputs at the beginning of the message grid of S short pulses with a repetition period τ and a positive pulse, respectively. In gpsa 8 is formed of the synchronization signal is a pseudorandom binary sequence consisting of S elements of duration τ, and the message is delayed in the PC 2 at a time equal to Sτ. As a result, the output of the circuit OR 3 is formed of a sequence of clock and messages. The elements of these signals are used to control the frequency GNC 4. The received frequency-shift keyed signal is amplified in the transmitter 5, the switched pulse duration (n+S)τ, acting on the third output of the information source 1, and is transmitted through the communication line 29.

At the receiving side after total filtering in the receiver 9 carries out who I am demodulation of the received signal in BH 10 and matched filtering clock in SF 12, which together with the unit 13 is the first measuring channel, which represents the optimal measurement device to the provisional regulations of the clock (see, for example, p.115, is in the book Justina "introduction to theory and technique of radio systems", M., "Radio communication, 1986).

In RU 13 compares the input signal with a threshold and, if it is exceeded, a signal is formed at the moment of its maximum value a short pulse, which in the absence of noise exactly coincides with the end of the clock at the reception. On the positive edge of this pulse on the first output PHI 14 with a delay time τ creates a grid of 2n short clock pulses of duration α (α<<τ) with period τ, and the second - pulse duration nτ+2α, who with the help of circuit breaker 11 disables the input SF 12 from the output of block 10. In the comparator 22 in the moment of action the first n output clock pulses of the block 14 by the sign of the output signals BH 10 decisions on admission n binary symbols of the message are the same pulses are recorded in the (n+1)-bit PC 23, the next n clock pulses read out the information from the PC 23 to the first input of the second key 24. The output signal SF 12 in the point of action of the output pulse RU 13 with the first key 21 via the first adder 16 is supplied in L with n taps, the distance between them (in time) is equal to τ.

In ne 15 calculates the modular element values of the output signal BH 10, which through the same adder 16 is fed to the input of the 17. Then the input signal LPA 17 and output signals with n its outputs are added in the second adder 18 and the received signal at the moment of action of the trailing edge of the pulse at the second output PHI 14 is compared in PU 19 with a certain threshold. Provided exceeded his threshold RS-trigger 20 set output pulse RU 13 in the zero state, is translated in one state. This opens the key 24 and information with its first input is transferred to its output. If the threshold in PU 19 signal is not exceeded, the input unit 24 on his way out to do will not.

The lack of a prototype system - low immunity due.

The invention aims to improve the noise immunity of communication.

To achieve this in start-stop communication system with frequency shift keying signal (SSCM), containing on the transmission side connected in series source of information, the first PC, the scheme OR, GNC and transmitter, and gpsa, the output of which is connected with the second input circuit OR the second output information source connected to a clock input of the first PC and the first input of the gpsa, the second input of the gpsa is connected with the third output of the source of information is and the second input of the transmitter, and at the receiving side is connected in series receiver, BH, breaker, SF, RU and PHI; connected in series ne, the first adder and LPA; sequentially connected to the second adder, the first n inputs of which are connected via the bus to the n outputs of the and (n+1)-th input is connected to the input of the threshold device and the RS-trigger; a first key and a comparator connected in series, the second PC and the second key, the output of which is output SCCM, and the first release of PHI is connected to the clock inputs of the comparator and the second PC, and it the second output is connected with the second inputs of the circuit breaker and PU, BH output connected to the signal input of the comparator and the input of the ne, the output SF is connected to the first input of the first key, the second input of the first key is combined with the output of the PN and the second input of the RS flip-flop and the output of the first key is connected to the second input of the first adder, the output of the RS flip-flop is connected to the second input of the second key; reception and transmission sides SCCM connected through a communication line, according to the invention is introduced on the transmission side: the fourth output of the information source, the third input of the circuit OR connected in series to the first flip-flop and the first circuit And the second input of which is connected to the fourth output of the information source, and the output connected to the third input of the circuit OR, and the counting input of the first T-flip-flop connected to the output of the first PC, and its installation input to the third output of the information source, and at the receiving side further introduced: (n+1)-th tap of LPA, 2n installation of inputs and n outputs of the second PC (n+2)-th input of the second adder connected to the (n+1)-th tap of LPA, a scheme of selecting the minimum signal (RAS), connected to n inputs via the bus with the first n outputs of the and (n+1)-th - with the input of the LPA, n switches, each of which is connected to the first the input with the corresponding output of the SVM, the second - with the corresponding output of the second PC, and a pair of outputs from the respective pair of the installation of the inputs of the second PC; sequentially connected to the second flip-flop, connected to a counter input to the comparator output, and adjusting the input to the output of the RU, and the second circuit And the output of which is connected to the gate input of SVM, and the second input - output PU.

Figure 2 presents a functional diagram of the proposed SCCM.

It contains on the transmission side connected in series source 1, the first PC 2, scheme, OR 3, GN 4 and the transmitter 5; sequentially connected to the first flip-flop 6 and the first schema And 7, the second input of which is connected to the fourth output of the information source 1 and the output to the third input schema OR 3, with the counting input of the first T-flip-flop 6 is connected to the output of the PC 2, and its installation entrance combined with the third output of the information source 1 and the second is the input of the transmitter 5; Gpsa 8, the first input of which is combined with a clock input of the PC 2 and connected to the second output of the information source, the second input is connected to the third output of the information source 1, and the output connected to the second input of the differential OR 3, and at the receiving side contains, United receiver 9, BH 10, the circuit breaker 11, SF 12, RU 13 and PHI 14; connected in series ne 15, the first summator 16 and LPA 17; sequentially connected to the second adder 18, the first n inputs of which are connected via the bus to the n outputs of the 17, (n+1)the first input is connected to the input of the LPA 17, and (n+2)-th to (n+1)-th output LPA 17, PU 19 and RS-trigger 20; the first key 21 and connected in series to the comparator 22, the second (n+2)-bit PC 23 and the second key 24, the output of which is output SCCM, and the first output PHI 14 is connected to the clock inputs of the comparator 22 and the second PC 23, and its second output is connected with the second inputs of the circuit breaker 11 and PU 19, exit BH 10 is connected to the signal input of the comparator 22 and the ne entrance 15, the output SF 12 is connected to the first input of the first key 21, the second input is combined with the output of RU 13 and the second input of the RS flip-flop 20, and its output connected to the second input of the first adder 16, the output of the RS flip-flop 20 is connected with the second input of the second key 24; and contains: RAS 25 connected to n inputs via the bus with the first n outputs LPA 17, and (n+1)-th - the entrance LPA 17, n switches (26-1)-(26-n, each of which is connected to the first input with the corresponding output of the SVM 25, the second with the corresponding output of the PC 23 (starting with the second digit), and a pair of outputs from the respective pair of mounting inputs PC 23 (beginning with a pair of installation of the inputs of the second category); connected in series to the second flip-flop 27 is connected to a counting input connected to the output of the comparator 22, and the installation of the entrance to the exit RU 13, and a second circuit 28, the output of which is connected to the gate input of SVM 25, and the second input - output PU 19; reception and transmission side SSCM are connected through the communication line 29.

Start-stop communication system with frequency shift keying signal is as follows.

Information source 1 at a random point in time creates the first output message consisting of n binary symbols of the same duration τ, the second and third outputs at the beginning of the message grid of S short pulses with a repetition period τ and a positive pulse, respectively, and the fourth pulse duration τ at the time of the last pulse at its second output.

In gpsa 8 is formed of the synchronization signal is a pseudorandom binary sequence consisting of S elements of duration τ, and the message is delayed in the PC 2 at a time equal to Sτ.

If the number of symbols "1" in the message is odd, the trigger 6, set the front edge of the pulse, the current at the third output of the information source 1 in state "0", state is "1" and this signal passes through the first circuit And 7 on the third input schema OR 3 pulse from the fourth output of the information source 1, which is the verification code symbol. When there is an even number of symbols "1" in the message pulse to the third input schema OR 3 will not arrive. As a result, at the output of the circuit OR 3 is formed of a sequence of clock, messages, and the symbol "1" or "0" (depending on the number of symbols "1" in the message). The elements of these signals are used to control the frequency GNC 4. The received frequency-shift keyed signal is amplified in the transmitter 5, the switched pulse duration (n+S+1)τ, acting on the third output of the information source and is transmitted through the communication line 29.

At the receiving side after total filtering in the receiver 9 is the demodulation of the received signal in BH 10, and matched filtering of the clock - SF 12, which together with the unit 13 is the first measurement channel is the same as in the system prototype. In RU 13 compares the input signal with a threshold and, if it is exceeded, a signal is formed at the moment of its maximum value a short pulse, the longer the spine of α, which in the absence of noise exactly coincides with the receipt of the synchronization signal when receiving. On the positive edge of this pulse on the first output PHI 14 with a delay time τ creates a grid of [(n+1)+n] short clock pulses of duration α with period τ, and the second output - pulse duration (n+1)τ+0,5α, who with the help of circuit breaker 11 disables the input SF 12 from the output of block 10. In the comparator 22 in the moment of action fore fronts of the first (n+1) output clock pulses of the block 14, the sign of the output signals BH 10 decisions on admission n binary symbols of the message and the verification code symbol, which is the same pulses are recorded in the (n+2)-bit PC 23. The output signal SF 12 in the point of action of the output pulse RU 13 with the first key 21 via the first adder 16 is supplied in LPA 17 with (n+1) taps, the distance between them (in time) is equal to τ.

In ne 15 calculates the modular element values of the output signal BH 10, which through the same adder 16 is fed to the input of the 17. Then the input signal LPA 17, the output signals from the first n its inputs (bus) and the output signal (n+1)-th additional outputs are added in the second adder 18 and the received signal at the moment of action of the trailing edge of the pulse at the second output PHI 14, are compared in PU 19 with a certain threshold. Provided exceeded his threshold RS-TRG is R 20, set the output pulse RU 13 in the zero state, is translated in one state. This opens the key 24. If the threshold in PU 19 signal is not exceeded, the key 24 is not opened. The blocks 25, 26, 27 and 28 are intended to detect and correct single errors in the received code combination. For this purpose, the inputs of SVM 25 serves input LPA 17 and its output signals (bus) with n first taps, and the first input of the second T-flip-flop 27 - (n+1) output binary symbols of the block 22. If the number of symbols "1" is thus odd (indicating distortion noise code combinations), then the output of the second circuit And 28 at the time of actions leading edge of the output signal PU 19 will operate the voltage drop in the SVM 25 will sample numbers of the output signal with the lowest level, so that only one of its outputs will be valid pulse level "1"and all the rest zero signal.

This pulse arrives at the input of the corresponding switch 26, to the second input of which is applied the output signal of the corresponding category of the PC 23 and, if the level is, for example, will be equal to "1", the pulse from the first input of the switch will go to one of the pair of its outputs, which will set the appropriate category of PC 23 in the opposite position. So will fix mistaken what about the character. The last n output pulses from the first output PHI 14 information from the PC 23 is read via the public key 24 to the output of the communication system. Naturally, this method of error correction is not possible to correct them with probability equal to one. However, calculations showed that when the real signal to noise in the communication channel 12-14 dB the probability of erroneous reception of the message is smaller than in the system prototype. Moreover, the comparison of the two systems was carried out with the same energy consumption during transmission. This advantage of the proposed system in comparison with the known illustrate curves of the probability of erroneous reception of the message P (n=12) from the ratio h (where the dashed line plotted curve for the proposed system, and the solid - known)obtained by the method of statistical simulation.

Thus, the application of the proposed start-stop communication system with frequency shift keying signal can improve the noise immunity of communication.

Sources of information

1. Kanevsky SM, Ledovskikh VI transmission of a discrete channel information feedback interrupts. "Electrosvyaz", No. 2, 1970

2. Gbolahan, Viedensky. About immunity start-stop communication system with frequency shift keying signal. "Theory and technique of radio communication", vol.No. 2, 1998

start-stop communication system with frequency shift keying signal, containing on the transmission side connected in series source information, the first shift register circuit OR generator of carrier frequencies and transmitter, as well as the pseudo-random sequence generator, the output of which is connected with the second input circuit OR the second output information source connected to a clock input of the first shift register and the first input of the pseudo-random sequence generator, a second input of the pseudorandom sequence generator connected to the third output of the information source and the second input of the transmitter and at the receiver side is connected in series receiver, a frequency discriminator, a breaker, a coherent filter, solver and the pulse shaper; connected in series non-linear element, the first adder and the delay line; sequentially connected to the second adder, the first n inputs of which are connected via the bus to the n outputs of the delay line and (n+1)th input is connected to the input of the delay line, a threshold device and RS-trigger; a first key and a comparator connected in series, the second shift register and the second key, the output of which is output communication system, and the first output of the pulse shaper is connected to the clock inputs of the comparator and the second shift register, and its second output is connected to storieskagome breaker and threshold device, the output of the frequency discriminator connected to the signal input of the comparator and the input of the nonlinear element, the output of the matched filter connected to the first input of the first key, the second input of the first key is combined with the output of a casting device and the second input of the RS flip-flop and the output of the first key is connected to the second input of the first adder, the output of the RS flip-flop is connected to the second input of the second key; reception and transmission side of the communication system are connected through a communication line, characterized in that it introduced at the transmitting side: a fourth output of the information source, the third input of the circuit OR connected in series to the first flip-flop and the first circuit And the second input of which is connected to the fourth output of the information source, and the output connected to the third input of the circuit OR, and the counting input of the first T-flip-flop connected to the output of the first shift register and its installation input to the third output of the information source, and at the receiving side further introduced: (n+1)-th tap of the delay line, 2n installation of inputs and n outputs of the second shift register, (n+2)-th input of the second adder connected to the (n+1)-th tap of the delay line, scheme of minimum signal connected to n inputs via the bus with the first n outputs of the delay line and (n+1)-m - with the input of the delay line, n switches, each of which connection is replaced by the first input with the corresponding output of the minimum selection signal, second - with the corresponding output of the second shift register, and a pair of outputs from the respective pair of the installation of the inputs of the second shift register; sequentially connected to the second flip-flop, connected to a counter input to the comparator output and the installation of the entrance to the exit of the casting device, and the second circuit And the output of which is connected to the gate input circuit of the choice of the minimum signal and the second input with the output of the threshold device.